[gcc r11-3287] [PATCH 3/5][Arm] New pattern for CSINC instructions

[gcc r11-3287] [PATCH 3/5][Arm] New pattern for CSINC instructions

[Omar Tahir]

https://gcc.gnu.org/g:778f19ff953792702c0a7e1fde00214709d9317e

commit r11-3287-g778f19ff953792702c0a7e1fde00214709d9317e
Author: Sudi Das <sudi.das@arm.com>
Date:   Fri Sep 18 16:30:11 2020 +0100

    [PATCH 3/5][Arm] New pattern for CSINC instructions
    
    This patch adds a new pattern, *thumb2_csinc, for generating CSINC
    instructions. It also modifies an existing pattern, *thumb2_cond_arith, to
    output CINC when the operation is an addition and TARGET_COND_ARITH is true.
    
    gcc/ChangeLog:
    
            * config/arm/thumb2.md (*thumb2_csinc): New.
            (*thumb2_cond_arith): Generate CINC where possible.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/csinc-1.c: New test.
    
    Co-authored-by: Omar Tahir <omar.tahir@arm.com>

Diff:
---
 gcc/config/arm/thumb2.md               | 19 +++++++++++++++++++
 gcc/testsuite/gcc.target/arm/csinc-1.c | 23 +++++++++++++++++++++++
 2 files changed, 42 insertions(+)

diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md
index d648ba1da53..0ff5a537f8f 100644
--- a/gcc/config/arm/thumb2.md
+++ b/gcc/config/arm/thumb2.md
@@ -744,6 +744,10 @@
       return \"%i5\\t%0, %1, %2, lsr #31\";
 
     output_asm_insn (\"cmp\\t%2, %3\", operands);
+
+    if (GET_CODE (operands[5]) == PLUS && TARGET_COND_ARITH)
+      return \"cinc\\t%0, %1, %d4\";
+
     if (GET_CODE (operands[5]) == AND)
       {
 	output_asm_insn (\"ite\\t%D4\", operands);
@@ -952,6 +956,21 @@
    (set_attr "predicable" "no")]
 )
 
+(define_insn "*thumb2_csinc"
+  [(set (match_operand:SI 0 "arm_general_register_operand" "=r, r")
+        (if_then_else:SI
+         (match_operand 1 "arm_comparison_operation" "")
+         (plus:SI (match_operand:SI 2 "arm_general_register_operand" "r, r")
+                  (const_int 1))
+         (match_operand:SI 3 "reg_or_zero_operand" "r, Pz")))]
+  "TARGET_COND_ARITH"
+  "@
+   csinc\\t%0, %3, %2, %D1
+   csinc\\t%0, zr, %2, %D1"
+  [(set_attr "type" "csel")
+   (set_attr "predicable" "no")]
+)
+
 (define_insn "*thumb2_movcond"
   [(set (match_operand:SI 0 "s_register_operand" "=Ts,Ts,Ts")
 	(if_then_else:SI
diff --git a/gcc/testsuite/gcc.target/arm/csinc-1.c b/gcc/testsuite/gcc.target/arm/csinc-1.c
new file mode 100644
index 00000000000..b9928493862
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/csinc-1.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_arch_v8_1m_main_ok } */
+/* { dg-options "-O2 -march=armv8.1-m.main" } */
+
+int
+test_csinc32_condasn1(int w0, int w1, int w2, int w3)
+{
+  int w4;
+
+  /* { dg-final { scan-assembler "csinc\tr\[0-9\]*.*ne" } } */
+  w4 = (w0 == w1) ? (w2 + 1) : w3;
+  return w4;
+}
+
+int
+test_csinc32_condasn2(int w0, int w1, int w2, int w3)
+{
+  int w4;
+
+  /* { dg-final { scan-assembler "csinc\tr\[0-9\]*.*eq" } } */
+  w4 = (w0 == w1) ? w3 : (w2 + 1);
+  return w4;
+}