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From: Andrea Corallo <akrl@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc r10-8793] aarch64: Do not alter value on a force_reg returned rtx expanding __jcvt Date: Thu, 24 Sep 2020 09:31:23 +0000 (GMT) [thread overview] Message-ID: <20200924093123.CD29C3857C52@sourceware.org> (raw) https://gcc.gnu.org/g:aa47c987340946034fe9e32832bd1eb49d6287f3 commit r10-8793-gaa47c987340946034fe9e32832bd1eb49d6287f3 Author: Andrea Corallo <andrea.corallo@arm.com> Date: Thu Sep 17 17:17:52 2020 +0100 aarch64: Do not alter value on a force_reg returned rtx expanding __jcvt 2020-09-17 Andrea Corallo <andrea.corallo@arm.com> * config/aarch64/aarch64-builtins.c (aarch64_general_expand_builtin): Use expand machinery not to alter the value of an rtx returned by force_reg. (cherry picked from commit 2c62952f8160bdc8d4111edb34a4bc75096c1e05) Diff: --- gcc/config/aarch64/aarch64-builtins.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/gcc/config/aarch64/aarch64-builtins.c b/gcc/config/aarch64/aarch64-builtins.c index 8407a34b594..b8d301f00e2 100644 --- a/gcc/config/aarch64/aarch64-builtins.c +++ b/gcc/config/aarch64/aarch64-builtins.c @@ -1976,14 +1976,14 @@ aarch64_general_expand_builtin (unsigned int fcode, tree exp, rtx target, return target; case AARCH64_JSCVT: - arg0 = CALL_EXPR_ARG (exp, 0); - op0 = force_reg (DFmode, expand_normal (arg0)); - if (!target) - target = gen_reg_rtx (SImode); - else - target = force_reg (SImode, target); - emit_insn (GEN_FCN (CODE_FOR_aarch64_fjcvtzs) (target, op0)); - return target; + { + expand_operand ops[2]; + create_output_operand (&ops[0], target, SImode); + op0 = expand_normal (CALL_EXPR_ARG (exp, 0)); + create_input_operand (&ops[1], op0, DFmode); + expand_insn (CODE_FOR_aarch64_fjcvtzs, 2, ops); + return ops[0].value; + } case AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V2SF: case AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V2SF:
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