From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2168) id E24B2388A404; Fri, 25 Sep 2020 00:18:13 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org E24B2388A404 Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: GCC Administrator To: gcc-cvs@gcc.gnu.org Subject: [gcc r8-10534] Daily bump. X-Act-Checkin: gcc X-Git-Author: GCC Administrator X-Git-Refname: refs/heads/releases/gcc-8 X-Git-Oldrev: 97c34eb5f57bb1d37f3feddefefa5f553bcea9fc X-Git-Newrev: 5a2283440668f96a537f8a9e3cd5fc659d0643e2 Message-Id: <20200925001813.E24B2388A404@sourceware.org> Date: Fri, 25 Sep 2020 00:18:13 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 25 Sep 2020 00:18:14 -0000 https://gcc.gnu.org/g:5a2283440668f96a537f8a9e3cd5fc659d0643e2 commit r8-10534-g5a2283440668f96a537f8a9e3cd5fc659d0643e2 Author: GCC Administrator Date: Fri Sep 25 00:17:47 2020 +0000 Daily bump. Diff: --- gcc/ChangeLog | 78 +++++++++++++++++++++++++++++++++++++++++++++++++ gcc/DATESTAMP | 2 +- gcc/testsuite/ChangeLog | 72 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 151 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 5697b44a10e..e596b0d7780 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,81 @@ +2020-09-24 H.J. Lu + + Backported from master: + 2020-09-16 H.J. Lu + + PR target/97032 + * cfgexpand.c (expand_asm_stmt): Set sp_is_clobbered_by_asm to + true if the stack pointer is clobbered by asm statement. + * emit-rtl.h (rtl_data): Add sp_is_clobbered_by_asm. + * config/i386/i386.c (ix86_get_drap_rtx): Set need_drap to true + if the stack pointer is clobbered by asm statement. + +2020-09-24 Kyrylo Tkachov + + Backported from master: + 2020-09-24 Kyrylo Tkachov + Andrea Corallo + + PR target/71233 + * config/aarch64/aarch64.md (UNSPEC_FJCVTZS): Define. + (aarch64_fjcvtzs): New define_insn. + * config/aarch64/aarch64.h (TARGET_JSCVT): Define. + * config/aarch64/aarch64-builtins.c (aarch64_builtins): + Add AARCH64_JSCVT. + (aarch64_init_builtins): Initialize __builtin_aarch64_jcvtzs. + (aarch64_expand_builtin): Handle AARCH64_JSCVT. + * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define + __ARM_FEATURE_JCVT where appropriate. + * config/aarch64/arm_acle.h (__jcvt): Define. + * doc/sourcebuild.texi (aarch64_fjcvtzs_hw) Document new + target supports option. + +2020-09-24 Tamar Christina + + Backported from master: + 2019-02-25 Tamar Christina + + PR target/71233 + * config/aarch64/arm_neon.h (vfmlal_low_u32, vfmlsl_low_u32, + vfmlalq_low_u32, vfmlslq_low_u32, vfmlal_high_u32, vfmlsl_high_u32, + vfmlalq_high_u32, vfmlslq_high_u32, vfmlal_lane_low_u32, + vfmlsl_lane_low_u32, vfmlal_laneq_low_u32, vfmlsl_laneq_low_u32, + vfmlalq_lane_low_u32, vfmlslq_lane_low_u32, vfmlalq_laneq_low_u32, + vfmlslq_laneq_low_u32, vfmlal_lane_high_u32, vfmlsl_lane_high_u32, + vfmlal_laneq_high_u32, vfmlsl_laneq_high_u32, vfmlalq_lane_high_u32, + vfmlslq_lane_high_u32, vfmlalq_laneq_high_u32, vfmlslq_laneq_high_u32): + Rename ... + (vfmlal_low_f16, vfmlsl_low_f16, vfmlalq_low_f16, vfmlslq_low_f16, + vfmlal_high_f16, vfmlsl_high_f16, vfmlalq_high_f16, vfmlslq_high_f16, + vfmlal_lane_low_f16, vfmlsl_lane_low_f16, vfmlal_laneq_low_f16, + vfmlsl_laneq_low_f16, vfmlalq_lane_low_f16, vfmlslq_lane_low_f16, + vfmlalq_laneq_low_f16, vfmlslq_laneq_low_f16, vfmlal_lane_high_f16, + vfmlsl_lane_high_f16, vfmlal_laneq_high_f16, vfmlsl_laneq_high_f16, + vfmlalq_lane_high_f16, vfmlslq_lane_high_f16, vfmlalq_laneq_high_f16, + vfmlslq_laneq_high_f16): ... To this. + +2020-09-24 Tamar Christina + + Backported from master: + 2018-05-21 Tamar Christina + + PR target/71233 + * config/aarch64/aarch64-simd.md (aarch64_eor3qv8hi): Change to + eor3q4. + (aarch64_bcaxqv8hi): Change to bcaxq4. + * config/aarch64/aarch64-simd-builtins.def (veor3q_u8, veor3q_u32, + veor3q_u64, veor3q_s8, veor3q_s16, veor3q_s32, veor3q_s64, vbcaxq_u8, + vbcaxq_u32, vbcaxq_u64, vbcaxq_s8, vbcaxq_s16, vbcaxq_s32, + vbcaxq_s64): New. + * config/aarch64/arm_neon.h: Likewise. + * config/aarch64/iterators.md (VQ_I): New. + +2020-09-24 Alex Coplan + + * config/aarch64/aarch64-cores.def: Add Neoverse V1. + * config/aarch64/aarch64-tune.md: Regenerate. + * doc/invoke.texi: Document support for Neoverse V1. + 2020-09-22 Vlad Lazar Backported from master: diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index 52a894dd654..cfe4a2ef954 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20200924 +20200925 diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index d35366fb1ef..b2e821ad7b0 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,75 @@ +2020-09-24 H.J. Lu + + Backported from master: + 2020-09-16 H.J. Lu + + PR target/97032 + * gcc.target/i386/pr97032.c: New test. + +2020-09-24 Kyrylo Tkachov + + Backported from master: + 2020-09-24 Kyrylo Tkachov + Andrea Corallo + + PR target/71233 + * gcc.target/aarch64/acle/jcvt_1.c: New test. + * gcc.target/aarch64/acle/jcvt_2.c: New testcase. + * lib/target-supports.exp + (check_effective_target_aarch64_fjcvtzs_hw): Add new check for + FJCVTZS hw. + +2020-09-24 Tamar Christina + + Backported from master: + 2019-02-25 Tamar Christina + + PR target/71233 + * gcc.target/aarch64/fp16_fmul_high.h (test_vfmlal_high_u32, + test_vfmlalq_high_u32, test_vfmlsl_high_u32, test_vfmlslq_high_u32): + Rename ... + (test_vfmlal_high_f16, test_vfmlalq_high_f16, test_vfmlsl_high_f16, + test_vfmlslq_high_f16): ... To this. + * gcc.target/aarch64/fp16_fmul_lane_high.h (test_vfmlal_lane_high_u32, + tets_vfmlsl_lane_high_u32, test_vfmlal_laneq_high_u32, + test_vfmlsl_laneq_high_u32, test_vfmlalq_lane_high_u32, + test_vfmlslq_lane_high_u32, test_vfmlalq_laneq_high_u32, + test_vfmlslq_laneq_high_u32): Rename ... + (test_vfmlal_lane_high_f16, tets_vfmlsl_lane_high_f16, + test_vfmlal_laneq_high_f16, test_vfmlsl_laneq_high_f16, + test_vfmlalq_lane_high_f16, test_vfmlslq_lane_high_f16, + test_vfmlalq_laneq_high_f16, test_vfmlslq_laneq_high_f16): ... To this. + * gcc.target/aarch64/fp16_fmul_lane_low.h (test_vfmlal_lane_low_u32, + test_vfmlsl_lane_low_u32, test_vfmlal_laneq_low_u32, + test_vfmlsl_laneq_low_u32, test_vfmlalq_lane_low_u32, + test_vfmlslq_lane_low_u32, test_vfmlalq_laneq_low_u32, + test_vfmlslq_laneq_low_u32): Rename ... + (test_vfmlal_lane_low_f16, test_vfmlsl_lane_low_f16, + test_vfmlal_laneq_low_f16, test_vfmlsl_laneq_low_f16, + test_vfmlalq_lane_low_f16, test_vfmlslq_lane_low_f16, + test_vfmlalq_laneq_low_f16, test_vfmlslq_laneq_low_f16): ... To this. + * gcc.target/aarch64/fp16_fmul_low.h (test_vfmlal_low_u32, + test_vfmlalq_low_u32, test_vfmlsl_low_u32, test_vfmlslq_low_u32): + Rename ... + (test_vfmlal_low_f16, test_vfmlalq_low_f16, test_vfmlsl_low_f16, + test_vfmlslq_low_f16): ... To This. + * lib/target-supports.exp + (check_effective_target_arm_fp16fml_neon_ok_nocache): Update test. + +2020-09-24 Tamar Christina + + Backported from master: + 2018-05-21 Tamar Christina + + PR target/71233 + * gcc.target/aarch64/sha3.h (veor3q_u8, veor3q_u32, + veor3q_u64, veor3q_s8, veor3q_s16, veor3q_s32, veor3q_s64, vbcaxq_u8, + vbcaxq_u32, vbcaxq_u64, vbcaxq_s8, vbcaxq_s16, vbcaxq_s32, + vbcaxq_s64): New. + * gcc.target/aarch64/sha3_1.c: Likewise. + * gcc.target/aarch64/sha3_2.c: Likewise. + * gcc.target/aarch64/sha3_3.c: Likewise. + 2020-09-22 Vlad Lazar Backported from master: