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* [gcc r8-10537] Daily bump.
@ 2020-09-26 0:18 GCC Administrator
0 siblings, 0 replies; only message in thread
From: GCC Administrator @ 2020-09-26 0:18 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:bf4ce3fcedf5931f25086aaf9f778fd6c750b3af
commit r8-10537-gbf4ce3fcedf5931f25086aaf9f778fd6c750b3af
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date: Sat Sep 26 00:17:45 2020 +0000
Daily bump.
Diff:
---
gcc/ChangeLog | 120 ++++++++++++++++++++++++++++++++++++++++++++++++
gcc/DATESTAMP | 2 +-
gcc/testsuite/ChangeLog | 17 +++++++
3 files changed, 138 insertions(+), 1 deletion(-)
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index e596b0d7780..40bc74fa6c5 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,123 @@
+2020-09-25 Tamar Christina <tamar.christina@arm.com>
+
+ PR target/71233
+ * config/aarch64/aarch64-builtins.c (enum aarch64_type_qualifiers):
+ Add qualifier_lane_pair_index.
+ (emit-rtl.h): Include.
+ (TYPES_QUADOP_LANE_PAIR): New.
+ (aarch64_simd_expand_args): Use it.
+ (aarch64_simd_expand_builtin): Likewise.
+ (AARCH64_SIMD_FCMLA_LANEQ_BUILTINS, aarch64_fcmla_laneq_builtin_datum): New.
+ (FCMLA_LANEQ_BUILTIN, AARCH64_SIMD_FCMLA_LANEQ_BUILTIN_BASE,
+ AARCH64_SIMD_FCMLA_LANEQ_BUILTINS, aarch64_fcmla_lane_builtin_data,
+ aarch64_init_fcmla_laneq_builtins, aarch64_expand_fcmla_builtin): New.
+ (aarch64_init_builtins): Add aarch64_init_fcmla_laneq_builtins.
+ (aarch64_expand_buildin): Add AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V2SF,
+ AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V2SF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ180_V2SF,
+ AARCH64_SIMD_BUILTIN_FCMLA_LANEQ2700_V2SF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V4HF,
+ AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V4HF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ180_V4HF,
+ AARCH64_SIMD_BUILTIN_FCMLA_LANEQ270_V4HF.
+ * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Add __ARM_FEATURE_COMPLEX.
+ * config/aarch64/aarch64-simd-builtins.def (fcadd90, fcadd270, fcmla0, fcmla90,
+ fcmla180, fcmla270, fcmla_lane0, fcmla_lane90, fcmla_lane180, fcmla_lane270,
+ fcmla_laneq0, fcmla_laneq90, fcmla_laneq180, fcmla_laneq270,
+ fcmlaq_lane0, fcmlaq_lane90, fcmlaq_lane180, fcmlaq_lane270): New.
+ * config/aarch64/aarch64-simd.md (aarch64_fcmla_lane<rot><mode>,
+ aarch64_fcmla_laneq<rot>v4hf, aarch64_fcmlaq_lane<rot><mode>,aarch64_fcadd<rot><mode>,
+ aarch64_fcmla<rot><mode>): New.
+ * config/aarch64/arm_neon.h:
+ (vcadd_rot90_f16): New.
+ (vcaddq_rot90_f16): New.
+ (vcadd_rot270_f16): New.
+ (vcaddq_rot270_f16): New.
+ (vcmla_f16): New.
+ (vcmlaq_f16): New.
+ (vcmla_lane_f16): New.
+ (vcmla_laneq_f16): New.
+ (vcmlaq_lane_f16): New.
+ (vcmlaq_rot90_lane_f16): New.
+ (vcmla_rot90_laneq_f16): New.
+ (vcmla_rot90_lane_f16): New.
+ (vcmlaq_rot90_f16): New.
+ (vcmla_rot90_f16): New.
+ (vcmlaq_laneq_f16): New.
+ (vcmla_rot180_laneq_f16): New.
+ (vcmla_rot180_lane_f16): New.
+ (vcmlaq_rot180_f16): New.
+ (vcmla_rot180_f16): New.
+ (vcmlaq_rot90_laneq_f16): New.
+ (vcmlaq_rot270_laneq_f16): New.
+ (vcmlaq_rot270_lane_f16): New.
+ (vcmla_rot270_laneq_f16): New.
+ (vcmlaq_rot270_f16): New.
+ (vcmla_rot270_f16): New.
+ (vcmlaq_rot180_laneq_f16): New.
+ (vcmlaq_rot180_lane_f16): New.
+ (vcmla_rot270_lane_f16): New.
+ (vcadd_rot90_f32): New.
+ (vcaddq_rot90_f32): New.
+ (vcaddq_rot90_f64): New.
+ (vcadd_rot270_f32): New.
+ (vcaddq_rot270_f32): New.
+ (vcaddq_rot270_f64): New.
+ (vcmla_f32): New.
+ (vcmlaq_f32): New.
+ (vcmlaq_f64): New.
+ (vcmla_lane_f32): New.
+ (vcmla_laneq_f32): New.
+ (vcmlaq_lane_f32): New.
+ (vcmlaq_laneq_f32): New.
+ (vcmla_rot90_f32): New.
+ (vcmlaq_rot90_f32): New.
+ (vcmlaq_rot90_f64): New.
+ (vcmla_rot90_lane_f32): New.
+ (vcmla_rot90_laneq_f32): New.
+ (vcmlaq_rot90_lane_f32): New.
+ (vcmlaq_rot90_laneq_f32): New.
+ (vcmla_rot180_f32): New.
+ (vcmlaq_rot180_f32): New.
+ (vcmlaq_rot180_f64): New.
+ (vcmla_rot180_lane_f32): New.
+ (vcmla_rot180_laneq_f32): New.
+ (vcmlaq_rot180_lane_f32): New.
+ (vcmlaq_rot180_laneq_f32): New.
+ (vcmla_rot270_f32): New.
+ (vcmlaq_rot270_f32): New.
+ (vcmlaq_rot270_f64): New.
+ (vcmla_rot270_lane_f32): New.
+ (vcmla_rot270_laneq_f32): New.
+ (vcmlaq_rot270_lane_f32): New.
+ (vcmlaq_rot270_laneq_f32): New.
+ * config/aarch64/aarch64.h (TARGET_COMPLEX): New.
+ * config/aarch64/iterators.md (UNSPEC_FCADD90, UNSPEC_FCADD270,
+ UNSPEC_FCMLA, UNSPEC_FCMLA90, UNSPEC_FCMLA180, UNSPEC_FCMLA270): New.
+ (FCADD, FCMLA): New.
+ (rot): New.
+ (FCMLA_maybe_lane): New.
+ * config/arm/types.md (neon_fcadd, neon_fcmla): New.
+
+2020-09-25 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
+
+ PR target/71233
+ * config/aarch64/aarch64.md (UNSPEC_RNDR, UNSPEC_RNDRRS):
+ Define.
+ (aarch64_rndr): New define_insn.
+ (aarch64_rndrrs): Likewise.
+ * config/aarch64/aarch64.h (AARCH64_ISA_RNG): Define.
+ (TARGET_RNG): Likewise.
+ (AARCH64_FL_RNG): Likewise.
+ * config/aarch64/aarch64-option-extensions.def (rng): Define.
+ * config/aarch64/aarch64-builtins.c (enum aarch64_builtins):
+ Add AARCH64_BUILTIN_RNG_RNDR, AARCH64_BUILTIN_RNG_RNDRRS.
+ (aarch64_init_rng_builtins): Define.
+ (aarch64_init_builtins): Call aarch64_init_rng_builtins.
+ (aarch64_expand_rng_builtin): Define.
+ (aarch64_expand_builtin): Use IGNORE argument, handle
+ RNG builtins.
+ * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins):
+ Define __ARM_FEATURE_RNG when TARGET_RNG.
+ * config/aarch64/arm_acle.h (__rndr, __rndrrs): Define.
+
2020-09-24 H.J. Lu <hjl.tools@gmail.com>
Backported from master:
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index cfe4a2ef954..bfdd19d304c 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200925
+20200926
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index b2e821ad7b0..32eb0521334 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,20 @@
+2020-09-25 Tamar Christina <tamar.christina@arm.com>
+
+ PR target/71233
+ * lib/target-supports.exp
+ (check_effective_target_arm_v8_3a_complex_neon_ok_nocache,
+ check_effective_target_arm_v8_3a_complex_neon_ok,
+ add_options_for_arm_v8_3a_complex_neon,
+ check_effective_target_arm_v8_3a_complex_neon_hw,
+ check_effective_target_vect_complex_rot_N): New.
+ * gcc.target/aarch64/advsimd-intrinsics/vector-complex.c: New test.
+ * gcc.target/aarch64/advsimd-intrinsics/vector-complex_f16.c: New test.
+
+2020-09-25 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
+
+ PR target/71233
+ * gcc.target/aarch64/acle/rng_1.c: New test.
+
2020-09-24 H.J. Lu <hjl.tools@gmail.com>
Backported from master:
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