From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2153) id 07428384B110; Mon, 28 Sep 2020 09:15:44 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 07428384B110 Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Jakub Jelinek To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/vendors/redhat/heads/gcc-8-branch)] Add support for __jcvt intrinsic X-Act-Checkin: gcc X-Git-Author: Kyrylo Tkachov X-Git-Refname: refs/vendors/redhat/heads/gcc-8-branch X-Git-Oldrev: e6245152f82571943c1d708307b35e5407f63f6e X-Git-Newrev: f7e76fbc8a8f154366c2875c74068e569972698b Message-Id: <20200928091544.07428384B110@sourceware.org> Date: Mon, 28 Sep 2020 09:15:44 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 28 Sep 2020 09:15:44 -0000 https://gcc.gnu.org/g:f7e76fbc8a8f154366c2875c74068e569972698b commit f7e76fbc8a8f154366c2875c74068e569972698b Author: Kyrylo Tkachov Date: Tue Sep 3 08:40:30 2019 +0000 Add support for __jcvt intrinsic This patch implements the __jcvt ACLE intrinsic [1] that maps down to the FJCVTZS [2] instruction from Armv8.3-a. No fancy mode iterators or nothing. Just a single builtin, UNSPEC and define_insn and the associate plumbing. This patch also defines __ARM_FEATURE_JCVT to indicate when the intrinsic is available. [1] https://developer.arm.com/docs/101028/latest/data-processing-intrinsics [2] https://developer.arm.com/docs/ddi0596/latest/simd-and-floating-point-instructions-alphabetic-order/fjcvtzs-floating-point-javascript-convert-to-signed-fixed-point-rounding-toward-zero gcc/ PR target/71233 * config/aarch64/aarch64.md (UNSPEC_FJCVTZS): Define. (aarch64_fjcvtzs): New define_insn. * config/aarch64/aarch64.h (TARGET_JSCVT): Define. * config/aarch64/aarch64-builtins.c (aarch64_builtins): Add AARCH64_JSCVT. (aarch64_init_builtins): Initialize __builtin_aarch64_jcvtzs. (aarch64_expand_builtin): Handle AARCH64_JSCVT. * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define __ARM_FEATURE_JCVT where appropriate. * config/aarch64/arm_acle.h (__jcvt): Define. * doc/sourcebuild.texi (aarch64_fjcvtzs_hw) Document new target supports option. gcc/testsuite/ PR target/71233 * gcc.target/aarch64/acle/jcvt_1.c: New test. * gcc.target/aarch64/acle/jcvt_2.c: New testcase. * lib/target-supports.exp (check_effective_target_aarch64_fjcvtzs_hw): Add new check for FJCVTZS hw. Co-Authored-By: Andrea Corallo (cherry picked from commit e1d5d19ec4f84b67ac693fef5b2add7dc9cf056d) (cherry picked from commit 2c62952f8160bdc8d4111edb34a4bc75096c1e05) (cherry picked from commit d2b86e14c14020f3e119ab8f462e2a91bd7d46e5) (cherry picked from commit 58ae77d3ba70a2b9ccc90a90f3f82cf46239d5f1) Diff: --- gcc/config/aarch64/aarch64-builtins.c | 18 ++++++++++++++ gcc/config/aarch64/aarch64-c.c | 1 + gcc/config/aarch64/aarch64.h | 3 +++ gcc/config/aarch64/aarch64.md | 11 +++++++++ gcc/config/aarch64/arm_acle.h | 10 ++++++++ gcc/doc/sourcebuild.texi | 3 +++ gcc/testsuite/gcc.target/aarch64/acle/jcvt_1.c | 15 ++++++++++++ gcc/testsuite/gcc.target/aarch64/acle/jcvt_2.c | 33 ++++++++++++++++++++++++++ gcc/testsuite/lib/target-supports.exp | 21 ++++++++++++++++ 9 files changed, 115 insertions(+) diff --git a/gcc/config/aarch64/aarch64-builtins.c b/gcc/config/aarch64/aarch64-builtins.c index ced3aa6c100..9a542e829a4 100644 --- a/gcc/config/aarch64/aarch64-builtins.c +++ b/gcc/config/aarch64/aarch64-builtins.c @@ -399,6 +399,8 @@ enum aarch64_builtins AARCH64_PAUTH_BUILTIN_AUTIA1716, AARCH64_PAUTH_BUILTIN_PACIA1716, AARCH64_PAUTH_BUILTIN_XPACLRI, + /* Builtin for Arm8.3-a Javascript conversion instruction. */ + AARCH64_JSCVT, AARCH64_BUILTIN_MAX }; @@ -1002,6 +1004,12 @@ aarch64_init_builtins (void) aarch64_init_crc32_builtins (); aarch64_init_builtin_rsqrt (); + tree ftype_jcvt + = build_function_type_list (intSI_type_node, double_type_node, NULL); + aarch64_builtin_decls[AARCH64_JSCVT] + = add_builtin_function ("__builtin_aarch64_jcvtzs", ftype_jcvt, + AARCH64_JSCVT, BUILT_IN_MD, NULL, NULL_TREE); + /* Initialize pointer authentication builtins which are backed by instructions in NOP encoding space. @@ -1391,6 +1399,16 @@ aarch64_expand_builtin (tree exp, } return target; + + case AARCH64_JSCVT: + { + expand_operand ops[2]; + create_output_operand (&ops[0], target, SImode); + op0 = expand_normal (CALL_EXPR_ARG (exp, 0)); + create_input_operand (&ops[1], op0, DFmode); + expand_insn (CODE_FOR_aarch64_fjcvtzs, 2, ops); + return ops[0].value; + } } if (fcode >= AARCH64_SIMD_BUILTIN_BASE && fcode <= AARCH64_SIMD_BUILTIN_MAX) diff --git a/gcc/config/aarch64/aarch64-c.c b/gcc/config/aarch64/aarch64-c.c index 108c0120394..fcce3d672b6 100644 --- a/gcc/config/aarch64/aarch64-c.c +++ b/gcc/config/aarch64/aarch64-c.c @@ -109,6 +109,7 @@ aarch64_update_cpp_builtins (cpp_reader *pfile) aarch64_def_or_undef (TARGET_CRC32, "__ARM_FEATURE_CRC32", pfile); aarch64_def_or_undef (TARGET_DOTPROD, "__ARM_FEATURE_DOTPROD", pfile); + aarch64_def_or_undef (TARGET_JSCVT, "__ARM_FEATURE_JCVT", pfile); cpp_undef (pfile, "__AARCH64_CMODEL_TINY__"); cpp_undef (pfile, "__AARCH64_CMODEL_SMALL__"); diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index 976f9afae54..8c63733c699 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -234,6 +234,9 @@ extern unsigned aarch64_architecture_version; /* ARMv8.3-A features. */ #define TARGET_ARMV8_3 (AARCH64_ISA_V8_3) +/* Javascript conversion instruction from Armv8.3-a. */ +#define TARGET_JSCVT (TARGET_FLOAT && AARCH64_ISA_V8_3) + /* Make sure this is always defined so we don't have to check for ifdefs but rather use normal ifs. */ #ifndef TARGET_FIX_ERR_A53_835769_DEFAULT diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 82db038c77a..2b492b53391 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -105,6 +105,7 @@ UNSPEC_CRC32X UNSPEC_FCVTZS UNSPEC_FCVTZU + UNSPEC_FJCVTZS UNSPEC_URECPE UNSPEC_FRECPE UNSPEC_FRECPS @@ -5885,6 +5886,16 @@ [(set_attr "length" "0")] ) +(define_insn "aarch64_fjcvtzs" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:DF 1 "register_operand" "w")] + UNSPEC_FJCVTZS)) + (clobber (reg:CC CC_REGNUM))] + "TARGET_JSCVT" + "fjcvtzs\\t%w0, %d1" + [(set_attr "type" "f_cvtf2i")] +) + ;; Pointer authentication patterns are always provided. In architecture ;; revisions prior to ARMv8.3-A these HINT instructions operate as NOPs. ;; This lets the user write portable software which authenticates pointers diff --git a/gcc/config/aarch64/arm_acle.h b/gcc/config/aarch64/arm_acle.h index 8504c3f1d76..7bae393c33d 100644 --- a/gcc/config/aarch64/arm_acle.h +++ b/gcc/config/aarch64/arm_acle.h @@ -29,6 +29,16 @@ #include +#pragma GCC push_options +#pragma GCC target ("arch=armv8.3-a") +__extension__ static __inline int32_t __attribute__ ((__always_inline__)) +__jcvt (double __a) +{ + return __builtin_aarch64_jcvtzs (__a); +} + +#pragma GCC pop_options + #pragma GCC push_options #pragma GCC target ("+nothing+crc") diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi index ad7dea3744c..eb85aca5042 100644 --- a/gcc/doc/sourcebuild.texi +++ b/gcc/doc/sourcebuild.texi @@ -1898,6 +1898,9 @@ AArch64 target which generates instruction sequences for big endian. Binutils installed on test system supports relocation types required by -fpic for AArch64 small memory model. +@item aarch64_fjcvtzs_hw +AArch64 target that is able to generate and execute armv8.3-a FJCVTZS +instruction. @end table @subsubsection MIPS-specific attributes diff --git a/gcc/testsuite/gcc.target/aarch64/acle/jcvt_1.c b/gcc/testsuite/gcc.target/aarch64/acle/jcvt_1.c new file mode 100644 index 00000000000..0c900b1b57c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/acle/jcvt_1.c @@ -0,0 +1,15 @@ +/* Test the __jcvt ACLE intrinsic. */ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=armv8.3-a" } */ + +#include + +#ifdef __ARM_FEATURE_JCVT +int32_t +test_jcvt (double a) +{ + return __jcvt (a); +} +#endif + +/* { dg-final { scan-assembler-times "fjcvtzs\tw\[0-9\]+, d\[0-9\]+\n" 1 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/acle/jcvt_2.c b/gcc/testsuite/gcc.target/aarch64/acle/jcvt_2.c new file mode 100644 index 00000000000..ea2dfd14cf2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/acle/jcvt_2.c @@ -0,0 +1,33 @@ +/* Test the __jcvt ACLE intrinsic. */ +/* { dg-do run } */ +/* { dg-options "-O2 -march=armv8.3-a -save-temps" } */ +/* { dg-require-effective-target aarch64_fjcvtzs_hw } */ + +#include + +extern void abort (void); + +#ifdef __ARM_FEATURE_JCVT +volatile int32_t x; + +int __attribute__((noinline)) +foo (double a, int b, int c) +{ + b = b > c; + x = __jcvt (a); + return b; +} + +int +main (void) +{ + int x = foo (1.1, 2, 3); + if (x) + abort (); + + return 0; +} + +#endif + +/* { dg-final { scan-assembler-times "fjcvtzs\tw\[0-9\]+, d\[0-9\]+\n" 1 } } */ diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 3d85e17b74f..fde6cf45274 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -4386,6 +4386,27 @@ proc check_effective_target_arm_neonv2_hw { } { } [add_options_for_arm_neonv2 ""]] } +# Return 1 if the target supports executing the armv8.3-a FJCVTZS +# instruction. +proc check_effective_target_aarch64_fjcvtzs_hw { } { + if { ![istarget aarch64*-*-*] } { + return 0 + } + return [check_runtime aarch64_fjcvtzs_hw_available { + int + main (void) + { + double in = 25.1; + int out; + asm volatile ("fjcvtzs %w0, %d1" + : "=r" (out) + : "w" (in) + : /* No clobbers. */); + return out != 25; + } + } "-march=armv8.3-a" ] +} + # Return 1 if the target supports the ARMv8.1 Adv.SIMD extension, 0 # otherwise. The test is valid for AArch64 and ARM. Record the command # line options needed.