[gcc r10-8846] arm: Add support for Neoverse N2 CPU

[gcc r10-8846] arm: Add support for Neoverse N2 CPU

[Alex Coplan]

https://gcc.gnu.org/g:d7e8411f6a333d4054894ad3b23f23415a525230

commit r10-8846-gd7e8411f6a333d4054894ad3b23f23415a525230
Author: Alex Coplan <alex.coplan@arm.com>
Date:   Fri Oct 2 16:06:15 2020 +0100

    arm: Add support for Neoverse N2 CPU
    
    This patch backports the AArch32 support for Arm's Neoverse N2 CPU to
    GCC 10.
    
    gcc/ChangeLog:
    
            * config/arm/arm-cpus.in (neoverse-n2): New.
            * config/arm/arm-tables.opt: Regenerate.
            * config/arm/arm-tune.md: Regenerate.
            * doc/invoke.texi: Document support for Neoverse N2.

Diff:
---
 gcc/config/arm/arm-cpus.in    | 12 ++++++++++++
 gcc/config/arm/arm-tables.opt |  3 +++
 gcc/config/arm/arm-tune.md    |  5 +++--
 gcc/doc/invoke.texi           |  6 +++---
 4 files changed, 21 insertions(+), 5 deletions(-)

diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in
index b1fe48eb087..ca772bdcf6d 100644
--- a/gcc/config/arm/arm-cpus.in
+++ b/gcc/config/arm/arm-cpus.in
@@ -1488,6 +1488,18 @@ begin cpu neoverse-v1
   costs cortex_a57
 end cpu neoverse-v1
 
+# Armv8.5 A-profile Architecture Processors
+begin cpu neoverse-n2
+  cname neoversen2
+  tune for cortex-a57
+  tune flags LDSCHED
+  architecture armv8.5-a+fp16+bf16+i8mm
+  option crypto add FP_ARMv8 CRYPTO
+  costs cortex_a57
+  vendor 41
+  part 0xd49
+end cpu neoverse-n2
+
 # V8 M-profile implementations.
 begin cpu cortex-m23
  cname cortexm23
diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt
index 1a7c3191784..c8f83b03b6f 100644
--- a/gcc/config/arm/arm-tables.opt
+++ b/gcc/config/arm/arm-tables.opt
@@ -252,6 +252,9 @@ Enum(processor_type) String(cortex-a76.cortex-a55) Value( TARGET_CPU_cortexa76co
 EnumValue
 Enum(processor_type) String(neoverse-v1) Value( TARGET_CPU_neoversev1)
 
+EnumValue
+Enum(processor_type) String(neoverse-n2) Value( TARGET_CPU_neoversen2)
+
 EnumValue
 Enum(processor_type) String(cortex-m23) Value( TARGET_CPU_cortexm23)
 
diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md
index 3874f42a26b..f98f7ca9ae5 100644
--- a/gcc/config/arm/arm-tune.md
+++ b/gcc/config/arm/arm-tune.md
@@ -46,6 +46,7 @@
 	cortexa73cortexa53,cortexa55,cortexa75,
 	cortexa76,cortexa76ae,cortexa77,
 	neoversen1,cortexa75cortexa55,cortexa76cortexa55,
-	neoversev1,cortexm23,cortexm33,
-	cortexm35p,cortexm55,cortexr52"
+	neoversev1,neoversen2,cortexm23,
+	cortexm33,cortexm35p,cortexm55,
+	cortexr52"
 	(const (symbol_ref "((enum attr_tune) arm_tune)")))
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 4c08258bf57..1d924085b02 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -18824,9 +18824,9 @@ Permissible names are: @samp{arm7tdmi}, @samp{arm7tdmi-s}, @samp{arm710t},
 @samp{cortex-m35p}, @samp{cortex-m55},
 @samp{cortex-m1.small-multiply}, @samp{cortex-m0.small-multiply},
 @samp{cortex-m0plus.small-multiply}, @samp{exynos-m1}, @samp{marvell-pj4},
-@samp{neoverse-n1} @samp{neoverse-v1}, @samp{xscale}, @samp{iwmmxt},
-@samp{iwmmxt2}, @samp{ep9312}, @samp{fa526}, @samp{fa626}, @samp{fa606te},
-@samp{fa626te}, @samp{fmp626}, @samp{fa726te}, @samp{xgene1}.
+@samp{neoverse-n1}, @samp{neoverse-n2}, @samp{neoverse-v1}, @samp{xscale},
+@samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}, @samp{fa526}, @samp{fa626},
+@samp{fa606te}, @samp{fa626te}, @samp{fmp626}, @samp{fa726te}, @samp{xgene1}.
 
 Additionally, this option can specify that GCC should tune the performance
 of the code for a big.LITTLE system.  Permissible names are: