[gcc(refs/users/acsawdey/heads/ld-cmpi-cr0)] Work in progress for ld-cmpi fusion

[gcc(refs/users/acsawdey/heads/ld-cmpi-cr0)] Work in progress for ld-cmpi fusion

[Aaron Sawdey]

https://gcc.gnu.org/g:ecc7a7e1d8c1f809c5b95b4ea96ef1ade6a37aab

commit ecc7a7e1d8c1f809c5b95b4ea96ef1ade6a37aab
Author: Aaron Sawdey <acsawdey@linux.ibm.com>
Date:   Mon Sep 28 11:15:46 2020 -0500

    Work in progress for ld-cmpi fusion
    
    bootstrap passed, regtests good

Diff:
---
 gcc/config/rs6000/predicates.md   |  5 +++
 gcc/config/rs6000/rs6000-protos.h |  2 ++
 gcc/config/rs6000/rs6000.c        | 27 ++++++++++++++++
 gcc/config/rs6000/rs6000.md       | 68 +++++++++++++++++++++++++++++++++++++++
 4 files changed, 102 insertions(+)

diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 4c2fe7fa312..b75c1ddfb69 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -297,6 +297,11 @@
   (and (match_code "const_int")
        (match_test "IN_RANGE (INTVAL (op), 0, 1)")))
 
+;; Match op = -1, op = 0, or op = 1.
+(define_predicate "const_m1_to_1_operand"
+  (and (match_code "const_int")
+       (match_test "IN_RANGE (INTVAL (op), -1, 1)")))
+
 ;; Match op = 0..3.
 (define_predicate "const_0_to_3_operand"
   (and (match_code "const_int")
diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h
index 25fa5dd57cd..d8a344245e6 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -190,6 +190,8 @@ enum non_prefixed_form {
 
 extern enum insn_form address_to_insn_form (rtx, machine_mode,
 					    enum non_prefixed_form);
+extern bool address_ok_for_form (rtx, machine_mode,
+				 enum non_prefixed_form);
 extern bool prefixed_load_p (rtx_insn *);
 extern bool prefixed_store_p (rtx_insn *);
 extern bool prefixed_paddi_p (rtx_insn *);
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index b58eeae2b98..feb1566c859 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -25474,6 +25474,33 @@ address_to_insn_form (rtx addr,
   return INSN_FORM_BAD;
 }
 
+bool
+address_ok_for_form (rtx addr,
+		     machine_mode mode,
+		     enum non_prefixed_form non_prefixed_format)
+{
+  enum insn_form result_form;
+
+  result_form = address_to_insn_form (addr, mode, non_prefixed_format);
+
+  switch (non_prefixed_format)
+    {
+    case NON_PREFIXED_DS:
+      switch (result_form)
+	{
+	case INSN_FORM_DS:
+	case INSN_FORM_BASE_REG:
+	  return true;
+	default:
+	  break;
+	}
+      break;
+    default:
+      break;
+    }
+  return false;
+}
+
 /* Helper function to see if we're potentially looking at lfs/stfs.
    - PARALLEL containing a SET and a CLOBBER
    - stfs:
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 779bfd11237..49deccd110e 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -1896,6 +1896,74 @@
    (set_attr "dot" "yes")
    (set_attr "length" "4,8")])
 
+;; Define an insn for ld+cmpi so we can force it to use CR0 on p10
+;; immediate has to be -1/0/1
+(define_insn_and_split "*ld_cmpi_cr0"
+  [(set (match_operand:CC 2 "cc_reg_operand" "=x")
+	(compare:CC (match_operand:DI 1 "memory_operand" "m")
+		    (match_operand:GPR 3 "const_m1_to_1_operand" "n")))
+   (set (match_operand:DI 0 "gpc_reg_operand" "=r")
+	(match_dup 1))
+   ]
+  "(getenv(\"NOCR0HACK\")==NULL)"
+  "ld %0,%1\;cmpi 0,1,%0,%3"
+  "&& reload_completed
+   && (cc_reg_not_cr0_operand (operands[2], CCmode)
+       || !address_ok_for_form (XEXP (operands[1],0), DImode, NON_PREFIXED_DS))"
+  [(set (match_dup 0) (match_dup 1))
+   (set (match_dup 2)
+        (compare:CC (match_dup 0)
+		    (match_dup 3)))]
+  ""
+  [(set_attr "type" "load")
+   (set_attr "length" "8")])
+
+;; Define an insn for lwa+cmpdi so we can force it to use CR0 on p10
+;; immediate is -1/0/1
+(define_insn_and_split "*lwa_cmpdi_cr0"
+  [(set (match_operand:CC 2 "cc_reg_operand" "=x")
+	(compare:CC (sign_extend:DI (match_operand:SI 1 "memory_operand" "m"))
+		    (match_operand:GPR 3 "const_m1_to_1_operand" "n")))
+   (set (match_operand:DI 0 "gpc_reg_operand" "=r")
+	(sign_extend:DI (match_dup 1)))
+   ]
+  "(getenv(\"NOCR0HACK\")==NULL)"
+  "lwa %0,%1\;cmpdi %0,%3"
+  "&& reload_completed
+   && (cc_reg_not_cr0_operand (operands[2], CCmode)
+       || !address_ok_for_form (XEXP (operands[1],0), DImode, NON_PREFIXED_DS))"
+  [(set (match_dup 0)
+	(sign_extend:DI (match_dup 1)))
+   (set (match_dup 2)
+        (compare:CC (match_dup 0)
+		    (match_dup 3)))]
+  ""
+  [(set_attr "type" "load")
+   (set_attr "length" "8")])
+
+;; Define an insn for lwa+cmpwi so we can force it to use CR0 on p10
+;; immediate is -1/0/1
+(define_insn_and_split "*lwa_cmpwi_cr0"
+  [(set (match_operand:CC 2 "cc_reg_operand" "=x")
+	(compare:CC (match_operand:SI 1 "memory_operand" "m")
+		    (match_operand:SI 3 "const_m1_to_1_operand" "n")))
+   (set (match_operand:DI 0 "gpc_reg_operand" "=r")
+	(sign_extend:DI (match_dup 1)))
+   ]
+  "(getenv(\"NOCR0HACK\")==NULL)"
+  "lwa %0,%1\;cmpwi %0,%3"
+  "&& reload_completed
+   && (cc_reg_not_cr0_operand (operands[2], CCmode)
+       || !address_ok_for_form (XEXP (operands[1],0), DImode, NON_PREFIXED_DS))"
+  [(set (match_dup 0)
+	(sign_extend:DI (match_dup 1)))
+   (set (match_dup 2)
+        (compare:CC (match_dup 0)
+		    (match_dup 3)))]
+  ""
+  [(set_attr "type" "load")
+   (set_attr "length" "8")])
+
 ;; Split an add that we can't do in one insn into two insns, each of which
 ;; does one 16-bit part.  This is used by combine.  Note that the low-order
 ;; add should be last in case the result gets used in an address.

[gcc(refs/users/acsawdey/heads/ld-cmpi-cr0)] Work in progress for ld-cmpi fusion

[Aaron Sawdey]

https://gcc.gnu.org/g:3cb90e60f7687b5c5ba2bd37859fdb45143c72f9

commit 3cb90e60f7687b5c5ba2bd37859fdb45143c72f9
Author: Aaron Sawdey <acsawdey@linux.ibm.com>
Date:   Mon Sep 28 11:15:46 2020 -0500

    Work in progress for ld-cmpi fusion

Diff:
---
 gcc/config/rs6000/predicates.md   |  5 ++++
 gcc/config/rs6000/rs6000-protos.h |  2 ++
 gcc/config/rs6000/rs6000.c        | 27 +++++++++++++++++
 gcc/config/rs6000/rs6000.md       | 62 +++++++++++++++++++++++++++++++++++++++
 4 files changed, 96 insertions(+)

diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 4c2fe7fa312..b75c1ddfb69 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -297,6 +297,11 @@
   (and (match_code "const_int")
        (match_test "IN_RANGE (INTVAL (op), 0, 1)")))
 
+;; Match op = -1, op = 0, or op = 1.
+(define_predicate "const_m1_to_1_operand"
+  (and (match_code "const_int")
+       (match_test "IN_RANGE (INTVAL (op), -1, 1)")))
+
 ;; Match op = 0..3.
 (define_predicate "const_0_to_3_operand"
   (and (match_code "const_int")
diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h
index 25fa5dd57cd..d8a344245e6 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -190,6 +190,8 @@ enum non_prefixed_form {
 
 extern enum insn_form address_to_insn_form (rtx, machine_mode,
 					    enum non_prefixed_form);
+extern bool address_ok_for_form (rtx, machine_mode,
+				 enum non_prefixed_form);
 extern bool prefixed_load_p (rtx_insn *);
 extern bool prefixed_store_p (rtx_insn *);
 extern bool prefixed_paddi_p (rtx_insn *);
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 375fff59928..714cbc4051c 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -25386,6 +25386,33 @@ address_to_insn_form (rtx addr,
   return INSN_FORM_BAD;
 }
 
+bool
+address_ok_for_form (rtx addr, 
+		     machine_mode mode,
+		     enum non_prefixed_form non_prefixed_format)
+{
+  enum insn_form result_form;
+
+  result_form = address_to_insn_form (addr, mode, non_prefixed_format);
+
+  switch (non_prefixed_format)
+    {
+    case NON_PREFIXED_DS:
+      switch (result_form)
+	{
+	case INSN_FORM_DS:
+	case INSN_FORM_BASE_REG:
+	  return true;
+	default:
+	  break;
+	}
+      break;
+    default:
+      break;
+    }
+  return false;
+}
+
 /* Helper function to see if we're potentially looking at lfs/stfs.
    - PARALLEL containing a SET and a CLOBBER
    - stfs:
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 694ff70635e..bc723cef15a 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -1896,6 +1896,68 @@
    (set_attr "dot" "yes")
    (set_attr "length" "4,8")])
 
+;; Define an insn for ld+cmpi so we can force it to use CR0 on p10
+;; immediate has to be -1/0/1
+(define_insn_and_split "*ld_cmpi_cr0"
+  [(set (match_operand:CC 2 "cc_reg_operand" "=x")
+	(compare:CC (match_operand:DI 1 "memory_operand" "m")
+		    (match_operand:GPR 3 "const_m1_to_1_operand" "I")))
+   (set (match_operand:DI 0 "gpc_reg_operand" "=r")
+	(match_dup 1))
+   ]
+  "(getenv(\"NOCR0HACK\")==NULL)"
+  "ld %0,%1\;cmpi 0,1,%0,%3"
+  "&& reload_completed && (cc_reg_not_cr0_operand (operands[2], CCmode) || !address_ok_for_form (XEXP (operands[1],0), DImode, NON_PREFIXED_DS))"
+  [(set (match_dup 0) (match_dup 1))
+   (set (match_dup 2)
+        (compare:CC (match_dup 0)
+		    (match_dup 3)))]
+  ""
+  [(set_attr "type" "load")
+   (set_attr "length" "8")])
+
+;; Define an insn for lwa+cmpdi so we can force it to use CR0 on p10
+;; immediate is -1/0/1
+(define_insn_and_split "*lwa_cmpdi_cr0"
+  [(set (match_operand:CC 2 "cc_reg_operand" "=x")
+	(compare:CC (sign_extend:DI (match_operand:SI 1 "memory_operand" "m"))
+		    (match_operand:GPR 3 "const_m1_to_1_operand" "I")))
+   (set (match_operand:DI 0 "gpc_reg_operand" "=r")
+	(sign_extend:DI (match_dup 1)))
+   ]
+  "(getenv(\"NOCR0HACK\")==NULL)"
+  "lwa %0,%1\;cmpdi %0,%3"
+  "&& reload_completed && (cc_reg_not_cr0_operand (operands[2], CCmode) || !address_ok_for_form (XEXP (operands[1],0), DImode, NON_PREFIXED_DS))"
+  [(set (match_dup 0)
+	(sign_extend:DI (match_dup 1)))
+   (set (match_dup 2)
+        (compare:CC (match_dup 0)
+		    (match_dup 3)))]
+  ""
+  [(set_attr "type" "load")
+   (set_attr "length" "8")])
+
+;; Define an insn for lwa+cmpwi so we can force it to use CR0 on p10
+;; immediate is -1/0/1
+(define_insn_and_split "*lwa_cmpwi_cr0"
+  [(set (match_operand:CC 2 "cc_reg_operand" "=x")
+	(compare:CC (match_operand:SI 1 "memory_operand" "m")
+		    (match_operand:SI 3 "const_m1_to_1_operand" "I")))
+   (set (match_operand:DI 0 "gpc_reg_operand" "=r")
+	(sign_extend:DI (match_dup 1)))
+   ]
+  "(getenv(\"NOCR0HACK\")==NULL)"
+  "lwa %0,%1\;cmpwi %0,%3"
+  "&& reload_completed && (cc_reg_not_cr0_operand (operands[2], CCmode) || !address_ok_for_form (XEXP (operands[1],0), DImode, NON_PREFIXED_DS))"
+  [(set (match_dup 0)
+	(sign_extend:DI (match_dup 1)))
+   (set (match_dup 2)
+        (compare:CC (match_dup 0)
+		    (match_dup 3)))]
+  ""
+  [(set_attr "type" "load")
+   (set_attr "length" "8")])
+
 ;; Split an add that we can't do in one insn into two insns, each of which
 ;; does one 16-bit part.  This is used by combine.  Note that the low-order
 ;; add should be last in case the result gets used in an address.

[gcc(refs/users/acsawdey/heads/ld-cmpi-cr0)] Work in progress for ld-cmpi fusion

[Aaron Sawdey]

https://gcc.gnu.org/g:426081dfb3c976e01ce28c6b11e0a097a25ce927

commit 426081dfb3c976e01ce28c6b11e0a097a25ce927
Author: Aaron Sawdey <acsawdey@linux.ibm.com>
Date:   Mon Sep 28 11:15:46 2020 -0500

    Work in progress for ld-cmpi fusion

Diff:
---
 gcc/config/rs6000/predicates.md |  5 ++++
 gcc/config/rs6000/rs6000.md     | 65 +++++++++++++++++++++++++++++++++++++++++
 2 files changed, 70 insertions(+)

diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 4c2fe7fa312..b75c1ddfb69 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -297,6 +297,11 @@
   (and (match_code "const_int")
        (match_test "IN_RANGE (INTVAL (op), 0, 1)")))
 
+;; Match op = -1, op = 0, or op = 1.
+(define_predicate "const_m1_to_1_operand"
+  (and (match_code "const_int")
+       (match_test "IN_RANGE (INTVAL (op), -1, 1)")))
+
 ;; Match op = 0..3.
 (define_predicate "const_0_to_3_operand"
   (and (match_code "const_int")
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 694ff70635e..841c28f174b 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -1896,6 +1896,71 @@
    (set_attr "dot" "yes")
    (set_attr "length" "4,8")])
 
+;; Define an insn for ld+cmpi so we can force it to use CR0 on p10
+;; immediate has to be -1/0/1
+(define_insn_and_split "*ld_cmpi_cr0"
+  [(set (match_operand:CC 2 "cc_reg_operand" "=x")
+	(compare:CC (match_operand:DI 1 "memory_operand" "m")
+		    (match_operand:GPR 3 "const_m1_to_1_operand" "I")))
+   (set (match_operand:DI 0 "gpc_reg_operand" "=r")
+	(match_dup 1))
+   ]
+  "(getenv(\"NOCR0HACK\")==NULL)"
+  "ld %0,%1 \;
+   cmpi 0,1,%0,%3"
+  "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
+  [(set (match_dup 0) (match_dup 1))
+   (set (match_dup 2)
+        (compare:CC (match_dup 0)
+		    (match_dup 3)))]
+  ""
+  [(set_attr "type" "load")
+   (set_attr "length" "8")])
+
+;; Define an insn for lwa+cmpdi so we can force it to use CR0 on p10
+;; immediate is -1/0/1
+(define_insn_and_split "*lwa_cmpdi_cr0"
+  [(set (match_operand:CC 2 "cc_reg_operand" "=x")
+	(compare:CC (sign_extend:DI (match_operand:SI 1 "memory_operand" "m"))
+		    (match_operand:GPR 3 "const_m1_to_1_operand" "I")))
+   (set (match_operand:DI 0 "gpc_reg_operand" "=r")
+	(sign_extend:DI (match_dup 1)))
+   ]
+  "(getenv(\"NOCR0HACK\")==NULL)"
+  "lwa %0,%1 \;
+   cmpdi %0,%3"
+  "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
+  [(set (match_dup 0)
+	(sign_extend:DI (match_dup 1)))
+   (set (match_dup 2)
+        (compare:CC (match_dup 0)
+		    (match_dup 3)))]
+  ""
+  [(set_attr "type" "load")
+   (set_attr "length" "8")])
+
+;; Define an insn for lwa+cmpwi so we can force it to use CR0 on p10
+;; immediate is -1/0/1
+(define_insn_and_split "*lwa_cmpwi_cr0"
+  [(set (match_operand:CC 2 "cc_reg_operand" "=x")
+	(compare:CC (match_operand:SI 1 "memory_operand" "m")
+		    (match_operand:SI 3 "const_m1_to_1_operand" "I")))
+   (set (match_operand:DI 0 "gpc_reg_operand" "=r")
+	(sign_extend:DI (match_dup 1)))
+   ]
+  "(getenv(\"NOCR0HACK\")==NULL)"
+  "lwa %0,%1 \;
+   cmpwi %0,%3"
+  "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
+  [(set (match_dup 0)
+	(sign_extend:DI (match_dup 1)))
+   (set (match_dup 2)
+        (compare:CC (match_dup 0)
+		    (match_dup 3)))]
+  ""
+  [(set_attr "type" "load")
+   (set_attr "length" "8")])
+
 ;; Split an add that we can't do in one insn into two insns, each of which
 ;; does one 16-bit part.  This is used by combine.  Note that the low-order
 ;; add should be last in case the result gets used in an address.

[gcc(refs/users/acsawdey/heads/ld-cmpi-cr0)] Work in progress for ld-cmpi fusion

[Aaron Sawdey]

https://gcc.gnu.org/g:26d99b7b2fe2a0fbdd8c1d397a92f984fa036a9a

commit 26d99b7b2fe2a0fbdd8c1d397a92f984fa036a9a
Author: Aaron Sawdey <acsawdey@linux.ibm.com>
Date:   Mon Sep 28 11:15:46 2020 -0500

    Work in progress for ld-cmpi fusion

Diff:
---
 gcc/config/rs6000/rs6000.md | 62 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 62 insertions(+)

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 694ff70635e..5c259a33d76 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -1896,6 +1896,68 @@
    (set_attr "dot" "yes")
    (set_attr "length" "4,8")])
 
+;; Define an insn for ld+cmpi so we can force it to use CR0 on p10
+(define_insn_and_split "*ld_cmpi_cr0"
+  [(set (match_operand:CC 2 "cc_reg_operand" "=x")
+	(compare:CC (match_operand:DI 1 "memory_operand" "m")
+		    (match_operand:GPR 3 "short_cint_operand" "I")))
+   (set (match_operand:DI 0 "gpc_reg_operand" "=r")
+	(match_dup 1))
+   ]
+  "(getenv(\"CR0HACK\")!=NULL)"
+  "ld %0,%1 \;
+   cmpi 0,1,%0,%3"
+  "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
+  [(set (match_dup 0) (match_dup 1))
+   (set (match_dup 2)
+        (compare:CC (match_dup 0)
+		    (match_dup 3)))]
+  ""
+  [(set_attr "type" "load")
+   (set_attr "length" "8")])
+
+;; Define an insn for lwa+cmpdi so we can force it to use CR0 on p10
+(define_insn_and_split "*lwa_cmpdi_cr0"
+  [(set (match_operand:CC 2 "cc_reg_operand" "=x")
+	(compare:CC (sign_extend:DI (match_operand:SI 1 "memory_operand" "m"))
+		    (match_operand:GPR 3 "short_cint_operand" "I")))
+   (set (match_operand:DI 0 "gpc_reg_operand" "=r")
+	(sign_extend:DI (match_dup 1)))
+   ]
+  "(getenv(\"CR0HACK\")!=NULL)"
+  "lwa %0,%1 \;
+   cmpdi %0,%3"
+  "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
+  [(set (match_dup 0)
+	(sign_extend:DI (match_dup 1)))
+   (set (match_dup 2)
+        (compare:CC (match_dup 0)
+		    (match_dup 3)))]
+  ""
+  [(set_attr "type" "load")
+   (set_attr "length" "8")])
+
+;; Define an insn for lwa+cmpwi so we can force it to use CR0 on p10
+(define_insn_and_split "*lwa_cmpwi_cr0"
+  [(set (match_operand:CC 2 "cc_reg_operand" "=x")
+	(compare:CC (match_operand:SI 1 "memory_operand" "m")
+		    (match_operand:SI 3 "short_cint_operand" "I")))
+   (set (match_operand:DI 0 "gpc_reg_operand" "=r")
+	(sign_extend:DI (match_dup 1)))
+   ]
+  "(getenv(\"CR0HACK\")!=NULL)"
+  "lwa %0,%1 \;
+   cmpwi %0,%3"
+  "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
+  [(set (match_dup 0)
+	(sign_extend:DI (match_dup 1)))
+   (set (match_dup 2)
+        (compare:CC (match_dup 0)
+		    (match_dup 3)))]
+  ""
+  [(set_attr "type" "load")
+   (set_attr "length" "8")])
+
 ;; Split an add that we can't do in one insn into two insns, each of which
 ;; does one 16-bit part.  This is used by combine.  Note that the low-order
 ;; add should be last in case the result gets used in an address.

[gcc(refs/users/acsawdey/heads/ld-cmpi-cr0)] Work in progress for ld-cmpi fusion

[Aaron Sawdey]

https://gcc.gnu.org/g:636055b8d50d96e6e379e9ad5b7be96fe193f16f

commit 636055b8d50d96e6e379e9ad5b7be96fe193f16f
Author: Aaron Sawdey <acsawdey@linux.ibm.com>
Date:   Mon Sep 28 11:15:46 2020 -0500

    Work in progress for ld-cmpi fusion

Diff:
---
 gcc/config/rs6000/rs6000.md | 62 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 62 insertions(+)

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 43b620ae1c0..115d7d39e86 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -1896,6 +1896,68 @@
    (set_attr "dot" "yes")
    (set_attr "length" "4,8")])
 
+;; Define an insn for ld+cmpi so we can force it to use CR0 on p10
+(define_insn_and_split "*ld_cmpi_cr0"
+  [(set (match_operand:CC 2 "cc_reg_operand" "=x")
+	(compare:CC (match_operand:DI 1 "memory_operand" "m")
+		    (match_operand:GPR 3 "short_cint_operand" "I")))
+   (set (match_operand:DI 0 "gpc_reg_operand" "=r")
+	(match_dup 1))
+   ]
+  "(getenv(\"CR0HACK\")!=NULL)"
+  "ld %0,%1 \;
+   cmpi 0,1,%0,%3"
+  "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
+  [(set (match_dup 0) (match_dup 1))
+   (set (match_dup 2)
+        (compare:CC (match_dup 0)
+		    (match_dup 3)))]
+  ""
+  [(set_attr "type" "load")
+   (set_attr "length" "8")])
+
+;; Define an insn for lwa+cmpdi so we can force it to use CR0 on p10
+(define_insn_and_split "*lwa_cmpdi_cr0"
+  [(set (match_operand:CC 2 "cc_reg_operand" "=x")
+	(compare:CC (sign_extend:DI (match_operand:SI 1 "memory_operand" "m"))
+		    (match_operand:GPR 3 "short_cint_operand" "I")))
+   (set (match_operand:DI 0 "gpc_reg_operand" "=r")
+	(sign_extend:DI (match_dup 1)))
+   ]
+  "(getenv(\"CR0HACK\")!=NULL)"
+  "lwa %0,%1 \;
+   cmpdi %0,%3"
+  "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
+  [(set (match_dup 0)
+	(sign_extend:DI (match_dup 1)))
+   (set (match_dup 2)
+        (compare:CC (match_dup 0)
+		    (match_dup 3)))]
+  ""
+  [(set_attr "type" "load")
+   (set_attr "length" "8")])
+
+;; Define an insn for lwa+cmpwi so we can force it to use CR0 on p10
+(define_insn_and_split "*lwa_cmpwi_cr0"
+  [(set (match_operand:CC 2 "cc_reg_operand" "=x")
+	(compare:CC (match_operand:SI 1 "memory_operand" "m")
+		    (match_operand:SI 3 "short_cint_operand" "I")))
+   (set (match_operand:DI 0 "gpc_reg_operand" "=r")
+	(sign_extend:DI (match_dup 1)))
+   ]
+  "(getenv(\"CR0HACK\")!=NULL)"
+  "lwa %0,%1 \;
+   cmpwi %0,%3"
+  "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
+  [(set (match_dup 0)
+	(sign_extend:DI (match_dup 1)))
+   (set (match_dup 2)
+        (compare:CC (match_dup 0)
+		    (match_dup 3)))]
+  ""
+  [(set_attr "type" "load")
+   (set_attr "length" "8")])
+
 ;; Split an add that we can't do in one insn into two insns, each of which
 ;; does one 16-bit part.  This is used by combine.  Note that the low-order
 ;; add should be last in case the result gets used in an address.