[gcc(refs/vendors/ibm/heads/int128)] Power10: Add int128_t comparisons.

[gcc(refs/vendors/ibm/heads/int128)] Power10: Add int128_t comparisons.

[Michael Meissner]

https://gcc.gnu.org/g:131b69ed9617a591d80e27187910d9a6a37eded1

commit 131b69ed9617a591d80e27187910d9a6a37eded1
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Thu Nov 5 00:50:06 2020 -0500

    Power10: Add int128_t comparisons.
    
    gcc/
    2020-11-05  Michael Meissner  <meissner@linux.ibm.com>
    
            * config/rs6000/rs6000.md (cbranchti4): New insn.
            (cmpti_signed): New insn.
            (cmpti_unsigned): New insn.

Diff:
---
 gcc/config/rs6000/rs6000.md | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index f76a073d6c9..566ec9b9cac 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -11374,6 +11374,17 @@
   DONE;
 })
 
+(define_expand "cbranchti4"
+  [(use (match_operator 0 "comparison_operator"
+         [(match_operand:TI 1 "gpc_reg_operand")
+          (match_operand:TI 2 "gpc_reg_operand")]))
+   (use (match_operand 3))]
+  "TARGET_QUAD_ARITHMETIC && TARGET_POWER10"
+{
+  rs6000_emit_cbranch (TImode, operands);
+  DONE;
+})
+
 (define_expand "cbranch<mode>4"
   [(use (match_operator 0 "comparison_operator"
          [(match_operand:FP 1 "gpc_reg_operand")
@@ -11849,6 +11860,14 @@
   "cmp<wd>%I2 %0,%1,%2"
   [(set_attr "type" "cmp")])
 
+(define_insn "*cmpti_signed"
+  [(set (match_operand:CC 0 "cc_reg_operand" "=y")
+	(compare:CC (match_operand:TI 1 "gpc_reg_operand" "v")
+		    (match_operand:TI 2 "gpc_reg_operand" "v")))]
+  "TARGET_QUAD_ARITHMETIC && TARGET_POWER10"
+  "vcmpsq %0,%1,%2"
+  [(set_attr "type" "veccmp")])
+
 (define_insn "*cmp<mode>_unsigned"
   [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
 	(compare:CCUNS (match_operand:GPR 1 "gpc_reg_operand" "r")
@@ -11857,6 +11876,14 @@
   "cmpl<wd>%I2 %0,%1,%2"
   [(set_attr "type" "cmp")])
 
+(define_insn "*cmpti_unsigned"
+  [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
+	(compare:CCUNS (match_operand:TI 1 "gpc_reg_operand" "v")
+		       (match_operand:TI 2 "gpc_reg_operand" "v")))]
+  "TARGET_QUAD_ARITHMETIC && TARGET_POWER10"
+  "vcmpuq %0,%1,%2"
+  [(set_attr "type" "veccmp")])
+
 ;; If we are comparing a register for equality with a large constant,
 ;; we can do this with an XOR followed by a compare.  But this is profitable
 ;; only if the large constant is only used for the comparison (and in this