From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1652) id AE5833857034; Mon, 16 Nov 2020 15:04:54 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org AE5833857034 Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Christophe Lyon To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/clyon/heads/mve-autovec)] arm: Auto-vectorization for MVE: vshl X-Act-Checkin: gcc X-Git-Author: Christophe Lyon X-Git-Refname: refs/users/clyon/heads/mve-autovec X-Git-Oldrev: 2de478260d1342f49b773dc553fa372a47d144ae X-Git-Newrev: 9536498e0f2aeba5761ff4964c1851169023a35a Message-Id: <20201116150454.AE5833857034@sourceware.org> Date: Mon, 16 Nov 2020 15:04:54 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Nov 2020 15:04:54 -0000 https://gcc.gnu.org/g:9536498e0f2aeba5761ff4964c1851169023a35a commit 9536498e0f2aeba5761ff4964c1851169023a35a Author: Christophe Lyon Date: Mon Nov 16 14:58:19 2020 +0000 arm: Auto-vectorization for MVE: vshl This patch enables MVE vshl instructions for auto-vectorization. New MVE patterns are introduced that take a vector of constants as second operand, all constants being equal. The existing mve_vshlq_n_ is kept, as it takes a single immediate as second operand, and is used by arm_mve.h The vashl3 expander is added to vec-common.md. 2020-11-12 Christophe Lyon gcc/ * config/arm/mve.md (mve_vshlq_n_s_vec): New entry. (mve_vshlq_n_u_vec): Likewise. * config/arm/neon.md (vashl3): Renamed into vashl3_neon. * config/arm/vec-common.md (vasl3): New expander. gcc/testsuite/ * gcc.target/arm/simd/mve-vshl.c: Add tests for vshl. Diff: --- gcc/config/arm/mve.md | 32 ++++++++++++++++++ gcc/config/arm/neon.md | 2 +- gcc/config/arm/vec-common.md | 7 ++++ gcc/testsuite/gcc.target/arm/simd/mve-vshl.c | 50 ++++++++++++++++++++++++++++ 4 files changed, 90 insertions(+), 1 deletion(-) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 4c6cc093822..1f8483d18d6 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -1939,6 +1939,38 @@ [(set_attr "type" "mve_move") ]) +;; Versions with a vector of immediates as operand 2 +(define_insn "mve_vshlq_n_s_vec" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (ashift:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "imm_for_neon_lshift_operand" "i"))) + ] + "TARGET_HAVE_MVE" +{ + return neon_output_shift_immediate ("vshl", 'i', &operands[2], + mode, + VALID_NEON_QREG_MODE (mode), + true); +} + [(set_attr "type" "mve_move") +]) +(define_insn "mve_vshlq_n_u_vec" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (ashift:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "imm_for_neon_lshift_operand" "i"))) + ] + "TARGET_HAVE_MVE" +{ + return neon_output_shift_immediate ("vshl", 'i', &operands[2], + mode, + VALID_NEON_QREG_MODE (mode), + true); +} + [(set_attr "type" "mve_move") +]) + ;; ;; [vshlq_r_s, vshlq_r_u]) ;; diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index e1263b00b39..cb7646ea752 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -870,7 +870,7 @@ ; generic vectorizer code. It ends up creating a V2DI constructor with ; SImode elements. -(define_insn "vashl3" +(define_insn "vashl3_neon" [(set (match_operand:VDQIW 0 "s_register_operand" "=w,w") (ashift:VDQIW (match_operand:VDQIW 1 "s_register_operand" "w,w") (match_operand:VDQIW 2 "imm_lshift_or_reg_neon" "w,Dm")))] diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md index 99ea1cc0b06..86496d06d7d 100644 --- a/gcc/config/arm/vec-common.md +++ b/gcc/config/arm/vec-common.md @@ -193,3 +193,10 @@ (match_operand:VDQ 2 "s_register_operand" "")))] "TARGET_NEON || TARGET_HAVE_MVE" ) + +(define_expand "vashl3" + [(set (match_operand:VDQIW 0 "s_register_operand" "") + (ashift:VDQIW (match_operand:VDQIW 1 "s_register_operand" "") + (match_operand:VDQIW 2 "imm_lshift_or_reg_neon" "")))] + "TARGET_NEON || TARGET_HAVE_MVE" +) \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-vshl.c b/gcc/testsuite/gcc.target/arm/simd/mve-vshl.c new file mode 100644 index 00000000000..63893010e7e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/mve-vshl.c @@ -0,0 +1,50 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O3" } */ + +#include + +void test_vshl_i32 (int32_t * __restrict__ dest, int32_t * a) { + int i; + for (i=0; i<4; i++) { + dest[i] = a[i] << 2; + } +} + +void test_vshl_i32_u (uint32_t * __restrict__ dest, uint32_t * a) { + int i; + for (i=0; i<4; i++) { + dest[i] = a[i] << 3; + } +} + +void test_vshl_i16 (int16_t * __restrict__ dest, int16_t * a) { + int i; + for (i=0; i<8; i++) { + dest[i] = a[i] << 4; + } +} + +void test_vshl_i16_u (uint16_t * __restrict__ dest, uint16_t * a) { + int i; + for (i=0; i<8; i++) { + dest[i] = a[i] << 5; + } +} + +void test_vshl_i8 (int8_t * __restrict__ dest, int8_t * a) { + int i; + for (i=0; i<16; i++) { + dest[i] = a[i] << 6; + } +} + +void test_vshl_i8_u (uint8_t * __restrict__ dest, uint8_t * a) { + int i; + for (i=0; i<16; i++) { + dest[i] = a[i] << 7; + } +} + +/* { dg-final { scan-assembler-times {vshl.i[0-9]+\tq[0-9]+, q[0-9]+} 6 } } */