[gcc(refs/users/acsawdey/heads/fusion-combine)] Add earlyclobber

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* [gcc(refs/users/acsawdey/heads/fusion-combine)] Add earlyclobber
@ 2020-12-09 18:25 Aaron Sawdey
  0 siblings, 0 replies; only message in thread
From: Aaron Sawdey @ 2020-12-09 18:25 UTC (permalink / raw)
  To: gcc-cvs

https://gcc.gnu.org/g:301eadbb015443d4aa916b68e363ecb1a944a5d1

commit 301eadbb015443d4aa916b68e363ecb1a944a5d1
Author: Aaron Sawdey <acsawdey@linux.ibm.com>
Date:   Wed Dec 9 12:25:26 2020 -0600

    Add earlyclobber

Diff:
---
 gcc/config/rs6000/fusion.md    | 256 ++++++++++++++++++++---------------------
 gcc/config/rs6000/genfusion.pl |   2 +-
 2 files changed, 129 insertions(+), 129 deletions(-)

diff --git a/gcc/config/rs6000/fusion.md b/gcc/config/rs6000/fusion.md
index c56090b82c7..2c53987f7ee 100644
--- a/gcc/config/rs6000/fusion.md
+++ b/gcc/config/rs6000/fusion.md
@@ -360,7 +360,7 @@
 ;; kind: scalar outer: and op and rtl and inv 0 comp 0
 ;; inner: and op and rtl and inv 0 comp 0
 (define_insn "*fuse_and_and"
-  [(set (match_operand:GPR 3 "gpc_reg_operand" "=r")
+  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r")
         (and:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r") (match_operand:GPR 1 "gpc_reg_operand" "r")) (match_operand:GPR 2 "gpc_reg_operand" "r")))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "and %3,%1,%0\;and %3,%3,%2"
@@ -372,7 +372,7 @@
 ;; kind: scalar outer: and op and rtl and inv 0 comp 0
 ;; inner: andc op andc rtl and inv 0 comp 1
 (define_insn "*fuse_andc_and"
-  [(set (match_operand:GPR 3 "gpc_reg_operand" "=r")
+  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r")
         (and:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r")) (match_operand:GPR 1 "gpc_reg_operand" "r")) (match_operand:GPR 2 "gpc_reg_operand" "r")))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "andc %3,%1,%0\;and %3,%3,%2"
@@ -384,7 +384,7 @@
 ;; kind: scalar outer: and op and rtl and inv 0 comp 0
 ;; inner: eqv op eqv rtl xor inv 1 comp 0
 (define_insn "*fuse_eqv_and"
-  [(set (match_operand:GPR 3 "gpc_reg_operand" "=r")
+  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r")
         (and:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r") (match_operand:GPR 1 "gpc_reg_operand" "r"))) (match_operand:GPR 2 "gpc_reg_operand" "r")))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "eqv %3,%1,%0\;and %3,%3,%2"
@@ -396,7 +396,7 @@
 ;; kind: scalar outer: and op and rtl and inv 0 comp 0
 ;; inner: nand op nand rtl ior inv 0 comp 3
 (define_insn "*fuse_nand_and"
-  [(set (match_operand:GPR 3 "gpc_reg_operand" "=r")
+  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r")
         (and:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r"))) (match_operand:GPR 2 "gpc_reg_operand" "r")))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "nand %3,%1,%0\;and %3,%3,%2"
@@ -408,7 +408,7 @@
 ;; kind: scalar outer: and op and rtl and inv 0 comp 0
 ;; inner: nor op nor rtl and inv 0 comp 3
 (define_insn "*fuse_nor_and"
-  [(set (match_operand:GPR 3 "gpc_reg_operand" "=r")
+  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r")
         (and:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r"))) (match_operand:GPR 2 "gpc_reg_operand" "r")))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "nor %3,%1,%0\;and %3,%3,%2"
@@ -420,7 +420,7 @@
 ;; kind: scalar outer: and op and rtl and inv 0 comp 0
 ;; inner: or op or rtl ior inv 0 comp 0
 (define_insn "*fuse_or_and"
-  [(set (match_operand:GPR 3 "gpc_reg_operand" "=r")
+  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r")
         (and:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r") (match_operand:GPR 1 "gpc_reg_operand" "r")) (match_operand:GPR 2 "gpc_reg_operand" "r")))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "or %3,%1,%0\;and %3,%3,%2"
@@ -432,7 +432,7 @@
 ;; kind: scalar outer: and op and rtl and inv 0 comp 0
 ;; inner: orc op orc rtl ior inv 0 comp 1
 (define_insn "*fuse_orc_and"
-  [(set (match_operand:GPR 3 "gpc_reg_operand" "=r")
+  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r")
         (and:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r")) (match_operand:GPR 1 "gpc_reg_operand" "r")) (match_operand:GPR 2 "gpc_reg_operand" "r")))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "orc %3,%1,%0\;and %3,%3,%2"
@@ -444,7 +444,7 @@
 ;; kind: scalar outer: and op and rtl and inv 0 comp 0
 ;; inner: xor op xor rtl xor inv 0 comp 0
 (define_insn "*fuse_xor_and"
-  [(set (match_operand:GPR 3 "gpc_reg_operand" "=r")
+  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r")
         (and:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r") (match_operand:GPR 1 "gpc_reg_operand" "r")) (match_operand:GPR 2 "gpc_reg_operand" "r")))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "xor %3,%1,%0\;and %3,%3,%2"
@@ -456,7 +456,7 @@
 ;; kind: scalar outer: andc op andc rtl and inv 0 comp 1
 ;; inner: and op and rtl and inv 0 comp 0
 (define_insn "*fuse_and_andc"
-  [(set (match_operand:GPR 3 "gpc_reg_operand" "=r")
+  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r")
         (and:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r") (match_operand:GPR 1 "gpc_reg_operand" "r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "and %3,%1,%0\;andc %3,%3,%2"
@@ -468,7 +468,7 @@
 ;; kind: scalar outer: andc op andc rtl and inv 0 comp 1
 ;; inner: andc op andc rtl and inv 0 comp 1
 (define_insn "*fuse_andc_andc"
-  [(set (match_operand:GPR 3 "gpc_reg_operand" "=r")
+  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r")
         (and:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r")) (match_operand:GPR 1 "gpc_reg_operand" "r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "andc %3,%1,%0\;andc %3,%3,%2"
@@ -480,7 +480,7 @@
 ;; kind: scalar outer: andc op andc rtl and inv 0 comp 1
 ;; inner: eqv op eqv rtl xor inv 1 comp 0
 (define_insn "*fuse_eqv_andc"
-  [(set (match_operand:GPR 3 "gpc_reg_operand" "=r")
+  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r")
         (and:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r") (match_operand:GPR 1 "gpc_reg_operand" "r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "eqv %3,%1,%0\;andc %3,%3,%2"
@@ -492,7 +492,7 @@
 ;; kind: scalar outer: andc op andc rtl and inv 0 comp 1
 ;; inner: nand op nand rtl ior inv 0 comp 3
 (define_insn "*fuse_nand_andc"
-  [(set (match_operand:GPR 3 "gpc_reg_operand" "=r")
+  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r")
         (and:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "nand %3,%1,%0\;andc %3,%3,%2"
@@ -504,7 +504,7 @@
 ;; kind: scalar outer: andc op andc rtl and inv 0 comp 1
 ;; inner: nor op nor rtl and inv 0 comp 3
 (define_insn "*fuse_nor_andc"
-  [(set (match_operand:GPR 3 "gpc_reg_operand" "=r")
+  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r")
         (and:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "nor %3,%1,%0\;andc %3,%3,%2"
@@ -516,7 +516,7 @@
 ;; kind: scalar outer: andc op andc rtl and inv 0 comp 1
 ;; inner: or op or rtl ior inv 0 comp 0
 (define_insn "*fuse_or_andc"
-  [(set (match_operand:GPR 3 "gpc_reg_operand" "=r")
+  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r")
         (and:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r") (match_operand:GPR 1 "gpc_reg_operand" "r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "or %3,%1,%0\;andc %3,%3,%2"
@@ -528,7 +528,7 @@
 ;; kind: scalar outer: andc op andc rtl and inv 0 comp 1
 ;; inner: orc op orc rtl ior inv 0 comp 1
 (define_insn "*fuse_orc_andc"
-  [(set (match_operand:GPR 3 "gpc_reg_operand" "=r")
+  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r")
         (and:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r")) (match_operand:GPR 1 "gpc_reg_operand" "r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "orc %3,%1,%0\;andc %3,%3,%2"
@@ -540,7 +540,7 @@
 ;; kind: scalar outer: andc op andc rtl and inv 0 comp 1
 ;; inner: xor op xor rtl xor inv 0 comp 0
 (define_insn "*fuse_xor_andc"
-  [(set (match_operand:GPR 3 "gpc_reg_operand" "=r")
+  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r")
         (and:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r") (match_operand:GPR 1 "gpc_reg_operand" "r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "xor %3,%1,%0\;andc %3,%3,%2"
@@ -552,7 +552,7 @@
 ;; kind: scalar outer: eqv op eqv rtl xor inv 1 comp 0
 ;; inner: and op and rtl and inv 0 comp 0
 (define_insn "*fuse_and_eqv"
-  [(set (match_operand:GPR 3 "gpc_reg_operand" "=r")
+  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r")
         (not:GPR (xor:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r") (match_operand:GPR 1 "gpc_reg_operand" "r")) (match_operand:GPR 2 "gpc_reg_operand" "r"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "and %3,%1,%0\;eqv %3,%3,%2"
@@ -564,7 +564,7 @@
 ;; kind: scalar outer: eqv op eqv rtl xor inv 1 comp 0
 ;; inner: andc op andc rtl and inv 0 comp 1
 (define_insn "*fuse_andc_eqv"
-  [(set (match_operand:GPR 3 "gpc_reg_operand" "=r")
+  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r")
         (not:GPR (xor:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r")) (match_operand:GPR 1 "gpc_reg_operand" "r")) (match_operand:GPR 2 "gpc_reg_operand" "r"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "andc %3,%1,%0\;eqv %3,%3,%2"
@@ -576,7 +576,7 @@
 ;; kind: scalar outer: eqv op eqv rtl xor inv 1 comp 0
 ;; inner: eqv op eqv rtl xor inv 1 comp 0
 (define_insn "*fuse_eqv_eqv"
-  [(set (match_operand:GPR 3 "gpc_reg_operand" "=r")
+  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r")
         (not:GPR (xor:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r") (match_operand:GPR 1 "gpc_reg_operand" "r"))) (match_operand:GPR 2 "gpc_reg_operand" "r"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "eqv %3,%1,%0\;eqv %3,%3,%2"
@@ -588,7 +588,7 @@
 ;; kind: scalar outer: eqv op eqv rtl xor inv 1 comp 0
 ;; inner: nand op nand rtl ior inv 0 comp 3
 (define_insn "*fuse_nand_eqv"
-  [(set (match_operand:GPR 3 "gpc_reg_operand" "=r")
+  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r")
         (not:GPR (xor:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r"))) (match_operand:GPR 2 "gpc_reg_operand" "r"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "nand %3,%1,%0\;eqv %3,%3,%2"
@@ -600,7 +600,7 @@
 ;; kind: scalar outer: eqv op eqv rtl xor inv 1 comp 0
 ;; inner: nor op nor rtl and inv 0 comp 3
 (define_insn "*fuse_nor_eqv"
-  [(set (match_operand:GPR 3 "gpc_reg_operand" "=r")
+  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r")
         (not:GPR (xor:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r"))) (match_operand:GPR 2 "gpc_reg_operand" "r"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "nor %3,%1,%0\;eqv %3,%3,%2"
@@ -612,7 +612,7 @@
 ;; kind: scalar outer: eqv op eqv rtl xor inv 1 comp 0
 ;; inner: or op or rtl ior inv 0 comp 0
 (define_insn "*fuse_or_eqv"
-  [(set (match_operand:GPR 3 "gpc_reg_operand" "=r")
+  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r")
         (not:GPR (xor:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r") (match_operand:GPR 1 "gpc_reg_operand" "r")) (match_operand:GPR 2 "gpc_reg_operand" "r"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "or %3,%1,%0\;eqv %3,%3,%2"
@@ -624,7 +624,7 @@
 ;; kind: scalar outer: eqv op eqv rtl xor inv 1 comp 0
 ;; inner: orc op orc rtl ior inv 0 comp 1
 (define_insn "*fuse_orc_eqv"
-  [(set (match_operand:GPR 3 "gpc_reg_operand" "=r")
+  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r")
         (not:GPR (xor:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r")) (match_operand:GPR 1 "gpc_reg_operand" "r")) (match_operand:GPR 2 "gpc_reg_operand" "r"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "orc %3,%1,%0\;eqv %3,%3,%2"
@@ -636,7 +636,7 @@
 ;; kind: scalar outer: eqv op eqv rtl xor inv 1 comp 0
 ;; inner: xor op xor rtl xor inv 0 comp 0
 (define_insn "*fuse_xor_eqv"
-  [(set (match_operand:GPR 3 "gpc_reg_operand" "=r")
+  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r")
         (not:GPR (xor:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r") (match_operand:GPR 1 "gpc_reg_operand" "r")) (match_operand:GPR 2 "gpc_reg_operand" "r"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "xor %3,%1,%0\;eqv %3,%3,%2"
@@ -648,7 +648,7 @@
 ;; kind: scalar outer: nand op nand rtl ior inv 0 comp 3
 ;; inner: and op and rtl and inv 0 comp 0
 (define_insn "*fuse_and_nand"
-  [(set (match_operand:GPR 3 "gpc_reg_operand" "=r")
+  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r")
         (ior:GPR (not:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r") (match_operand:GPR 1 "gpc_reg_operand" "r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "and %3,%1,%0\;nand %3,%3,%2"
@@ -660,7 +660,7 @@
 ;; kind: scalar outer: nand op nand rtl ior inv 0 comp 3
 ;; inner: andc op andc rtl and inv 0 comp 1
 (define_insn "*fuse_andc_nand"
-  [(set (match_operand:GPR 3 "gpc_reg_operand" "=r")
+  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r")
         (ior:GPR (not:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r")) (match_operand:GPR 1 "gpc_reg_operand" "r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "andc %3,%1,%0\;nand %3,%3,%2"
@@ -672,7 +672,7 @@
 ;; kind: scalar outer: nand op nand rtl ior inv 0 comp 3
 ;; inner: eqv op eqv rtl xor inv 1 comp 0
 (define_insn "*fuse_eqv_nand"
-  [(set (match_operand:GPR 3 "gpc_reg_operand" "=r")
+  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r")
         (ior:GPR (not:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r") (match_operand:GPR 1 "gpc_reg_operand" "r")))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "eqv %3,%1,%0\;nand %3,%3,%2"
@@ -684,7 +684,7 @@
 ;; kind: scalar outer: nand op nand rtl ior inv 0 comp 3
 ;; inner: nand op nand rtl ior inv 0 comp 3
 (define_insn "*fuse_nand_nand"
-  [(set (match_operand:GPR 3 "gpc_reg_operand" "=r")
+  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r")
         (ior:GPR (not:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "nand %3,%1,%0\;nand %3,%3,%2"
@@ -696,7 +696,7 @@
 ;; kind: scalar outer: nand op nand rtl ior inv 0 comp 3
 ;; inner: nor op nor rtl and inv 0 comp 3
 (define_insn "*fuse_nor_nand"
-  [(set (match_operand:GPR 3 "gpc_reg_operand" "=r")
+  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r")
         (ior:GPR (not:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "nor %3,%1,%0\;nand %3,%3,%2"
@@ -708,7 +708,7 @@
 ;; kind: scalar outer: nand op nand rtl ior inv 0 comp 3
 ;; inner: or op or rtl ior inv 0 comp 0
 (define_insn "*fuse_or_nand"
-  [(set (match_operand:GPR 3 "gpc_reg_operand" "=r")
+  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r")
         (ior:GPR (not:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r") (match_operand:GPR 1 "gpc_reg_operand" "r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "or %3,%1,%0\;nand %3,%3,%2"
@@ -720,7 +720,7 @@
 ;; kind: scalar outer: nand op nand rtl ior inv 0 comp 3
 ;; inner: orc op orc rtl ior inv 0 comp 1
 (define_insn "*fuse_orc_nand"
-  [(set (match_operand:GPR 3 "gpc_reg_operand" "=r")
+  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r")
         (ior:GPR (not:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r")) (match_operand:GPR 1 "gpc_reg_operand" "r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "orc %3,%1,%0\;nand %3,%3,%2"
@@ -732,7 +732,7 @@
 ;; kind: scalar outer: nand op nand rtl ior inv 0 comp 3
 ;; inner: xor op xor rtl xor inv 0 comp 0
 (define_insn "*fuse_xor_nand"
-  [(set (match_operand:GPR 3 "gpc_reg_operand" "=r")
+  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r")
         (ior:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r") (match_operand:GPR 1 "gpc_reg_operand" "r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "xor %3,%1,%0\;nand %3,%3,%2"
@@ -744,7 +744,7 @@
 ;; kind: scalar outer: nor op nor rtl and inv 0 comp 3
 ;; inner: and op and rtl and inv 0 comp 0
 (define_insn "*fuse_and_nor"
-  [(set (match_operand:GPR 3 "gpc_reg_operand" "=r")
+  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r")
         (and:GPR (not:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r") (match_operand:GPR 1 "gpc_reg_operand" "r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "and %3,%1,%0\;nor %3,%3,%2"
@@ -756,7 +756,7 @@
 ;; kind: scalar outer: nor op nor rtl and inv 0 comp 3
 ;; inner: andc op andc rtl and inv 0 comp 1
 (define_insn "*fuse_andc_nor"
-  [(set (match_operand:GPR 3 "gpc_reg_operand" "=r")
+  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r")
         (and:GPR (not:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r")) (match_operand:GPR 1 "gpc_reg_operand" "r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "andc %3,%1,%0\;nor %3,%3,%2"
@@ -768,7 +768,7 @@
 ;; kind: scalar outer: nor op nor rtl and inv 0 comp 3
 ;; inner: eqv op eqv rtl xor inv 1 comp 0
 (define_insn "*fuse_eqv_nor"
-  [(set (match_operand:GPR 3 "gpc_reg_operand" "=r")
+  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r")
         (and:GPR (not:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r") (match_operand:GPR 1 "gpc_reg_operand" "r")))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "eqv %3,%1,%0\;nor %3,%3,%2"
@@ -780,7 +780,7 @@
 ;; kind: scalar outer: nor op nor rtl and inv 0 comp 3
 ;; inner: nand op nand rtl ior inv 0 comp 3
 (define_insn "*fuse_nand_nor"
-  [(set (match_operand:GPR 3 "gpc_reg_operand" "=r")
+  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r")
         (and:GPR (not:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "nand %3,%1,%0\;nor %3,%3,%2"
@@ -792,7 +792,7 @@
 ;; kind: scalar outer: nor op nor rtl and inv 0 comp 3
 ;; inner: nor op nor rtl and inv 0 comp 3
 (define_insn "*fuse_nor_nor"
-  [(set (match_operand:GPR 3 "gpc_reg_operand" "=r")
+  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r")
         (and:GPR (not:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "nor %3,%1,%0\;nor %3,%3,%2"
@@ -804,7 +804,7 @@
 ;; kind: scalar outer: nor op nor rtl and inv 0 comp 3
 ;; inner: or op or rtl ior inv 0 comp 0
 (define_insn "*fuse_or_nor"
-  [(set (match_operand:GPR 3 "gpc_reg_operand" "=r")
+  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r")
         (and:GPR (not:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r") (match_operand:GPR 1 "gpc_reg_operand" "r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "or %3,%1,%0\;nor %3,%3,%2"
@@ -816,7 +816,7 @@
 ;; kind: scalar outer: nor op nor rtl and inv 0 comp 3
 ;; inner: orc op orc rtl ior inv 0 comp 1
 (define_insn "*fuse_orc_nor"
-  [(set (match_operand:GPR 3 "gpc_reg_operand" "=r")
+  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r")
         (and:GPR (not:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r")) (match_operand:GPR 1 "gpc_reg_operand" "r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "orc %3,%1,%0\;nor %3,%3,%2"
@@ -828,7 +828,7 @@
 ;; kind: scalar outer: nor op nor rtl and inv 0 comp 3
 ;; inner: xor op xor rtl xor inv 0 comp 0
 (define_insn "*fuse_xor_nor"
-  [(set (match_operand:GPR 3 "gpc_reg_operand" "=r")
+  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r")
         (and:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r") (match_operand:GPR 1 "gpc_reg_operand" "r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "xor %3,%1,%0\;nor %3,%3,%2"
@@ -840,7 +840,7 @@
 ;; kind: scalar outer: or op or rtl ior inv 0 comp 0
 ;; inner: and op and rtl and inv 0 comp 0
 (define_insn "*fuse_and_or"
-  [(set (match_operand:GPR 3 "gpc_reg_operand" "=r")
+  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r")
         (ior:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r") (match_operand:GPR 1 "gpc_reg_operand" "r")) (match_operand:GPR 2 "gpc_reg_operand" "r")))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "and %3,%1,%0\;or %3,%3,%2"
@@ -852,7 +852,7 @@
 ;; kind: scalar outer: or op or rtl ior inv 0 comp 0
 ;; inner: andc op andc rtl and inv 0 comp 1
 (define_insn "*fuse_andc_or"
-  [(set (match_operand:GPR 3 "gpc_reg_operand" "=r")
+  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r")
         (ior:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r")) (match_operand:GPR 1 "gpc_reg_operand" "r")) (match_operand:GPR 2 "gpc_reg_operand" "r")))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "andc %3,%1,%0\;or %3,%3,%2"
@@ -864,7 +864,7 @@
 ;; kind: scalar outer: or op or rtl ior inv 0 comp 0
 ;; inner: eqv op eqv rtl xor inv 1 comp 0
 (define_insn "*fuse_eqv_or"
-  [(set (match_operand:GPR 3 "gpc_reg_operand" "=r")
+  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r")
         (ior:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r") (match_operand:GPR 1 "gpc_reg_operand" "r"))) (match_operand:GPR 2 "gpc_reg_operand" "r")))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "eqv %3,%1,%0\;or %3,%3,%2"
@@ -876,7 +876,7 @@
 ;; kind: scalar outer: or op or rtl ior inv 0 comp 0
 ;; inner: nand op nand rtl ior inv 0 comp 3
 (define_insn "*fuse_nand_or"
-  [(set (match_operand:GPR 3 "gpc_reg_operand" "=r")
+  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r")
         (ior:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r"))) (match_operand:GPR 2 "gpc_reg_operand" "r")))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "nand %3,%1,%0\;or %3,%3,%2"
@@ -888,7 +888,7 @@
 ;; kind: scalar outer: or op or rtl ior inv 0 comp 0
 ;; inner: nor op nor rtl and inv 0 comp 3
 (define_insn "*fuse_nor_or"
-  [(set (match_operand:GPR 3 "gpc_reg_operand" "=r")
+  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r")
         (ior:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r"))) (match_operand:GPR 2 "gpc_reg_operand" "r")))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "nor %3,%1,%0\;or %3,%3,%2"
@@ -900,7 +900,7 @@
 ;; kind: scalar outer: or op or rtl ior inv 0 comp 0
 ;; inner: or op or rtl ior inv 0 comp 0
 (define_insn "*fuse_or_or"
-  [(set (match_operand:GPR 3 "gpc_reg_operand" "=r")
+  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r")
         (ior:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r") (match_operand:GPR 1 "gpc_reg_operand" "r")) (match_operand:GPR 2 "gpc_reg_operand" "r")))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "or %3,%1,%0\;or %3,%3,%2"
@@ -912,7 +912,7 @@
 ;; kind: scalar outer: or op or rtl ior inv 0 comp 0
 ;; inner: orc op orc rtl ior inv 0 comp 1
 (define_insn "*fuse_orc_or"
-  [(set (match_operand:GPR 3 "gpc_reg_operand" "=r")
+  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r")
         (ior:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r")) (match_operand:GPR 1 "gpc_reg_operand" "r")) (match_operand:GPR 2 "gpc_reg_operand" "r")))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "orc %3,%1,%0\;or %3,%3,%2"
@@ -924,7 +924,7 @@
 ;; kind: scalar outer: or op or rtl ior inv 0 comp 0
 ;; inner: xor op xor rtl xor inv 0 comp 0
 (define_insn "*fuse_xor_or"
-  [(set (match_operand:GPR 3 "gpc_reg_operand" "=r")
+  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r")
         (ior:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r") (match_operand:GPR 1 "gpc_reg_operand" "r")) (match_operand:GPR 2 "gpc_reg_operand" "r")))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "xor %3,%1,%0\;or %3,%3,%2"
@@ -936,7 +936,7 @@
 ;; kind: scalar outer: orc op orc rtl ior inv 0 comp 1
 ;; inner: and op and rtl and inv 0 comp 0
 (define_insn "*fuse_and_orc"
-  [(set (match_operand:GPR 3 "gpc_reg_operand" "=r")
+  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r")
         (ior:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r") (match_operand:GPR 1 "gpc_reg_operand" "r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "and %3,%1,%0\;orc %3,%3,%2"
@@ -948,7 +948,7 @@
 ;; kind: scalar outer: orc op orc rtl ior inv 0 comp 1
 ;; inner: andc op andc rtl and inv 0 comp 1
 (define_insn "*fuse_andc_orc"
-  [(set (match_operand:GPR 3 "gpc_reg_operand" "=r")
+  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r")
         (ior:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r")) (match_operand:GPR 1 "gpc_reg_operand" "r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "andc %3,%1,%0\;orc %3,%3,%2"
@@ -960,7 +960,7 @@
 ;; kind: scalar outer: orc op orc rtl ior inv 0 comp 1
 ;; inner: eqv op eqv rtl xor inv 1 comp 0
 (define_insn "*fuse_eqv_orc"
-  [(set (match_operand:GPR 3 "gpc_reg_operand" "=r")
+  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r")
         (ior:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r") (match_operand:GPR 1 "gpc_reg_operand" "r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "eqv %3,%1,%0\;orc %3,%3,%2"
@@ -972,7 +972,7 @@
 ;; kind: scalar outer: orc op orc rtl ior inv 0 comp 1
 ;; inner: nand op nand rtl ior inv 0 comp 3
 (define_insn "*fuse_nand_orc"
-  [(set (match_operand:GPR 3 "gpc_reg_operand" "=r")
+  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r")
         (ior:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "nand %3,%1,%0\;orc %3,%3,%2"
@@ -984,7 +984,7 @@
 ;; kind: scalar outer: orc op orc rtl ior inv 0 comp 1
 ;; inner: nor op nor rtl and inv 0 comp 3
 (define_insn "*fuse_nor_orc"
-  [(set (match_operand:GPR 3 "gpc_reg_operand" "=r")
+  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r")
         (ior:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "nor %3,%1,%0\;orc %3,%3,%2"
@@ -996,7 +996,7 @@
 ;; kind: scalar outer: orc op orc rtl ior inv 0 comp 1
 ;; inner: or op or rtl ior inv 0 comp 0
 (define_insn "*fuse_or_orc"
-  [(set (match_operand:GPR 3 "gpc_reg_operand" "=r")
+  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r")
         (ior:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r") (match_operand:GPR 1 "gpc_reg_operand" "r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "or %3,%1,%0\;orc %3,%3,%2"
@@ -1008,7 +1008,7 @@
 ;; kind: scalar outer: orc op orc rtl ior inv 0 comp 1
 ;; inner: orc op orc rtl ior inv 0 comp 1
 (define_insn "*fuse_orc_orc"
-  [(set (match_operand:GPR 3 "gpc_reg_operand" "=r")
+  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r")
         (ior:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r")) (match_operand:GPR 1 "gpc_reg_operand" "r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "orc %3,%1,%0\;orc %3,%3,%2"
@@ -1020,7 +1020,7 @@
 ;; kind: scalar outer: orc op orc rtl ior inv 0 comp 1
 ;; inner: xor op xor rtl xor inv 0 comp 0
 (define_insn "*fuse_xor_orc"
-  [(set (match_operand:GPR 3 "gpc_reg_operand" "=r")
+  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r")
         (ior:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r") (match_operand:GPR 1 "gpc_reg_operand" "r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "xor %3,%1,%0\;orc %3,%3,%2"
@@ -1032,7 +1032,7 @@
 ;; kind: scalar outer: xor op xor rtl xor inv 0 comp 0
 ;; inner: and op and rtl and inv 0 comp 0
 (define_insn "*fuse_and_xor"
-  [(set (match_operand:GPR 3 "gpc_reg_operand" "=r")
+  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r")
         (xor:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r") (match_operand:GPR 1 "gpc_reg_operand" "r")) (match_operand:GPR 2 "gpc_reg_operand" "r")))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "and %3,%1,%0\;xor %3,%3,%2"
@@ -1044,7 +1044,7 @@
 ;; kind: scalar outer: xor op xor rtl xor inv 0 comp 0
 ;; inner: andc op andc rtl and inv 0 comp 1
 (define_insn "*fuse_andc_xor"
-  [(set (match_operand:GPR 3 "gpc_reg_operand" "=r")
+  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r")
         (xor:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r")) (match_operand:GPR 1 "gpc_reg_operand" "r")) (match_operand:GPR 2 "gpc_reg_operand" "r")))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "andc %3,%1,%0\;xor %3,%3,%2"
@@ -1056,7 +1056,7 @@
 ;; kind: scalar outer: xor op xor rtl xor inv 0 comp 0
 ;; inner: eqv op eqv rtl xor inv 1 comp 0
 (define_insn "*fuse_eqv_xor"
-  [(set (match_operand:GPR 3 "gpc_reg_operand" "=r")
+  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r")
         (xor:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r") (match_operand:GPR 1 "gpc_reg_operand" "r"))) (match_operand:GPR 2 "gpc_reg_operand" "r")))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "eqv %3,%1,%0\;xor %3,%3,%2"
@@ -1068,7 +1068,7 @@
 ;; kind: scalar outer: xor op xor rtl xor inv 0 comp 0
 ;; inner: nand op nand rtl ior inv 0 comp 3
 (define_insn "*fuse_nand_xor"
-  [(set (match_operand:GPR 3 "gpc_reg_operand" "=r")
+  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r")
         (xor:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r"))) (match_operand:GPR 2 "gpc_reg_operand" "r")))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "nand %3,%1,%0\;xor %3,%3,%2"
@@ -1080,7 +1080,7 @@
 ;; kind: scalar outer: xor op xor rtl xor inv 0 comp 0
 ;; inner: nor op nor rtl and inv 0 comp 3
 (define_insn "*fuse_nor_xor"
-  [(set (match_operand:GPR 3 "gpc_reg_operand" "=r")
+  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r")
         (xor:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r"))) (match_operand:GPR 2 "gpc_reg_operand" "r")))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "nor %3,%1,%0\;xor %3,%3,%2"
@@ -1092,7 +1092,7 @@
 ;; kind: scalar outer: xor op xor rtl xor inv 0 comp 0
 ;; inner: or op or rtl ior inv 0 comp 0
 (define_insn "*fuse_or_xor"
-  [(set (match_operand:GPR 3 "gpc_reg_operand" "=r")
+  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r")
         (xor:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r") (match_operand:GPR 1 "gpc_reg_operand" "r")) (match_operand:GPR 2 "gpc_reg_operand" "r")))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "or %3,%1,%0\;xor %3,%3,%2"
@@ -1104,7 +1104,7 @@
 ;; kind: scalar outer: xor op xor rtl xor inv 0 comp 0
 ;; inner: orc op orc rtl ior inv 0 comp 1
 (define_insn "*fuse_orc_xor"
-  [(set (match_operand:GPR 3 "gpc_reg_operand" "=r")
+  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r")
         (xor:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r")) (match_operand:GPR 1 "gpc_reg_operand" "r")) (match_operand:GPR 2 "gpc_reg_operand" "r")))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "orc %3,%1,%0\;xor %3,%3,%2"
@@ -1116,7 +1116,7 @@
 ;; kind: scalar outer: xor op xor rtl xor inv 0 comp 0
 ;; inner: xor op xor rtl xor inv 0 comp 0
 (define_insn "*fuse_xor_xor"
-  [(set (match_operand:GPR 3 "gpc_reg_operand" "=r")
+  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r")
         (xor:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r") (match_operand:GPR 1 "gpc_reg_operand" "r")) (match_operand:GPR 2 "gpc_reg_operand" "r")))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "xor %3,%1,%0\;xor %3,%3,%2"
@@ -1128,7 +1128,7 @@
 ;; kind: vector outer: and op vand rtl and inv 0 comp 0
 ;; inner: and op vand rtl and inv 0 comp 0
 (define_insn "*fuse_vand_vand"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=v")
+  [(set (match_operand:VM 3 "altivec_register_operand" "=&v")
         (and:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v") (match_operand:VM 1 "altivec_register_operand" "v")) (match_operand:VM 2 "altivec_register_operand" "v")))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "vand %3,%1,%0\;vand %3,%3,%2"
@@ -1140,7 +1140,7 @@
 ;; kind: vector outer: and op vand rtl and inv 0 comp 0
 ;; inner: andc op vandc rtl and inv 0 comp 1
 (define_insn "*fuse_vandc_vand"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=v")
+  [(set (match_operand:VM 3 "altivec_register_operand" "=&v")
         (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v")) (match_operand:VM 1 "altivec_register_operand" "v")) (match_operand:VM 2 "altivec_register_operand" "v")))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "vandc %3,%1,%0\;vand %3,%3,%2"
@@ -1152,7 +1152,7 @@
 ;; kind: vector outer: and op vand rtl and inv 0 comp 0
 ;; inner: eqv op veqv rtl xor inv 1 comp 0
 (define_insn "*fuse_veqv_vand"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=v")
+  [(set (match_operand:VM 3 "altivec_register_operand" "=&v")
         (and:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v") (match_operand:VM 1 "altivec_register_operand" "v"))) (match_operand:VM 2 "altivec_register_operand" "v")))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "veqv %3,%1,%0\;vand %3,%3,%2"
@@ -1164,7 +1164,7 @@
 ;; kind: vector outer: and op vand rtl and inv 0 comp 0
 ;; inner: nand op vnand rtl ior inv 0 comp 3
 (define_insn "*fuse_vnand_vand"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=v")
+  [(set (match_operand:VM 3 "altivec_register_operand" "=&v")
         (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v"))) (match_operand:VM 2 "altivec_register_operand" "v")))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "vnand %3,%1,%0\;vand %3,%3,%2"
@@ -1176,7 +1176,7 @@
 ;; kind: vector outer: and op vand rtl and inv 0 comp 0
 ;; inner: nor op vnor rtl and inv 0 comp 3
 (define_insn "*fuse_vnor_vand"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=v")
+  [(set (match_operand:VM 3 "altivec_register_operand" "=&v")
         (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v"))) (match_operand:VM 2 "altivec_register_operand" "v")))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "vnor %3,%1,%0\;vand %3,%3,%2"
@@ -1188,7 +1188,7 @@
 ;; kind: vector outer: and op vand rtl and inv 0 comp 0
 ;; inner: or op vor rtl ior inv 0 comp 0
 (define_insn "*fuse_vor_vand"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=v")
+  [(set (match_operand:VM 3 "altivec_register_operand" "=&v")
         (and:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v") (match_operand:VM 1 "altivec_register_operand" "v")) (match_operand:VM 2 "altivec_register_operand" "v")))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "vor %3,%1,%0\;vand %3,%3,%2"
@@ -1200,7 +1200,7 @@
 ;; kind: vector outer: and op vand rtl and inv 0 comp 0
 ;; inner: orc op vorc rtl ior inv 0 comp 1
 (define_insn "*fuse_vorc_vand"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=v")
+  [(set (match_operand:VM 3 "altivec_register_operand" "=&v")
         (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v")) (match_operand:VM 1 "altivec_register_operand" "v")) (match_operand:VM 2 "altivec_register_operand" "v")))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "vorc %3,%1,%0\;vand %3,%3,%2"
@@ -1212,7 +1212,7 @@
 ;; kind: vector outer: and op vand rtl and inv 0 comp 0
 ;; inner: xor op vxor rtl xor inv 0 comp 0
 (define_insn "*fuse_vxor_vand"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=v")
+  [(set (match_operand:VM 3 "altivec_register_operand" "=&v")
         (and:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v") (match_operand:VM 1 "altivec_register_operand" "v")) (match_operand:VM 2 "altivec_register_operand" "v")))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "vxor %3,%1,%0\;vand %3,%3,%2"
@@ -1224,7 +1224,7 @@
 ;; kind: vector outer: andc op vandc rtl and inv 0 comp 1
 ;; inner: and op vand rtl and inv 0 comp 0
 (define_insn "*fuse_vand_vandc"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=v")
+  [(set (match_operand:VM 3 "altivec_register_operand" "=&v")
         (and:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v") (match_operand:VM 1 "altivec_register_operand" "v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "vand %3,%1,%0\;vandc %3,%3,%2"
@@ -1236,7 +1236,7 @@
 ;; kind: vector outer: andc op vandc rtl and inv 0 comp 1
 ;; inner: andc op vandc rtl and inv 0 comp 1
 (define_insn "*fuse_vandc_vandc"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=v")
+  [(set (match_operand:VM 3 "altivec_register_operand" "=&v")
         (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v")) (match_operand:VM 1 "altivec_register_operand" "v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "vandc %3,%1,%0\;vandc %3,%3,%2"
@@ -1248,7 +1248,7 @@
 ;; kind: vector outer: andc op vandc rtl and inv 0 comp 1
 ;; inner: eqv op veqv rtl xor inv 1 comp 0
 (define_insn "*fuse_veqv_vandc"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=v")
+  [(set (match_operand:VM 3 "altivec_register_operand" "=&v")
         (and:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v") (match_operand:VM 1 "altivec_register_operand" "v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "veqv %3,%1,%0\;vandc %3,%3,%2"
@@ -1260,7 +1260,7 @@
 ;; kind: vector outer: andc op vandc rtl and inv 0 comp 1
 ;; inner: nand op vnand rtl ior inv 0 comp 3
 (define_insn "*fuse_vnand_vandc"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=v")
+  [(set (match_operand:VM 3 "altivec_register_operand" "=&v")
         (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "vnand %3,%1,%0\;vandc %3,%3,%2"
@@ -1272,7 +1272,7 @@
 ;; kind: vector outer: andc op vandc rtl and inv 0 comp 1
 ;; inner: nor op vnor rtl and inv 0 comp 3
 (define_insn "*fuse_vnor_vandc"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=v")
+  [(set (match_operand:VM 3 "altivec_register_operand" "=&v")
         (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "vnor %3,%1,%0\;vandc %3,%3,%2"
@@ -1284,7 +1284,7 @@
 ;; kind: vector outer: andc op vandc rtl and inv 0 comp 1
 ;; inner: or op vor rtl ior inv 0 comp 0
 (define_insn "*fuse_vor_vandc"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=v")
+  [(set (match_operand:VM 3 "altivec_register_operand" "=&v")
         (and:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v") (match_operand:VM 1 "altivec_register_operand" "v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "vor %3,%1,%0\;vandc %3,%3,%2"
@@ -1296,7 +1296,7 @@
 ;; kind: vector outer: andc op vandc rtl and inv 0 comp 1
 ;; inner: orc op vorc rtl ior inv 0 comp 1
 (define_insn "*fuse_vorc_vandc"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=v")
+  [(set (match_operand:VM 3 "altivec_register_operand" "=&v")
         (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v")) (match_operand:VM 1 "altivec_register_operand" "v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "vorc %3,%1,%0\;vandc %3,%3,%2"
@@ -1308,7 +1308,7 @@
 ;; kind: vector outer: andc op vandc rtl and inv 0 comp 1
 ;; inner: xor op vxor rtl xor inv 0 comp 0
 (define_insn "*fuse_vxor_vandc"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=v")
+  [(set (match_operand:VM 3 "altivec_register_operand" "=&v")
         (and:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v") (match_operand:VM 1 "altivec_register_operand" "v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "vxor %3,%1,%0\;vandc %3,%3,%2"
@@ -1320,7 +1320,7 @@
 ;; kind: vector outer: eqv op veqv rtl xor inv 1 comp 0
 ;; inner: and op vand rtl and inv 0 comp 0
 (define_insn "*fuse_vand_veqv"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=v")
+  [(set (match_operand:VM 3 "altivec_register_operand" "=&v")
         (not:VM (xor:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v") (match_operand:VM 1 "altivec_register_operand" "v")) (match_operand:VM 2 "altivec_register_operand" "v"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "vand %3,%1,%0\;veqv %3,%3,%2"
@@ -1332,7 +1332,7 @@
 ;; kind: vector outer: eqv op veqv rtl xor inv 1 comp 0
 ;; inner: andc op vandc rtl and inv 0 comp 1
 (define_insn "*fuse_vandc_veqv"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=v")
+  [(set (match_operand:VM 3 "altivec_register_operand" "=&v")
         (not:VM (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v")) (match_operand:VM 1 "altivec_register_operand" "v")) (match_operand:VM 2 "altivec_register_operand" "v"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "vandc %3,%1,%0\;veqv %3,%3,%2"
@@ -1344,7 +1344,7 @@
 ;; kind: vector outer: eqv op veqv rtl xor inv 1 comp 0
 ;; inner: eqv op veqv rtl xor inv 1 comp 0
 (define_insn "*fuse_veqv_veqv"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=v")
+  [(set (match_operand:VM 3 "altivec_register_operand" "=&v")
         (not:VM (xor:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v") (match_operand:VM 1 "altivec_register_operand" "v"))) (match_operand:VM 2 "altivec_register_operand" "v"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "veqv %3,%1,%0\;veqv %3,%3,%2"
@@ -1356,7 +1356,7 @@
 ;; kind: vector outer: eqv op veqv rtl xor inv 1 comp 0
 ;; inner: nand op vnand rtl ior inv 0 comp 3
 (define_insn "*fuse_vnand_veqv"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=v")
+  [(set (match_operand:VM 3 "altivec_register_operand" "=&v")
         (not:VM (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v"))) (match_operand:VM 2 "altivec_register_operand" "v"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "vnand %3,%1,%0\;veqv %3,%3,%2"
@@ -1368,7 +1368,7 @@
 ;; kind: vector outer: eqv op veqv rtl xor inv 1 comp 0
 ;; inner: nor op vnor rtl and inv 0 comp 3
 (define_insn "*fuse_vnor_veqv"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=v")
+  [(set (match_operand:VM 3 "altivec_register_operand" "=&v")
         (not:VM (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v"))) (match_operand:VM 2 "altivec_register_operand" "v"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "vnor %3,%1,%0\;veqv %3,%3,%2"
@@ -1380,7 +1380,7 @@
 ;; kind: vector outer: eqv op veqv rtl xor inv 1 comp 0
 ;; inner: or op vor rtl ior inv 0 comp 0
 (define_insn "*fuse_vor_veqv"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=v")
+  [(set (match_operand:VM 3 "altivec_register_operand" "=&v")
         (not:VM (xor:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v") (match_operand:VM 1 "altivec_register_operand" "v")) (match_operand:VM 2 "altivec_register_operand" "v"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "vor %3,%1,%0\;veqv %3,%3,%2"
@@ -1392,7 +1392,7 @@
 ;; kind: vector outer: eqv op veqv rtl xor inv 1 comp 0
 ;; inner: orc op vorc rtl ior inv 0 comp 1
 (define_insn "*fuse_vorc_veqv"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=v")
+  [(set (match_operand:VM 3 "altivec_register_operand" "=&v")
         (not:VM (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v")) (match_operand:VM 1 "altivec_register_operand" "v")) (match_operand:VM 2 "altivec_register_operand" "v"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "vorc %3,%1,%0\;veqv %3,%3,%2"
@@ -1404,7 +1404,7 @@
 ;; kind: vector outer: eqv op veqv rtl xor inv 1 comp 0
 ;; inner: xor op vxor rtl xor inv 0 comp 0
 (define_insn "*fuse_vxor_veqv"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=v")
+  [(set (match_operand:VM 3 "altivec_register_operand" "=&v")
         (not:VM (xor:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v") (match_operand:VM 1 "altivec_register_operand" "v")) (match_operand:VM 2 "altivec_register_operand" "v"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "vxor %3,%1,%0\;veqv %3,%3,%2"
@@ -1416,7 +1416,7 @@
 ;; kind: vector outer: nand op vnand rtl ior inv 0 comp 3
 ;; inner: and op vand rtl and inv 0 comp 0
 (define_insn "*fuse_vand_vnand"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=v")
+  [(set (match_operand:VM 3 "altivec_register_operand" "=&v")
         (ior:VM (not:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v") (match_operand:VM 1 "altivec_register_operand" "v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "vand %3,%1,%0\;vnand %3,%3,%2"
@@ -1428,7 +1428,7 @@
 ;; kind: vector outer: nand op vnand rtl ior inv 0 comp 3
 ;; inner: andc op vandc rtl and inv 0 comp 1
 (define_insn "*fuse_vandc_vnand"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=v")
+  [(set (match_operand:VM 3 "altivec_register_operand" "=&v")
         (ior:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v")) (match_operand:VM 1 "altivec_register_operand" "v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "vandc %3,%1,%0\;vnand %3,%3,%2"
@@ -1440,7 +1440,7 @@
 ;; kind: vector outer: nand op vnand rtl ior inv 0 comp 3
 ;; inner: eqv op veqv rtl xor inv 1 comp 0
 (define_insn "*fuse_veqv_vnand"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=v")
+  [(set (match_operand:VM 3 "altivec_register_operand" "=&v")
         (ior:VM (not:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v") (match_operand:VM 1 "altivec_register_operand" "v")))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "veqv %3,%1,%0\;vnand %3,%3,%2"
@@ -1452,7 +1452,7 @@
 ;; kind: vector outer: nand op vnand rtl ior inv 0 comp 3
 ;; inner: nand op vnand rtl ior inv 0 comp 3
 (define_insn "*fuse_vnand_vnand"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=v")
+  [(set (match_operand:VM 3 "altivec_register_operand" "=&v")
         (ior:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v")))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "vnand %3,%1,%0\;vnand %3,%3,%2"
@@ -1464,7 +1464,7 @@
 ;; kind: vector outer: nand op vnand rtl ior inv 0 comp 3
 ;; inner: nor op vnor rtl and inv 0 comp 3
 (define_insn "*fuse_vnor_vnand"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=v")
+  [(set (match_operand:VM 3 "altivec_register_operand" "=&v")
         (ior:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v")))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "vnor %3,%1,%0\;vnand %3,%3,%2"
@@ -1476,7 +1476,7 @@
 ;; kind: vector outer: nand op vnand rtl ior inv 0 comp 3
 ;; inner: or op vor rtl ior inv 0 comp 0
 (define_insn "*fuse_vor_vnand"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=v")
+  [(set (match_operand:VM 3 "altivec_register_operand" "=&v")
         (ior:VM (not:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v") (match_operand:VM 1 "altivec_register_operand" "v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "vor %3,%1,%0\;vnand %3,%3,%2"
@@ -1488,7 +1488,7 @@
 ;; kind: vector outer: nand op vnand rtl ior inv 0 comp 3
 ;; inner: orc op vorc rtl ior inv 0 comp 1
 (define_insn "*fuse_vorc_vnand"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=v")
+  [(set (match_operand:VM 3 "altivec_register_operand" "=&v")
         (ior:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v")) (match_operand:VM 1 "altivec_register_operand" "v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "vorc %3,%1,%0\;vnand %3,%3,%2"
@@ -1500,7 +1500,7 @@
 ;; kind: vector outer: nand op vnand rtl ior inv 0 comp 3
 ;; inner: xor op vxor rtl xor inv 0 comp 0
 (define_insn "*fuse_vxor_vnand"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=v")
+  [(set (match_operand:VM 3 "altivec_register_operand" "=&v")
         (ior:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v") (match_operand:VM 1 "altivec_register_operand" "v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "vxor %3,%1,%0\;vnand %3,%3,%2"
@@ -1512,7 +1512,7 @@
 ;; kind: vector outer: nor op vnor rtl and inv 0 comp 3
 ;; inner: and op vand rtl and inv 0 comp 0
 (define_insn "*fuse_vand_vnor"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=v")
+  [(set (match_operand:VM 3 "altivec_register_operand" "=&v")
         (and:VM (not:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v") (match_operand:VM 1 "altivec_register_operand" "v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "vand %3,%1,%0\;vnor %3,%3,%2"
@@ -1524,7 +1524,7 @@
 ;; kind: vector outer: nor op vnor rtl and inv 0 comp 3
 ;; inner: andc op vandc rtl and inv 0 comp 1
 (define_insn "*fuse_vandc_vnor"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=v")
+  [(set (match_operand:VM 3 "altivec_register_operand" "=&v")
         (and:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v")) (match_operand:VM 1 "altivec_register_operand" "v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "vandc %3,%1,%0\;vnor %3,%3,%2"
@@ -1536,7 +1536,7 @@
 ;; kind: vector outer: nor op vnor rtl and inv 0 comp 3
 ;; inner: eqv op veqv rtl xor inv 1 comp 0
 (define_insn "*fuse_veqv_vnor"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=v")
+  [(set (match_operand:VM 3 "altivec_register_operand" "=&v")
         (and:VM (not:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v") (match_operand:VM 1 "altivec_register_operand" "v")))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "veqv %3,%1,%0\;vnor %3,%3,%2"
@@ -1548,7 +1548,7 @@
 ;; kind: vector outer: nor op vnor rtl and inv 0 comp 3
 ;; inner: nand op vnand rtl ior inv 0 comp 3
 (define_insn "*fuse_vnand_vnor"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=v")
+  [(set (match_operand:VM 3 "altivec_register_operand" "=&v")
         (and:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v")))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "vnand %3,%1,%0\;vnor %3,%3,%2"
@@ -1560,7 +1560,7 @@
 ;; kind: vector outer: nor op vnor rtl and inv 0 comp 3
 ;; inner: nor op vnor rtl and inv 0 comp 3
 (define_insn "*fuse_vnor_vnor"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=v")
+  [(set (match_operand:VM 3 "altivec_register_operand" "=&v")
         (and:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v")))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "vnor %3,%1,%0\;vnor %3,%3,%2"
@@ -1572,7 +1572,7 @@
 ;; kind: vector outer: nor op vnor rtl and inv 0 comp 3
 ;; inner: or op vor rtl ior inv 0 comp 0
 (define_insn "*fuse_vor_vnor"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=v")
+  [(set (match_operand:VM 3 "altivec_register_operand" "=&v")
         (and:VM (not:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v") (match_operand:VM 1 "altivec_register_operand" "v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "vor %3,%1,%0\;vnor %3,%3,%2"
@@ -1584,7 +1584,7 @@
 ;; kind: vector outer: nor op vnor rtl and inv 0 comp 3
 ;; inner: orc op vorc rtl ior inv 0 comp 1
 (define_insn "*fuse_vorc_vnor"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=v")
+  [(set (match_operand:VM 3 "altivec_register_operand" "=&v")
         (and:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v")) (match_operand:VM 1 "altivec_register_operand" "v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "vorc %3,%1,%0\;vnor %3,%3,%2"
@@ -1596,7 +1596,7 @@
 ;; kind: vector outer: nor op vnor rtl and inv 0 comp 3
 ;; inner: xor op vxor rtl xor inv 0 comp 0
 (define_insn "*fuse_vxor_vnor"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=v")
+  [(set (match_operand:VM 3 "altivec_register_operand" "=&v")
         (and:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v") (match_operand:VM 1 "altivec_register_operand" "v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "vxor %3,%1,%0\;vnor %3,%3,%2"
@@ -1608,7 +1608,7 @@
 ;; kind: vector outer: or op vor rtl ior inv 0 comp 0
 ;; inner: and op vand rtl and inv 0 comp 0
 (define_insn "*fuse_vand_vor"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=v")
+  [(set (match_operand:VM 3 "altivec_register_operand" "=&v")
         (ior:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v") (match_operand:VM 1 "altivec_register_operand" "v")) (match_operand:VM 2 "altivec_register_operand" "v")))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "vand %3,%1,%0\;vor %3,%3,%2"
@@ -1620,7 +1620,7 @@
 ;; kind: vector outer: or op vor rtl ior inv 0 comp 0
 ;; inner: andc op vandc rtl and inv 0 comp 1
 (define_insn "*fuse_vandc_vor"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=v")
+  [(set (match_operand:VM 3 "altivec_register_operand" "=&v")
         (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v")) (match_operand:VM 1 "altivec_register_operand" "v")) (match_operand:VM 2 "altivec_register_operand" "v")))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "vandc %3,%1,%0\;vor %3,%3,%2"
@@ -1632,7 +1632,7 @@
 ;; kind: vector outer: or op vor rtl ior inv 0 comp 0
 ;; inner: eqv op veqv rtl xor inv 1 comp 0
 (define_insn "*fuse_veqv_vor"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=v")
+  [(set (match_operand:VM 3 "altivec_register_operand" "=&v")
         (ior:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v") (match_operand:VM 1 "altivec_register_operand" "v"))) (match_operand:VM 2 "altivec_register_operand" "v")))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "veqv %3,%1,%0\;vor %3,%3,%2"
@@ -1644,7 +1644,7 @@
 ;; kind: vector outer: or op vor rtl ior inv 0 comp 0
 ;; inner: nand op vnand rtl ior inv 0 comp 3
 (define_insn "*fuse_vnand_vor"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=v")
+  [(set (match_operand:VM 3 "altivec_register_operand" "=&v")
         (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v"))) (match_operand:VM 2 "altivec_register_operand" "v")))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "vnand %3,%1,%0\;vor %3,%3,%2"
@@ -1656,7 +1656,7 @@
 ;; kind: vector outer: or op vor rtl ior inv 0 comp 0
 ;; inner: nor op vnor rtl and inv 0 comp 3
 (define_insn "*fuse_vnor_vor"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=v")
+  [(set (match_operand:VM 3 "altivec_register_operand" "=&v")
         (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v"))) (match_operand:VM 2 "altivec_register_operand" "v")))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "vnor %3,%1,%0\;vor %3,%3,%2"
@@ -1668,7 +1668,7 @@
 ;; kind: vector outer: or op vor rtl ior inv 0 comp 0
 ;; inner: or op vor rtl ior inv 0 comp 0
 (define_insn "*fuse_vor_vor"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=v")
+  [(set (match_operand:VM 3 "altivec_register_operand" "=&v")
         (ior:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v") (match_operand:VM 1 "altivec_register_operand" "v")) (match_operand:VM 2 "altivec_register_operand" "v")))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "vor %3,%1,%0\;vor %3,%3,%2"
@@ -1680,7 +1680,7 @@
 ;; kind: vector outer: or op vor rtl ior inv 0 comp 0
 ;; inner: orc op vorc rtl ior inv 0 comp 1
 (define_insn "*fuse_vorc_vor"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=v")
+  [(set (match_operand:VM 3 "altivec_register_operand" "=&v")
         (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v")) (match_operand:VM 1 "altivec_register_operand" "v")) (match_operand:VM 2 "altivec_register_operand" "v")))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "vorc %3,%1,%0\;vor %3,%3,%2"
@@ -1692,7 +1692,7 @@
 ;; kind: vector outer: or op vor rtl ior inv 0 comp 0
 ;; inner: xor op vxor rtl xor inv 0 comp 0
 (define_insn "*fuse_vxor_vor"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=v")
+  [(set (match_operand:VM 3 "altivec_register_operand" "=&v")
         (ior:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v") (match_operand:VM 1 "altivec_register_operand" "v")) (match_operand:VM 2 "altivec_register_operand" "v")))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "vxor %3,%1,%0\;vor %3,%3,%2"
@@ -1704,7 +1704,7 @@
 ;; kind: vector outer: orc op vorc rtl ior inv 0 comp 1
 ;; inner: and op vand rtl and inv 0 comp 0
 (define_insn "*fuse_vand_vorc"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=v")
+  [(set (match_operand:VM 3 "altivec_register_operand" "=&v")
         (ior:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v") (match_operand:VM 1 "altivec_register_operand" "v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "vand %3,%1,%0\;vorc %3,%3,%2"
@@ -1716,7 +1716,7 @@
 ;; kind: vector outer: orc op vorc rtl ior inv 0 comp 1
 ;; inner: andc op vandc rtl and inv 0 comp 1
 (define_insn "*fuse_vandc_vorc"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=v")
+  [(set (match_operand:VM 3 "altivec_register_operand" "=&v")
         (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v")) (match_operand:VM 1 "altivec_register_operand" "v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "vandc %3,%1,%0\;vorc %3,%3,%2"
@@ -1728,7 +1728,7 @@
 ;; kind: vector outer: orc op vorc rtl ior inv 0 comp 1
 ;; inner: eqv op veqv rtl xor inv 1 comp 0
 (define_insn "*fuse_veqv_vorc"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=v")
+  [(set (match_operand:VM 3 "altivec_register_operand" "=&v")
         (ior:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v") (match_operand:VM 1 "altivec_register_operand" "v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "veqv %3,%1,%0\;vorc %3,%3,%2"
@@ -1740,7 +1740,7 @@
 ;; kind: vector outer: orc op vorc rtl ior inv 0 comp 1
 ;; inner: nand op vnand rtl ior inv 0 comp 3
 (define_insn "*fuse_vnand_vorc"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=v")
+  [(set (match_operand:VM 3 "altivec_register_operand" "=&v")
         (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "vnand %3,%1,%0\;vorc %3,%3,%2"
@@ -1752,7 +1752,7 @@
 ;; kind: vector outer: orc op vorc rtl ior inv 0 comp 1
 ;; inner: nor op vnor rtl and inv 0 comp 3
 (define_insn "*fuse_vnor_vorc"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=v")
+  [(set (match_operand:VM 3 "altivec_register_operand" "=&v")
         (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "vnor %3,%1,%0\;vorc %3,%3,%2"
@@ -1764,7 +1764,7 @@
 ;; kind: vector outer: orc op vorc rtl ior inv 0 comp 1
 ;; inner: or op vor rtl ior inv 0 comp 0
 (define_insn "*fuse_vor_vorc"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=v")
+  [(set (match_operand:VM 3 "altivec_register_operand" "=&v")
         (ior:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v") (match_operand:VM 1 "altivec_register_operand" "v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "vor %3,%1,%0\;vorc %3,%3,%2"
@@ -1776,7 +1776,7 @@
 ;; kind: vector outer: orc op vorc rtl ior inv 0 comp 1
 ;; inner: orc op vorc rtl ior inv 0 comp 1
 (define_insn "*fuse_vorc_vorc"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=v")
+  [(set (match_operand:VM 3 "altivec_register_operand" "=&v")
         (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v")) (match_operand:VM 1 "altivec_register_operand" "v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "vorc %3,%1,%0\;vorc %3,%3,%2"
@@ -1788,7 +1788,7 @@
 ;; kind: vector outer: orc op vorc rtl ior inv 0 comp 1
 ;; inner: xor op vxor rtl xor inv 0 comp 0
 (define_insn "*fuse_vxor_vorc"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=v")
+  [(set (match_operand:VM 3 "altivec_register_operand" "=&v")
         (ior:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v") (match_operand:VM 1 "altivec_register_operand" "v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v"))))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "vxor %3,%1,%0\;vorc %3,%3,%2"
@@ -1800,7 +1800,7 @@
 ;; kind: vector outer: xor op vxor rtl xor inv 0 comp 0
 ;; inner: and op vand rtl and inv 0 comp 0
 (define_insn "*fuse_vand_vxor"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=v")
+  [(set (match_operand:VM 3 "altivec_register_operand" "=&v")
         (xor:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v") (match_operand:VM 1 "altivec_register_operand" "v")) (match_operand:VM 2 "altivec_register_operand" "v")))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "vand %3,%1,%0\;vxor %3,%3,%2"
@@ -1812,7 +1812,7 @@
 ;; kind: vector outer: xor op vxor rtl xor inv 0 comp 0
 ;; inner: andc op vandc rtl and inv 0 comp 1
 (define_insn "*fuse_vandc_vxor"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=v")
+  [(set (match_operand:VM 3 "altivec_register_operand" "=&v")
         (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v")) (match_operand:VM 1 "altivec_register_operand" "v")) (match_operand:VM 2 "altivec_register_operand" "v")))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "vandc %3,%1,%0\;vxor %3,%3,%2"
@@ -1824,7 +1824,7 @@
 ;; kind: vector outer: xor op vxor rtl xor inv 0 comp 0
 ;; inner: eqv op veqv rtl xor inv 1 comp 0
 (define_insn "*fuse_veqv_vxor"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=v")
+  [(set (match_operand:VM 3 "altivec_register_operand" "=&v")
         (xor:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v") (match_operand:VM 1 "altivec_register_operand" "v"))) (match_operand:VM 2 "altivec_register_operand" "v")))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "veqv %3,%1,%0\;vxor %3,%3,%2"
@@ -1836,7 +1836,7 @@
 ;; kind: vector outer: xor op vxor rtl xor inv 0 comp 0
 ;; inner: nand op vnand rtl ior inv 0 comp 3
 (define_insn "*fuse_vnand_vxor"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=v")
+  [(set (match_operand:VM 3 "altivec_register_operand" "=&v")
         (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v"))) (match_operand:VM 2 "altivec_register_operand" "v")))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "vnand %3,%1,%0\;vxor %3,%3,%2"
@@ -1848,7 +1848,7 @@
 ;; kind: vector outer: xor op vxor rtl xor inv 0 comp 0
 ;; inner: nor op vnor rtl and inv 0 comp 3
 (define_insn "*fuse_vnor_vxor"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=v")
+  [(set (match_operand:VM 3 "altivec_register_operand" "=&v")
         (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v"))) (match_operand:VM 2 "altivec_register_operand" "v")))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "vnor %3,%1,%0\;vxor %3,%3,%2"
@@ -1860,7 +1860,7 @@
 ;; kind: vector outer: xor op vxor rtl xor inv 0 comp 0
 ;; inner: or op vor rtl ior inv 0 comp 0
 (define_insn "*fuse_vor_vxor"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=v")
+  [(set (match_operand:VM 3 "altivec_register_operand" "=&v")
         (xor:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v") (match_operand:VM 1 "altivec_register_operand" "v")) (match_operand:VM 2 "altivec_register_operand" "v")))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "vor %3,%1,%0\;vxor %3,%3,%2"
@@ -1872,7 +1872,7 @@
 ;; kind: vector outer: xor op vxor rtl xor inv 0 comp 0
 ;; inner: orc op vorc rtl ior inv 0 comp 1
 (define_insn "*fuse_vorc_vxor"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=v")
+  [(set (match_operand:VM 3 "altivec_register_operand" "=&v")
         (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v")) (match_operand:VM 1 "altivec_register_operand" "v")) (match_operand:VM 2 "altivec_register_operand" "v")))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "vorc %3,%1,%0\;vxor %3,%3,%2"
@@ -1884,7 +1884,7 @@
 ;; kind: vector outer: xor op vxor rtl xor inv 0 comp 0
 ;; inner: xor op vxor rtl xor inv 0 comp 0
 (define_insn "*fuse_vxor_vxor"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=v")
+  [(set (match_operand:VM 3 "altivec_register_operand" "=&v")
         (xor:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v") (match_operand:VM 1 "altivec_register_operand" "v")) (match_operand:VM 2 "altivec_register_operand" "v")))]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "vxor %3,%1,%0\;vxor %3,%3,%2"
diff --git a/gcc/config/rs6000/genfusion.pl b/gcc/config/rs6000/genfusion.pl
index 15769aaede1..44cea5ed0e3 100755
--- a/gcc/config/rs6000/genfusion.pl
+++ b/gcc/config/rs6000/genfusion.pl
@@ -200,7 +200,7 @@ sub gen_2logical
 ;; kind: $kind outer: $outer op $outer_op rtl $outer_rtl inv $outer_inv comp $outer_comp
 ;; inner: $inner op $inner_op rtl $inner_rtl inv $inner_inv comp $inner_comp
 (define_insn "*fuse_${inner_op}_${outer_op}"
-  [(set (match_operand:${mode} 3 "${pred}" "=${constraint}")
+  [(set (match_operand:${mode} 3 "${pred}" "=&${constraint}")
         ${outer_exp})]
   "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
   "${inner_op} %3,%1,%0\\;${outer_op} %3,%3,%2"


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