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* [gcc(refs/users/clyon/heads/mve-autovec)] arm: Auto-vectorization for MVE: veor
@ 2020-12-16 13:48 Christophe Lyon
  0 siblings, 0 replies; 6+ messages in thread
From: Christophe Lyon @ 2020-12-16 13:48 UTC (permalink / raw)
  To: gcc-cvs

https://gcc.gnu.org/g:9af79eeb4e6b5c330fd0c9c10127ef07448cf324

commit 9af79eeb4e6b5c330fd0c9c10127ef07448cf324
Author: Christophe Lyon <christophe.lyon@linaro.org>
Date:   Fri Nov 13 13:05:43 2020 +0000

    arm: Auto-vectorization for MVE: veor
    
    This patch enables MVE veorq instructions for auto-vectorization.  MVE
    veorq insns in mve.md are modified to use xor instead of unspec
    expression to support xor<mode>3.  The xor<mode>3 expander is added to
    vec-common.md
    
    2020-12-11  Christophe Lyon  <christophe.lyon@linaro.org>
    
            gcc/
            * config/arm/iterators.md (supf): Remove VEORQ_S and VEORQ_U.
            (VEORQ): Remove.
            * config/arm/mve.md (mve_veorq_u<mode>): New entry for veor
            instruction using expression xor.
            (mve_veorq_s<mode>): New expander.
            (mve_veorq_f<mode>): Use 'xor' code instead of unspec.
            * config/arm/neon.md (xor<mode>3): Renamed into xor<mode>3_neon.
            * config/arm/unspecs.md (VEORQ_S, VEORQ_U, VEORQ_F): Remove.
            * config/arm/vec-common.md (xor<mode>3): New expander.
    
            gcc/testsuite/
            * gcc.target/arm/simd/mve-veor.c: Add tests for veor.

Diff:
---
 gcc/config/arm/iterators.md                  |  3 +-
 gcc/config/arm/mve.md                        | 22 ++++++----
 gcc/config/arm/neon.md                       |  2 +-
 gcc/config/arm/unspecs.md                    |  3 --
 gcc/config/arm/vec-common.md                 |  7 ++++
 gcc/testsuite/gcc.target/arm/simd/mve-veor.c | 61 ++++++++++++++++++++++++++++
 6 files changed, 84 insertions(+), 14 deletions(-)

diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index 5fcb7afe565..01952756e08 100644
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -1237,7 +1237,7 @@
 		       (VCADDQ_ROT270_U "u") (VCADDQ_ROT90_S "s")
 		       (VCMPEQQ_S "s") (VCMPEQQ_U "u") (VCADDQ_ROT90_U "u")
 		       (VCMPEQQ_N_S "s") (VCMPEQQ_N_U "u") (VCMPNEQ_N_S "s")
-		       (VCMPNEQ_N_U "u") (VEORQ_S "s") (VEORQ_U "u")
+		       (VCMPNEQ_N_U "u")
 		       (VHADDQ_N_S "s") (VHADDQ_N_U "u") (VHADDQ_S "s")
 		       (VHADDQ_U "u") (VHSUBQ_N_S "s")	(VHSUBQ_N_U "u")
 		       (VHSUBQ_S "s") (VMAXQ_S "s") (VMAXQ_U "u") (VHSUBQ_U "u")
@@ -1507,7 +1507,6 @@
 (define_int_iterator VCMPEQQ [VCMPEQQ_U VCMPEQQ_S])
 (define_int_iterator VCMPEQQ_N [VCMPEQQ_N_S VCMPEQQ_N_U])
 (define_int_iterator VCMPNEQ_N [VCMPNEQ_N_U VCMPNEQ_N_S])
-(define_int_iterator VEORQ [VEORQ_U VEORQ_S])
 (define_int_iterator VHADDQ [VHADDQ_S VHADDQ_U])
 (define_int_iterator VHADDQ_N [VHADDQ_N_U VHADDQ_N_S])
 (define_int_iterator VHSUBQ [VHSUBQ_S VHSUBQ_U])
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 4b2e46afc19..10512ad0007 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -1207,17 +1207,24 @@
 ;;
 ;; [veorq_u, veorq_s])
 ;;
-(define_insn "mve_veorq_<supf><mode>"
+(define_insn "mve_veorq_u<mode>"
   [
    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
-	(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
-		       (match_operand:MVE_2 2 "s_register_operand" "w")]
-	 VEORQ))
+	(xor:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w")
+		   (match_operand:MVE_2 2 "s_register_operand" "w")))
   ]
   "TARGET_HAVE_MVE"
-  "veor %q0, %q1, %q2"
+  "veor\t%q0, %q1, %q2"
   [(set_attr "type" "mve_move")
 ])
+(define_expand "mve_veorq_s<mode>"
+  [
+   (set (match_operand:MVE_2 0 "s_register_operand")
+	(xor:MVE_2 (match_operand:MVE_2 1 "s_register_operand")
+		   (match_operand:MVE_2 2 "s_register_operand")))
+  ]
+  "TARGET_HAVE_MVE"
+)
 
 ;;
 ;; [vhaddq_n_u, vhaddq_n_s])
@@ -2404,9 +2411,8 @@
 (define_insn "mve_veorq_f<mode>"
   [
    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
-	(unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
-		       (match_operand:MVE_0 2 "s_register_operand" "w")]
-	 VEORQ_F))
+	(xor:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w")
+		   (match_operand:MVE_0 2 "s_register_operand" "w")))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
   "veor %q0, %q1, %q2"
diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index 669c34da4e0..e1263b00b39 100644
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -747,7 +747,7 @@
   [(set_attr "type" "neon_logic<q>")]
 )
 
-(define_insn "xor<mode>3"
+(define_insn "xor<mode>3_neon"
   [(set (match_operand:VDQ 0 "s_register_operand" "=w")
 	(xor:VDQ (match_operand:VDQ 1 "s_register_operand" "w")
 		 (match_operand:VDQ 2 "s_register_operand" "w")))]
diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md
index c2076c9ce6f..fe240e8968a 100644
--- a/gcc/config/arm/unspecs.md
+++ b/gcc/config/arm/unspecs.md
@@ -608,7 +608,6 @@
   VCMPEQQ_S
   VCMPEQQ_N_S
   VCMPNEQ_N_S
-  VEORQ_S
   VHADDQ_S
   VHADDQ_N_S
   VHSUBQ_S
@@ -653,7 +652,6 @@
   VCMPEQQ_U
   VCMPEQQ_N_U
   VCMPNEQ_N_U
-  VEORQ_U
   VHADDQ_U
   VHADDQ_N_U
   VHSUBQ_U
@@ -736,7 +734,6 @@
   VCMULQ_ROT180_F
   VCMULQ_ROT270_F
   VCMULQ_ROT90_F
-  VEORQ_F
   VMAXNMAQ_F
   VMAXNMAVQ_F
   VMAXNMQ_F
diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md
index 8d9c89c5b2b..030ed82ca7e 100644
--- a/gcc/config/arm/vec-common.md
+++ b/gcc/config/arm/vec-common.md
@@ -186,3 +186,10 @@
 		 (match_operand:VDQ 2 "neon_logic_op2" "")))]
   "ARM_HAVE_<MODE>_ARITH"
 )
+
+(define_expand "xor<mode>3"
+  [(set (match_operand:VDQ 0 "s_register_operand" "")
+	(xor:VDQ (match_operand:VDQ 1 "s_register_operand" "")
+		 (match_operand:VDQ 2 "s_register_operand" "")))]
+  "ARM_HAVE_<MODE>_ARITH"
+)
diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-veor.c b/gcc/testsuite/gcc.target/arm/simd/mve-veor.c
new file mode 100644
index 00000000000..321961f251e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/mve-veor.c
@@ -0,0 +1,61 @@
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O3" } */
+
+#include <stdint.h>
+
+#define FUNC(SIGN, TYPE, BITS, NB, OP, NAME)				\
+  void test_ ## NAME ##_ ## SIGN ## BITS ## x ## NB (TYPE##BITS##_t * __restrict__ dest, TYPE##BITS##_t *a, TYPE##BITS##_t *b) { \
+    int i;								\
+    for (i=0; i<NB; i++) {						\
+      dest[i] = a[i] OP b[i];						\
+    }									\
+}
+
+#define FUNC_IMM(SIGN, TYPE, BITS, NB, OP, NAME)				\
+  void test_ ## NAME ##_ ## SIGN ## BITS ## x ## NB (TYPE##BITS##_t * __restrict__ dest, TYPE##BITS##_t *a) { \
+    int i;								\
+    for (i=0; i<NB; i++) {						\
+      dest[i] = a[i] OP 1;						\
+    }									\
+}
+
+/* 64-bit vectors.  */
+FUNC(s, int, 32, 2, ^, veor)
+FUNC(u, uint, 32, 2, ^, veor)
+FUNC(s, int, 16, 4, ^, veor)
+FUNC(u, uint, 16, 4, ^, veor)
+FUNC(s, int, 8, 8, ^, veor)
+FUNC(u, uint, 8, 8, ^, veor)
+
+/* 128-bit vectors.  */
+FUNC(s, int, 32, 4, ^, veor)
+FUNC(u, uint, 32, 4, ^, veor)
+FUNC(s, int, 16, 8, ^, veor)
+FUNC(u, uint, 16, 8, ^, veor)
+FUNC(s, int, 8, 16, ^, veor)
+FUNC(u, uint, 8, 16, ^, veor)
+
+/* 64-bit vectors.  */
+FUNC_IMM(s, int, 32, 2, ^, veorimm)
+FUNC_IMM(u, uint, 32, 2, ^, veorimm)
+FUNC_IMM(s, int, 16, 4, ^, veorimm)
+FUNC_IMM(u, uint, 16, 4, ^, veorimm)
+FUNC_IMM(s, int, 8, 8, ^, veorimm)
+FUNC_IMM(u, uint, 8, 8, ^, veorimm)
+
+/* 128-bit vectors.  */
+FUNC_IMM(s, int, 32, 4, ^, veorimm)
+FUNC_IMM(u, uint, 32, 4, ^, veorimm)
+FUNC_IMM(s, int, 16, 8, ^, veorimm)
+FUNC_IMM(u, uint, 16, 8, ^, veorimm)
+FUNC_IMM(s, int, 8, 16, ^, veorimm)
+FUNC_IMM(u, uint, 8, 16, ^, veorimm)
+
+/* MVE has only 128-bit vectors, so we can vectorize only half of the
+   functions above.  */
+/* Although float16 and float32 types are supported at assembly level,
+   we cannot test them with the '^' operator, so we check only the
+   integer variants.  */
+/* { dg-final { scan-assembler-times {veor\tq[0-9]+, q[0-9]+, q[0-9]+} 12 } } */


^ permalink raw reply	[flat|nested] 6+ messages in thread
* [gcc(refs/users/clyon/heads/mve-autovec)] arm: Auto-vectorization for MVE: veor
@ 2020-11-24 22:31 Christophe Lyon
  0 siblings, 0 replies; 6+ messages in thread
From: Christophe Lyon @ 2020-11-24 22:31 UTC (permalink / raw)
  To: gcc-cvs

https://gcc.gnu.org/g:7692471492fd0f974ce34b34fba04b8a02fb7822

commit 7692471492fd0f974ce34b34fba04b8a02fb7822
Author: Christophe Lyon <christophe.lyon@linaro.org>
Date:   Fri Nov 13 13:05:43 2020 +0000

    arm: Auto-vectorization for MVE: veor
    
    This patch enables MVE veorq instructions for auto-vectorization.  MVE
    veorq insns in mve.md are modified to use xor instead of unspec
    expression to support xor<mode>3.  The xor<mode>3 expander is added to
    vec-common.md
    
    2020-11-12  Christophe Lyon  <christophe.lyon@linaro.org>
    
            gcc/
            * config/arm/iterators.md (supf): Remove VEORQ_S and VEORQ_U.
            (VEORQ): Remove.
            * config/arm/mve.md (mve_veorq_u<mode>): New entry for veor
            instruction using expression xor.
            (mve_veorq_s<mode>): New expander.
            * config/arm/neon.md (xor<mode>3): Renamed into xor<mode>3_neon.
            * config/arm/unspscs.md (VEORQ_S, VEORQ_U): Remove.
            * config/arm/vec-common.md (xor<mode>3): New expander.
    
            gcc/testsuite/
            * gcc.target/arm/simd/mve-veor.c: Add tests for veor.

Diff:
---
 gcc/config/arm/iterators.md                  |  3 +--
 gcc/config/arm/mve.md                        | 17 ++++++++++----
 gcc/config/arm/neon.md                       |  2 +-
 gcc/config/arm/unspecs.md                    |  2 --
 gcc/config/arm/vec-common.md                 | 14 ++++++++++++
 gcc/testsuite/gcc.target/arm/simd/mve-veor.c | 34 ++++++++++++++++++++++++++++
 6 files changed, 62 insertions(+), 10 deletions(-)

diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index 5fcb7afe565..01952756e08 100644
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -1237,7 +1237,7 @@
 		       (VCADDQ_ROT270_U "u") (VCADDQ_ROT90_S "s")
 		       (VCMPEQQ_S "s") (VCMPEQQ_U "u") (VCADDQ_ROT90_U "u")
 		       (VCMPEQQ_N_S "s") (VCMPEQQ_N_U "u") (VCMPNEQ_N_S "s")
-		       (VCMPNEQ_N_U "u") (VEORQ_S "s") (VEORQ_U "u")
+		       (VCMPNEQ_N_U "u")
 		       (VHADDQ_N_S "s") (VHADDQ_N_U "u") (VHADDQ_S "s")
 		       (VHADDQ_U "u") (VHSUBQ_N_S "s")	(VHSUBQ_N_U "u")
 		       (VHSUBQ_S "s") (VMAXQ_S "s") (VMAXQ_U "u") (VHSUBQ_U "u")
@@ -1507,7 +1507,6 @@
 (define_int_iterator VCMPEQQ [VCMPEQQ_U VCMPEQQ_S])
 (define_int_iterator VCMPEQQ_N [VCMPEQQ_N_S VCMPEQQ_N_U])
 (define_int_iterator VCMPNEQ_N [VCMPNEQ_N_U VCMPNEQ_N_S])
-(define_int_iterator VEORQ [VEORQ_U VEORQ_S])
 (define_int_iterator VHADDQ [VHADDQ_S VHADDQ_U])
 (define_int_iterator VHADDQ_N [VHADDQ_N_U VHADDQ_N_S])
 (define_int_iterator VHSUBQ [VHSUBQ_S VHSUBQ_U])
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 0f040444861..a5f5d7527f4 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -1204,17 +1204,24 @@
 ;;
 ;; [veorq_u, veorq_s])
 ;;
-(define_insn "mve_veorq_<supf><mode>"
+(define_insn "mve_veorq_u<mode>"
   [
    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
-	(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
-		       (match_operand:MVE_2 2 "s_register_operand" "w")]
-	 VEORQ))
+	(xor:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w")
+		       (match_operand:MVE_2 2 "s_register_operand" "w")))
   ]
   "TARGET_HAVE_MVE"
-  "veor %q0, %q1, %q2"
+  "veor\t%q0, %q1, %q2"
   [(set_attr "type" "mve_move")
 ])
+(define_expand "mve_veorq_s<mode>"
+  [
+   (set (match_operand:MVE_2 0 "s_register_operand")
+	(xor:MVE_2 (match_operand:MVE_2 1 "s_register_operand")
+		       (match_operand:MVE_2 2 "s_register_operand")))
+  ]
+  "TARGET_HAVE_MVE"
+)
 
 ;;
 ;; [vhaddq_n_u, vhaddq_n_s])
diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index 669c34da4e0..e1263b00b39 100644
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -747,7 +747,7 @@
   [(set_attr "type" "neon_logic<q>")]
 )
 
-(define_insn "xor<mode>3"
+(define_insn "xor<mode>3_neon"
   [(set (match_operand:VDQ 0 "s_register_operand" "=w")
 	(xor:VDQ (match_operand:VDQ 1 "s_register_operand" "w")
 		 (match_operand:VDQ 2 "s_register_operand" "w")))]
diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md
index f111ad80ead..78313ea87bc 100644
--- a/gcc/config/arm/unspecs.md
+++ b/gcc/config/arm/unspecs.md
@@ -608,7 +608,6 @@
   VCMPEQQ_S
   VCMPEQQ_N_S
   VCMPNEQ_N_S
-  VEORQ_S
   VHADDQ_S
   VHADDQ_N_S
   VHSUBQ_S
@@ -653,7 +652,6 @@
   VCMPEQQ_U
   VCMPEQQ_N_U
   VCMPNEQ_N_U
-  VEORQ_U
   VHADDQ_U
   VHADDQ_N_U
   VHSUBQ_U
diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md
index 413fb07a9be..7825caa4e43 100644
--- a/gcc/config/arm/vec-common.md
+++ b/gcc/config/arm/vec-common.md
@@ -201,4 +201,18 @@
 	(ior:VNINOTM1 (match_operand:VNINOTM1 1 "s_register_operand" "")
 		      (match_operand:VNINOTM1 2 "neon_logic_op2" "")))]
   "TARGET_NEON"
+
+(define_expand "xor<mode>3"
+  [(set (match_operand:VNIM1 0 "s_register_operand" "")
+	(xor:VNIM1 (match_operand:VNIM1 1 "s_register_operand" "")
+		   (match_operand:VNIM1 2 "s_register_operand" "")))]
+  "TARGET_NEON
+   || (TARGET_HAVE_MVE && VALID_MVE_SI_MODE (<MODE>mode))"
+)
+
+(define_expand "xor<mode>3"
+  [(set (match_operand:VNINOTM1 0 "s_register_operand" "")
+	(xor:VNINOTM1 (match_operand:VNINOTM1 1 "s_register_operand" "")
+		      (match_operand:VNINOTM1 2 "s_register_operand" "")))]
+  "TARGET_NEON"
 )
diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-veor.c b/gcc/testsuite/gcc.target/arm/simd/mve-veor.c
new file mode 100644
index 00000000000..5c534ccedb0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/mve-veor.c
@@ -0,0 +1,34 @@
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O3" } */
+
+#include <stdint.h>
+
+#define FUNC(SIGN, TYPE, BITS, NB, OP, NAME)				\
+  void test_ ## NAME ##_ ## SIGN ## BITS ## x ## NB (TYPE##BITS##_t * __restrict__ dest, TYPE##BITS##_t *a, TYPE##BITS##_t *b) { \
+    int i;								\
+    for (i=0; i<NB; i++) {						\
+      dest[i] = a[i] OP b[i];						\
+    }									\
+}
+
+/* 64-bit vectors.  */
+FUNC(s, int, 32, 2, ^, veor)
+FUNC(u, uint, 32, 2, ^, veor)
+FUNC(s, int, 16, 4, ^, veor)
+FUNC(u, uint, 16, 4, ^, veor)
+FUNC(s, int, 8, 8, ^, veor)
+FUNC(u, uint, 8, 8, ^, veor)
+
+/* 128-bit vectors.  */
+FUNC(s, int, 32, 4, ^, veor)
+FUNC(u, uint, 32, 4, ^, veor)
+FUNC(s, int, 16, 8, ^, veor)
+FUNC(u, uint, 16, 8, ^, veor)
+FUNC(s, int, 8, 16, ^, veor)
+FUNC(u, uint, 8, 16, ^, veor)
+
+/* MVE has only 128-bit vectors, so we can vectorize only half of the
+   functions above.  */
+/* { dg-final { scan-assembler-times {veor\tq[0-9]+, q[0-9]+, q[0-9]+} 6 } } */


^ permalink raw reply	[flat|nested] 6+ messages in thread
* [gcc(refs/users/clyon/heads/mve-autovec)] arm: Auto-vectorization for MVE: veor
@ 2020-11-23 10:42 Christophe Lyon
  0 siblings, 0 replies; 6+ messages in thread
From: Christophe Lyon @ 2020-11-23 10:42 UTC (permalink / raw)
  To: gcc-cvs

https://gcc.gnu.org/g:8e5c88e0e2b6503c85e8291c2def2498223c408a

commit 8e5c88e0e2b6503c85e8291c2def2498223c408a
Author: Christophe Lyon <christophe.lyon@linaro.org>
Date:   Fri Nov 13 13:05:43 2020 +0000

    arm: Auto-vectorization for MVE: veor
    
    This patch enables MVE veorq instructions for auto-vectorization.  MVE
    veorq insns in mve.md are modified to use xor instead of unspec
    expression to support xor<mode>3.  The xor<mode>3 expander is added to
    vec-common.md
    
    2020-11-12  Christophe Lyon  <christophe.lyon@linaro.org>
    
            gcc/
            * config/arm/iterators.md (supf): Remove VEORQ_S and VEORQ_U.
            (VEORQ): Remove.
            * config/arm/mve.md (mve_veorq_u<mode>): New entry for veor
            instruction using expression xor.
            (mve_veorq_s<mode>): New expander.
            * config/arm/neon.md (xor<mode>3): Renamed into xor<mode>3_neon.
            * config/arm/unspscs.md (VEORQ_S, VEORQ_U): Remove.
            * config/arm/vec-common.md (xor<mode>3): New expander.
    
            gcc/testsuite/
            * gcc.target/arm/simd/mve-veor.c: Add tests for veor.

Diff:
---
 gcc/config/arm/iterators.md                  |  3 +-
 gcc/config/arm/mve.md                        | 17 +++--
 gcc/config/arm/neon.md                       |  2 +-
 gcc/config/arm/unspecs.md                    |  2 -
 gcc/config/arm/vec-common.md                 |  9 ++-
 gcc/testsuite/gcc.target/arm/simd/mve-veor.c | 96 ++++++++++++++++++++++++++++
 6 files changed, 118 insertions(+), 11 deletions(-)

diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index 5fcb7afe565..01952756e08 100644
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -1237,7 +1237,7 @@
 		       (VCADDQ_ROT270_U "u") (VCADDQ_ROT90_S "s")
 		       (VCMPEQQ_S "s") (VCMPEQQ_U "u") (VCADDQ_ROT90_U "u")
 		       (VCMPEQQ_N_S "s") (VCMPEQQ_N_U "u") (VCMPNEQ_N_S "s")
-		       (VCMPNEQ_N_U "u") (VEORQ_S "s") (VEORQ_U "u")
+		       (VCMPNEQ_N_U "u")
 		       (VHADDQ_N_S "s") (VHADDQ_N_U "u") (VHADDQ_S "s")
 		       (VHADDQ_U "u") (VHSUBQ_N_S "s")	(VHSUBQ_N_U "u")
 		       (VHSUBQ_S "s") (VMAXQ_S "s") (VMAXQ_U "u") (VHSUBQ_U "u")
@@ -1507,7 +1507,6 @@
 (define_int_iterator VCMPEQQ [VCMPEQQ_U VCMPEQQ_S])
 (define_int_iterator VCMPEQQ_N [VCMPEQQ_N_S VCMPEQQ_N_U])
 (define_int_iterator VCMPNEQ_N [VCMPNEQ_N_U VCMPNEQ_N_S])
-(define_int_iterator VEORQ [VEORQ_U VEORQ_S])
 (define_int_iterator VHADDQ [VHADDQ_S VHADDQ_U])
 (define_int_iterator VHADDQ_N [VHADDQ_N_U VHADDQ_N_S])
 (define_int_iterator VHSUBQ [VHSUBQ_S VHSUBQ_U])
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 0f040444861..a5f5d7527f4 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -1204,17 +1204,24 @@
 ;;
 ;; [veorq_u, veorq_s])
 ;;
-(define_insn "mve_veorq_<supf><mode>"
+(define_insn "mve_veorq_u<mode>"
   [
    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
-	(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
-		       (match_operand:MVE_2 2 "s_register_operand" "w")]
-	 VEORQ))
+	(xor:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w")
+		       (match_operand:MVE_2 2 "s_register_operand" "w")))
   ]
   "TARGET_HAVE_MVE"
-  "veor %q0, %q1, %q2"
+  "veor\t%q0, %q1, %q2"
   [(set_attr "type" "mve_move")
 ])
+(define_expand "mve_veorq_s<mode>"
+  [
+   (set (match_operand:MVE_2 0 "s_register_operand")
+	(xor:MVE_2 (match_operand:MVE_2 1 "s_register_operand")
+		       (match_operand:MVE_2 2 "s_register_operand")))
+  ]
+  "TARGET_HAVE_MVE"
+)
 
 ;;
 ;; [vhaddq_n_u, vhaddq_n_s])
diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index 669c34da4e0..e1263b00b39 100644
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -747,7 +747,7 @@
   [(set_attr "type" "neon_logic<q>")]
 )
 
-(define_insn "xor<mode>3"
+(define_insn "xor<mode>3_neon"
   [(set (match_operand:VDQ 0 "s_register_operand" "=w")
 	(xor:VDQ (match_operand:VDQ 1 "s_register_operand" "w")
 		 (match_operand:VDQ 2 "s_register_operand" "w")))]
diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md
index f111ad80ead..78313ea87bc 100644
--- a/gcc/config/arm/unspecs.md
+++ b/gcc/config/arm/unspecs.md
@@ -608,7 +608,6 @@
   VCMPEQQ_S
   VCMPEQQ_N_S
   VCMPNEQ_N_S
-  VEORQ_S
   VHADDQ_S
   VHADDQ_N_S
   VHSUBQ_S
@@ -653,7 +652,6 @@
   VCMPEQQ_U
   VCMPEQQ_N_U
   VCMPNEQ_N_U
-  VEORQ_U
   VHADDQ_U
   VHADDQ_N_U
   VHSUBQ_U
diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md
index 3e8387c54cb..99ea1cc0b06 100644
--- a/gcc/config/arm/vec-common.md
+++ b/gcc/config/arm/vec-common.md
@@ -185,4 +185,11 @@
 	(ior:VDQ (match_operand:VDQ 1 "s_register_operand" "")
 		 (match_operand:VDQ 2 "neon_logic_op2" "")))]
   "TARGET_NEON || TARGET_HAVE_MVE"
-)
\ No newline at end of file
+)
+
+(define_expand "xor<mode>3"
+  [(set (match_operand:VDQ 0 "s_register_operand" "")
+	(xor:VDQ (match_operand:VDQ 1 "s_register_operand" "")
+		 (match_operand:VDQ 2 "s_register_operand" "")))]
+  "TARGET_NEON || TARGET_HAVE_MVE"
+)
diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-veor.c b/gcc/testsuite/gcc.target/arm/simd/mve-veor.c
new file mode 100644
index 00000000000..7584028a645
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/mve-veor.c
@@ -0,0 +1,96 @@
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O3" } */
+
+#include <stdint.h>
+
+/* 64-bit vectors.  */
+void test_veor_i32x2 (int32_t * __restrict__ dest, int32_t * a, int32_t * b) {
+  int i;
+  for (i=0; i<2; i++) {
+    dest[i] = a[i] ^ b[i];
+  }
+}
+
+void test_veor_u32x2 (uint32_t * __restrict__ dest, uint32_t * a, uint32_t * b) {
+  int i;
+  for (i=0; i<2; i++) {
+    dest[i] = a[i] ^ b[i];
+  }
+}
+
+void test_veor_i16x4 (int16_t * __restrict__ dest, int16_t * a, int16_t * b) {
+  int i;
+  for (i=0; i<4; i++) {
+    dest[i] = a[i] ^ b[i];
+  }
+}
+
+void test_veor_u16x4 (uint16_t * __restrict__ dest, uint16_t * a, uint16_t * b) {
+  int i;
+  for (i=0; i<4; i++) {
+    dest[i] = a[i] ^ b[i];
+  }
+}
+
+void test_veor_i8x8 (int8_t * __restrict__ dest, int8_t * a, int8_t * b) {
+  int i;
+  for (i=0; i<8; i++) {
+    dest[i] = a[i] ^ b[i];
+  }
+}
+
+void test_veor_u8x8 (uint8_t * __restrict__ dest, uint8_t * a, uint8_t * b) {
+  int i;
+  for (i=0; i<8; i++) {
+    dest[i] = a[i] ^ b[i];
+  }
+}
+
+/* 128-bit vectors.  */
+void test_veor_i32x4 (int32_t * __restrict__ dest, int32_t * a, int32_t * b) {
+  int i;
+  for (i=0; i<4; i++) {
+    dest[i] = a[i] ^ b[i];
+  }
+}
+
+void test_veor_u32x4 (uint32_t * __restrict__ dest, uint32_t * a, uint32_t * b) {
+  int i;
+  for (i=0; i<4; i++) {
+    dest[i] = a[i] ^ b[i];
+  }
+}
+
+void test_veor_i16x8 (int16_t * __restrict__ dest, int16_t * a, int16_t * b) {
+  int i;
+  for (i=0; i<8; i++) {
+    dest[i] = a[i] ^ b[i];
+  }
+}
+
+void test_veor_u16x8 (uint16_t * __restrict__ dest, uint16_t * a, uint16_t * b) {
+  int i;
+  for (i=0; i<8; i++) {
+    dest[i] = a[i] ^ b[i];
+  }
+}
+
+void test_veor_i8x16 (int8_t * __restrict__ dest, int8_t * a, int8_t * b) {
+  int i;
+  for (i=0; i<16; i++) {
+    dest[i] = a[i] ^ b[i];
+  }
+}
+
+void test_veor_u8x16 (uint8_t * __restrict__ dest, uint8_t * a, uint8_t * b) {
+  int i;
+  for (i=0; i<16; i++) {
+    dest[i] = a[i] ^ b[i];
+  }
+}
+
+/* MVE has only 128-bit vectors, so we can vectorize only half of the
+   functions above.  */
+/* { dg-final { scan-assembler-times {veor\tq[0-9]+, q[0-9]+, q[0-9]+} 6 } } */


^ permalink raw reply	[flat|nested] 6+ messages in thread
* [gcc(refs/users/clyon/heads/mve-autovec)] arm: Auto-vectorization for MVE: veor
@ 2020-11-20 15:04 Christophe Lyon
  0 siblings, 0 replies; 6+ messages in thread
From: Christophe Lyon @ 2020-11-20 15:04 UTC (permalink / raw)
  To: gcc-cvs

https://gcc.gnu.org/g:4d22d5ea7a9a9907b8169559d0cb3306f25277d6

commit 4d22d5ea7a9a9907b8169559d0cb3306f25277d6
Author: Christophe Lyon <christophe.lyon@linaro.org>
Date:   Fri Nov 13 13:05:43 2020 +0000

    arm: Auto-vectorization for MVE: veor
    
    This patch enables MVE veor instructions for auto-vectorization.  MVE
    veor insns in mve.md are modified to use xor instead of unspec
    expression to support xor<mode>3.  The xor<mode>3 expander is added to
    vec-common.md
    
    2020-11-12  Christophe Lyon  <christophe.lyon@linaro.org>
    
            gcc/
            * config/arm/mve.md (mve_veorq_s<mode>): New entry for veor
            instruction using expression xor.
            (mve_veorq_u<mode>): Likewise.
            * config/arm/neon.md (xor<mode>3): Renamed into xor<mode>3_neon.
            * config/arm/vec-common.md (xor<mode>3): New expander.
    
            gcc/testsuite/
            * gcc.target/arm/simd/mve-veor.c: Add tests for veor.

Diff:
---
 gcc/config/arm/mve.md                        | 19 ++++--
 gcc/config/arm/neon.md                       |  2 +-
 gcc/config/arm/vec-common.md                 |  9 ++-
 gcc/testsuite/gcc.target/arm/simd/mve-veor.c | 96 ++++++++++++++++++++++++++++
 4 files changed, 119 insertions(+), 7 deletions(-)

diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 4127236c4f7..4c6cc093822 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -1203,15 +1203,24 @@
 ;;
 ;; [veorq_u, veorq_s])
 ;;
-(define_insn "mve_veorq_<supf><mode>"
+(define_insn "mve_veorq_s<mode>"
   [
    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
-	(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
-		       (match_operand:MVE_2 2 "s_register_operand" "w")]
-	 VEORQ))
+	(xor:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w")
+		       (match_operand:MVE_2 2 "s_register_operand" "w")))
   ]
   "TARGET_HAVE_MVE"
-  "veor %q0, %q1, %q2"
+  "veor\t%q0, %q1, %q2"
+  [(set_attr "type" "mve_move")
+])
+(define_insn "mve_veorq_u<mode>"
+  [
+   (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+	(xor:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w")
+		       (match_operand:MVE_2 2 "s_register_operand" "w")))
+  ]
+  "TARGET_HAVE_MVE"
+  "veor\t%q0, %q1, %q2"
   [(set_attr "type" "mve_move")
 ])
 
diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index 669c34da4e0..e1263b00b39 100644
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -747,7 +747,7 @@
   [(set_attr "type" "neon_logic<q>")]
 )
 
-(define_insn "xor<mode>3"
+(define_insn "xor<mode>3_neon"
   [(set (match_operand:VDQ 0 "s_register_operand" "=w")
 	(xor:VDQ (match_operand:VDQ 1 "s_register_operand" "w")
 		 (match_operand:VDQ 2 "s_register_operand" "w")))]
diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md
index 3e8387c54cb..99ea1cc0b06 100644
--- a/gcc/config/arm/vec-common.md
+++ b/gcc/config/arm/vec-common.md
@@ -185,4 +185,11 @@
 	(ior:VDQ (match_operand:VDQ 1 "s_register_operand" "")
 		 (match_operand:VDQ 2 "neon_logic_op2" "")))]
   "TARGET_NEON || TARGET_HAVE_MVE"
-)
\ No newline at end of file
+)
+
+(define_expand "xor<mode>3"
+  [(set (match_operand:VDQ 0 "s_register_operand" "")
+	(xor:VDQ (match_operand:VDQ 1 "s_register_operand" "")
+		 (match_operand:VDQ 2 "s_register_operand" "")))]
+  "TARGET_NEON || TARGET_HAVE_MVE"
+)
diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-veor.c b/gcc/testsuite/gcc.target/arm/simd/mve-veor.c
new file mode 100644
index 00000000000..7584028a645
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/mve-veor.c
@@ -0,0 +1,96 @@
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O3" } */
+
+#include <stdint.h>
+
+/* 64-bit vectors.  */
+void test_veor_i32x2 (int32_t * __restrict__ dest, int32_t * a, int32_t * b) {
+  int i;
+  for (i=0; i<2; i++) {
+    dest[i] = a[i] ^ b[i];
+  }
+}
+
+void test_veor_u32x2 (uint32_t * __restrict__ dest, uint32_t * a, uint32_t * b) {
+  int i;
+  for (i=0; i<2; i++) {
+    dest[i] = a[i] ^ b[i];
+  }
+}
+
+void test_veor_i16x4 (int16_t * __restrict__ dest, int16_t * a, int16_t * b) {
+  int i;
+  for (i=0; i<4; i++) {
+    dest[i] = a[i] ^ b[i];
+  }
+}
+
+void test_veor_u16x4 (uint16_t * __restrict__ dest, uint16_t * a, uint16_t * b) {
+  int i;
+  for (i=0; i<4; i++) {
+    dest[i] = a[i] ^ b[i];
+  }
+}
+
+void test_veor_i8x8 (int8_t * __restrict__ dest, int8_t * a, int8_t * b) {
+  int i;
+  for (i=0; i<8; i++) {
+    dest[i] = a[i] ^ b[i];
+  }
+}
+
+void test_veor_u8x8 (uint8_t * __restrict__ dest, uint8_t * a, uint8_t * b) {
+  int i;
+  for (i=0; i<8; i++) {
+    dest[i] = a[i] ^ b[i];
+  }
+}
+
+/* 128-bit vectors.  */
+void test_veor_i32x4 (int32_t * __restrict__ dest, int32_t * a, int32_t * b) {
+  int i;
+  for (i=0; i<4; i++) {
+    dest[i] = a[i] ^ b[i];
+  }
+}
+
+void test_veor_u32x4 (uint32_t * __restrict__ dest, uint32_t * a, uint32_t * b) {
+  int i;
+  for (i=0; i<4; i++) {
+    dest[i] = a[i] ^ b[i];
+  }
+}
+
+void test_veor_i16x8 (int16_t * __restrict__ dest, int16_t * a, int16_t * b) {
+  int i;
+  for (i=0; i<8; i++) {
+    dest[i] = a[i] ^ b[i];
+  }
+}
+
+void test_veor_u16x8 (uint16_t * __restrict__ dest, uint16_t * a, uint16_t * b) {
+  int i;
+  for (i=0; i<8; i++) {
+    dest[i] = a[i] ^ b[i];
+  }
+}
+
+void test_veor_i8x16 (int8_t * __restrict__ dest, int8_t * a, int8_t * b) {
+  int i;
+  for (i=0; i<16; i++) {
+    dest[i] = a[i] ^ b[i];
+  }
+}
+
+void test_veor_u8x16 (uint8_t * __restrict__ dest, uint8_t * a, uint8_t * b) {
+  int i;
+  for (i=0; i<16; i++) {
+    dest[i] = a[i] ^ b[i];
+  }
+}
+
+/* MVE has only 128-bit vectors, so we can vectorize only half of the
+   functions above.  */
+/* { dg-final { scan-assembler-times {veor\tq[0-9]+, q[0-9]+, q[0-9]+} 6 } } */


^ permalink raw reply	[flat|nested] 6+ messages in thread
* [gcc(refs/users/clyon/heads/mve-autovec)] arm: Auto-vectorization for MVE: veor
@ 2020-11-15 23:44 Christophe Lyon
  0 siblings, 0 replies; 6+ messages in thread
From: Christophe Lyon @ 2020-11-15 23:44 UTC (permalink / raw)
  To: gcc-cvs

https://gcc.gnu.org/g:2de478260d1342f49b773dc553fa372a47d144ae

commit 2de478260d1342f49b773dc553fa372a47d144ae
Author: Christophe Lyon <christophe.lyon@linaro.org>
Date:   Fri Nov 13 13:05:43 2020 +0000

    arm: Auto-vectorization for MVE: veor
    
    This patch enables MVE veor instructions for auto-vectorization.  MVE
    veor insns in mve.md are modified to use xor instead of unspec
    expression to support xor<mode>3.  The xor<mode>3 expander is added to
    vec-common.md
    
    2020-11-12  Christophe Lyon  <christophe.lyon@linaro.org>
    
            gcc/
            * config/arm/mve.md (mve_veorq_s<mode>): New entry for veor
            instruction using expression xor.
            (mve_veorq_u<mode>): Likewise.
            * config/arm/neon.md (xor<mode>3): Renamed into xor<mode>3_neon.
            * config/arm/vec-common.md (xor<mode>3): New expander.
    
            gcc/testsuite/
            * gcc.target/arm/simd/mve-veor.c: Add tests for veor.

Diff:
---
 gcc/config/arm/mve.md                        | 19 ++++++++---
 gcc/config/arm/neon.md                       |  2 +-
 gcc/config/arm/vec-common.md                 |  9 ++++-
 gcc/testsuite/gcc.target/arm/simd/mve-veor.c | 50 ++++++++++++++++++++++++++++
 4 files changed, 73 insertions(+), 7 deletions(-)

diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 4127236c4f7..4c6cc093822 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -1203,15 +1203,24 @@
 ;;
 ;; [veorq_u, veorq_s])
 ;;
-(define_insn "mve_veorq_<supf><mode>"
+(define_insn "mve_veorq_s<mode>"
   [
    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
-	(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
-		       (match_operand:MVE_2 2 "s_register_operand" "w")]
-	 VEORQ))
+	(xor:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w")
+		       (match_operand:MVE_2 2 "s_register_operand" "w")))
   ]
   "TARGET_HAVE_MVE"
-  "veor %q0, %q1, %q2"
+  "veor\t%q0, %q1, %q2"
+  [(set_attr "type" "mve_move")
+])
+(define_insn "mve_veorq_u<mode>"
+  [
+   (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+	(xor:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w")
+		       (match_operand:MVE_2 2 "s_register_operand" "w")))
+  ]
+  "TARGET_HAVE_MVE"
+  "veor\t%q0, %q1, %q2"
   [(set_attr "type" "mve_move")
 ])
 
diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index 669c34da4e0..e1263b00b39 100644
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -747,7 +747,7 @@
   [(set_attr "type" "neon_logic<q>")]
 )
 
-(define_insn "xor<mode>3"
+(define_insn "xor<mode>3_neon"
   [(set (match_operand:VDQ 0 "s_register_operand" "=w")
 	(xor:VDQ (match_operand:VDQ 1 "s_register_operand" "w")
 		 (match_operand:VDQ 2 "s_register_operand" "w")))]
diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md
index 3e8387c54cb..99ea1cc0b06 100644
--- a/gcc/config/arm/vec-common.md
+++ b/gcc/config/arm/vec-common.md
@@ -185,4 +185,11 @@
 	(ior:VDQ (match_operand:VDQ 1 "s_register_operand" "")
 		 (match_operand:VDQ 2 "neon_logic_op2" "")))]
   "TARGET_NEON || TARGET_HAVE_MVE"
-)
\ No newline at end of file
+)
+
+(define_expand "xor<mode>3"
+  [(set (match_operand:VDQ 0 "s_register_operand" "")
+	(xor:VDQ (match_operand:VDQ 1 "s_register_operand" "")
+		 (match_operand:VDQ 2 "s_register_operand" "")))]
+  "TARGET_NEON || TARGET_HAVE_MVE"
+)
diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-veor.c b/gcc/testsuite/gcc.target/arm/simd/mve-veor.c
new file mode 100644
index 00000000000..5acd23c26d8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/mve-veor.c
@@ -0,0 +1,50 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O3" } */
+
+#include <stdint.h>
+
+void test_veor_i32 (int32_t * __restrict__ dest, int32_t * a, int32_t * b) {
+  int i;
+  for (i=0; i<4; i++) {
+    dest[i] = a[i] ^ b[i];
+  }
+}
+
+void test_veor_i32_u (uint32_t * __restrict__ dest, uint32_t * a, uint32_t * b) {
+  int i;
+  for (i=0; i<4; i++) {
+    dest[i] = a[i] ^ b[i];
+  }
+}
+
+void test_veor_i16 (int16_t * __restrict__ dest, int16_t * a, int16_t * b) {
+  int i;
+  for (i=0; i<8; i++) {
+    dest[i] = a[i] ^ b[i];
+  }
+}
+
+void test_veor_i16_u (uint16_t * __restrict__ dest, uint16_t * a, uint16_t * b) {
+  int i;
+  for (i=0; i<8; i++) {
+    dest[i] = a[i] ^ b[i];
+  }
+}
+
+void test_veor_i8 (int8_t * __restrict__ dest, int8_t * a, int8_t * b) {
+  int i;
+  for (i=0; i<16; i++) {
+    dest[i] = a[i] ^ b[i];
+  }
+}
+
+void test_veor_i8_u (uint8_t * __restrict__ dest, uint8_t * a, uint8_t * b) {
+  int i;
+  for (i=0; i<16; i++) {
+    dest[i] = a[i] ^ b[i];
+  }
+}
+
+/* { dg-final { scan-assembler-times {veor\tq[0-9]+, q[0-9]+, q[0-9]+} 6 } } */


^ permalink raw reply	[flat|nested] 6+ messages in thread
* [gcc(refs/users/clyon/heads/mve-autovec)] arm: Auto-vectorization for MVE: veor
@ 2020-11-13 13:08 Christophe Lyon
  0 siblings, 0 replies; 6+ messages in thread
From: Christophe Lyon @ 2020-11-13 13:08 UTC (permalink / raw)
  To: gcc-cvs

https://gcc.gnu.org/g:ac173689e62cbf6858bc916eddd577f69a55b5b7

commit ac173689e62cbf6858bc916eddd577f69a55b5b7
Author: Christophe Lyon <christophe.lyon@linaro.org>
Date:   Fri Nov 13 13:05:43 2020 +0000

    arm: Auto-vectorization for MVE: veor
    
    This patch enables MVE veor instructions for auto-vectorization.  MVE
    veor insns in mve.md are modified to use xor instead of unspec
    expression to support xor<mode>3.  The xor<mode>3 expander is added to
    vec-common.md
    
    2020-11-12  Christophe Lyon  <christophe.lyon@linaro.org>
    
            gcc/
            * config/arm/mve.md (mve_veorq_s<mode>): New entry for veor
            instruction using expression xor.
            (mve_veorq_u<mode>): Likewise.
            * config/arm/neon.md (xor<mode>3): Renamed into xor<mode>3_neon.
            * config/arm/vec-common.md (xor<mode>3): New expander.
    
            gcc/testsuite/
            * gcc.target/arm/simd/mve-vlogical_1.c: Add tests for veor.

Diff:
---
 gcc/config/arm/mve.md                            | 19 +++++++---
 gcc/config/arm/neon.md                           |  2 +-
 gcc/config/arm/vec-common.md                     |  9 ++++-
 gcc/testsuite/gcc.target/arm/simd/mve-vlogical.c | 44 ++++++++++++++++++++++++
 4 files changed, 67 insertions(+), 7 deletions(-)

diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 4127236c4f7..4c6cc093822 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -1203,15 +1203,24 @@
 ;;
 ;; [veorq_u, veorq_s])
 ;;
-(define_insn "mve_veorq_<supf><mode>"
+(define_insn "mve_veorq_s<mode>"
   [
    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
-	(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
-		       (match_operand:MVE_2 2 "s_register_operand" "w")]
-	 VEORQ))
+	(xor:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w")
+		       (match_operand:MVE_2 2 "s_register_operand" "w")))
   ]
   "TARGET_HAVE_MVE"
-  "veor %q0, %q1, %q2"
+  "veor\t%q0, %q1, %q2"
+  [(set_attr "type" "mve_move")
+])
+(define_insn "mve_veorq_u<mode>"
+  [
+   (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+	(xor:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w")
+		       (match_operand:MVE_2 2 "s_register_operand" "w")))
+  ]
+  "TARGET_HAVE_MVE"
+  "veor\t%q0, %q1, %q2"
   [(set_attr "type" "mve_move")
 ])
 
diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index 669c34da4e0..e1263b00b39 100644
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -747,7 +747,7 @@
   [(set_attr "type" "neon_logic<q>")]
 )
 
-(define_insn "xor<mode>3"
+(define_insn "xor<mode>3_neon"
   [(set (match_operand:VDQ 0 "s_register_operand" "=w")
 	(xor:VDQ (match_operand:VDQ 1 "s_register_operand" "w")
 		 (match_operand:VDQ 2 "s_register_operand" "w")))]
diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md
index 3e8387c54cb..99ea1cc0b06 100644
--- a/gcc/config/arm/vec-common.md
+++ b/gcc/config/arm/vec-common.md
@@ -185,4 +185,11 @@
 	(ior:VDQ (match_operand:VDQ 1 "s_register_operand" "")
 		 (match_operand:VDQ 2 "neon_logic_op2" "")))]
   "TARGET_NEON || TARGET_HAVE_MVE"
-)
\ No newline at end of file
+)
+
+(define_expand "xor<mode>3"
+  [(set (match_operand:VDQ 0 "s_register_operand" "")
+	(xor:VDQ (match_operand:VDQ 1 "s_register_operand" "")
+		 (match_operand:VDQ 2 "s_register_operand" "")))]
+  "TARGET_NEON || TARGET_HAVE_MVE"
+)
diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-vlogical.c b/gcc/testsuite/gcc.target/arm/simd/mve-vlogical.c
index 903604fdd12..4e9ed6e1c53 100644
--- a/gcc/testsuite/gcc.target/arm/simd/mve-vlogical.c
+++ b/gcc/testsuite/gcc.target/arm/simd/mve-vlogical.c
@@ -92,3 +92,47 @@ void test_vorr_i8_u (uint8_t * __restrict__ dest, uint8_t * a, uint8_t * b) {
 }
 
 /* { dg-final { scan-assembler-times {vorr\tq[0-9]+, q[0-9]+, q[0-9]+} 6 } } */
+
+void test_veor_i32 (int32_t * __restrict__ dest, int32_t * a, int32_t * b) {
+  int i;
+  for (i=0; i<4; i++) {
+    dest[i] = a[i] ^ b[i];
+  }
+}
+
+void test_veor_i32_u (uint32_t * __restrict__ dest, uint32_t * a, uint32_t * b) {
+  int i;
+  for (i=0; i<4; i++) {
+    dest[i] = a[i] ^ b[i];
+  }
+}
+
+void test_veor_i16 (int16_t * __restrict__ dest, int16_t * a, int16_t * b) {
+  int i;
+  for (i=0; i<8; i++) {
+    dest[i] = a[i] ^ b[i];
+  }
+}
+
+void test_veor_i16_u (uint16_t * __restrict__ dest, uint16_t * a, uint16_t * b) {
+  int i;
+  for (i=0; i<8; i++) {
+    dest[i] = a[i] ^ b[i];
+  }
+}
+
+void test_veor_i8 (int8_t * __restrict__ dest, int8_t * a, int8_t * b) {
+  int i;
+  for (i=0; i<16; i++) {
+    dest[i] = a[i] ^ b[i];
+  }
+}
+
+void test_veor_i8_u (uint8_t * __restrict__ dest, uint8_t * a, uint8_t * b) {
+  int i;
+  for (i=0; i<16; i++) {
+    dest[i] = a[i] ^ b[i];
+  }
+}
+
+/* { dg-final { scan-assembler-times {veor\tq[0-9]+, q[0-9]+, q[0-9]+} 6 } } */


^ permalink raw reply	[flat|nested] 6+ messages in thread
end of thread, other threads:[~2020-12-16 13:48 UTC | newest]

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