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* [gcc(refs/vendors/ventana/heads/minor-improvements-for-gcc11)] RISC-V: branch-(not)equals-zero compares against $zero
@ 2020-12-17 17:10 Philipp Tomsich
0 siblings, 0 replies; 3+ messages in thread
From: Philipp Tomsich @ 2020-12-17 17:10 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:01acb29fa0a62492d13a3ece66abbb985f958997
commit 01acb29fa0a62492d13a3ece66abbb985f958997
Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date: Sun Aug 30 21:02:36 2020 +0200
RISC-V: branch-(not)equals-zero compares against $zero
If we are testing a register or a paradoxical subreg (i.e. anything that is not
a partial subreg) for equality/non-equality with zero, we can generate a branch
that compares against $zero. This will work for QI, HI, SI and DImode, so we
enable this for ANYI.
2020-08-30 gcc/ChangeLog:
* config/riscv/riscv.md (*branch<mode>_equals_zero): Added pattern.
Diff:
---
gcc/config/riscv/riscv.md | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index f5cca5df102..d28971c5d0e 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -1856,6 +1856,19 @@
;; Conditional branches
+(define_insn "*branch<mode>_equals_zero"
+ [(set (pc)
+ (if_then_else
+ (match_operator 1 "equality_operator"
+ [(match_operand:ANYI 2 "register_operand" "r")
+ (const_int 0)])
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+ "!partial_subreg_p(operands[2])"
+ "b%C1\t%2,zero,%0"
+ [(set_attr "type" "branch")
+ (set_attr "mode" "none")])
+
(define_insn "*branch<mode>"
[(set (pc)
(if_then_else
^ permalink raw reply [flat|nested] 3+ messages in thread
* [gcc(refs/vendors/ventana/heads/minor-improvements-for-gcc11)] RISC-V: branch-(not)equals-zero compares against $zero
@ 2021-01-04 19:21 Philipp Tomsich
0 siblings, 0 replies; 3+ messages in thread
From: Philipp Tomsich @ 2021-01-04 19:21 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:a3bc189dc9add2f3958c294362844bb79fcafc6f
commit a3bc189dc9add2f3958c294362844bb79fcafc6f
Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date: Sun Aug 30 21:02:36 2020 +0200
RISC-V: branch-(not)equals-zero compares against $zero
If we are testing a register or a paradoxical subreg (i.e. anything that is not
a partial subreg) for equality/non-equality with zero, we can generate a branch
that compares against $zero. This will work for QI, HI, SI and DImode, so we
enable this for ANYI.
2020-08-30 gcc/ChangeLog:
* config/riscv/riscv.md (*branch<mode>_equals_zero): Added pattern.
Diff:
---
gcc/config/riscv/riscv.md | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index e6dfc7237cf..4a6037b9646 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -1856,6 +1856,19 @@
;; Conditional branches
+(define_insn "*branch<mode>_equals_zero"
+ [(set (pc)
+ (if_then_else
+ (match_operator 1 "equality_operator"
+ [(match_operand:ANYI 2 "register_operand" "r")
+ (const_int 0)])
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+ "!partial_subreg_p(operands[2])"
+ "b%C1\t%2,zero,%0"
+ [(set_attr "type" "branch")
+ (set_attr "mode" "none")])
+
(define_insn "*branch<mode>"
[(set (pc)
(if_then_else
^ permalink raw reply [flat|nested] 3+ messages in thread
* [gcc(refs/vendors/ventana/heads/minor-improvements-for-gcc11)] RISC-V: branch-(not)equals-zero compares against $zero
@ 2021-01-04 17:01 Philipp Tomsich
0 siblings, 0 replies; 3+ messages in thread
From: Philipp Tomsich @ 2021-01-04 17:01 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:9623f66ee0f2f087ddfcac19b4c91717cb4cfb88
commit 9623f66ee0f2f087ddfcac19b4c91717cb4cfb88
Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date: Sun Aug 30 21:02:36 2020 +0200
RISC-V: branch-(not)equals-zero compares against $zero
If we are testing a register or a paradoxical subreg (i.e. anything that is not
a partial subreg) for equality/non-equality with zero, we can generate a branch
that compares against $zero. This will work for QI, HI, SI and DImode, so we
enable this for ANYI.
2020-08-30 gcc/ChangeLog:
* config/riscv/riscv.md (*branch<mode>_equals_zero): Added pattern.
Diff:
---
gcc/config/riscv/riscv.md | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index e6dfc7237cf..040cc2514fd 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -1856,6 +1856,19 @@
;; Conditional branches
+(define_insn "*branch<mode>_equals_zero"
+ [(set (pc)
+ (if_then_else
+ (match_operator 1 "equality_operator"
+ [(match_operand:ANYI 2 "register_operand" "r")
+ (const_int 0)])
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+ "!partial_subreg_p(operands[2])"
+ "b%C1\t%2,zero,%0"
+ [(set_attr "type" "branch")
+ (set_attr "mode" "none")])
+
(define_insn "*branch<mode>"
[(set (pc)
(if_then_else
^ permalink raw reply [flat|nested] 3+ messages in thread
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2021-01-04 19:21 Philipp Tomsich
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