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* [gcc(refs/users/wschmidt/heads/builtins4)] rs6000: More bug fixes
@ 2020-12-17 22:25 William Schmidt
0 siblings, 0 replies; 29+ messages in thread
From: William Schmidt @ 2020-12-17 22:25 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:9befce7ac191a33c2280d0fa99b24e83d34cbd79
commit 9befce7ac191a33c2280d0fa99b24e83d34cbd79
Author: Bill Schmidt <wschmidt@linux.ibm.com>
Date: Thu Dec 17 16:25:22 2020 -0600
rs6000: More bug fixes
2020-12-17 Bill Schmidt <wschmidt@linux.ibm.com>
* config/rs6000/rs6000-builtin-new.def (LVEBX): Fix return type.
(LVEHX): Likewise.
(LVEWX): Likeiwse.
* config/rs6000/rs6000-gen-builtins.c (construct_fntype_id): Don't
use "ci" for pointers.
* config/rs6000/rs6000-overload.def (VEC_CMPEQ): Use Altivec
forms, not VSX forms, for now.
(VEC_CMPEQ_P): Likewise.
(VEC_CMPGE): Likewise.
(VEC_CMPGE_P): Likewise.
(VEC_CMPGT): Likewise.
(VEC_CMPGT_P): Likewise.
(VEC_NMSUB): Likewise.
(VEC_RE): Likewise.
Diff:
---
gcc/config/rs6000/rs6000-builtin-new.def | 6 +++---
gcc/config/rs6000/rs6000-gen-builtins.c | 5 ++++-
gcc/config/rs6000/rs6000-overload.def | 27 +++++++++++++++++++--------
3 files changed, 26 insertions(+), 12 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-builtin-new.def b/gcc/config/rs6000/rs6000-builtin-new.def
index 3ca7ccab705..8b54b17e1ce 100644
--- a/gcc/config/rs6000/rs6000-builtin-new.def
+++ b/gcc/config/rs6000/rs6000-builtin-new.def
@@ -306,13 +306,13 @@
fpmath vf __builtin_altivec_float_sisf (vsi);
FLOAT_V4SI_V4SF floatv4siv4sf2 {}
- pure vop __builtin_altivec_lvebx (signed long long, const void *);
+ pure vsc __builtin_altivec_lvebx (signed long long, const void *);
LVEBX altivec_lvebx {ldvec}
- pure vop __builtin_altivec_lvehx (signed long long, const void *);
+ pure vss __builtin_altivec_lvehx (signed long long, const void *);
LVEHX altivec_lvehx {ldvec}
- pure vop __builtin_altivec_lvewx (signed long long, const void *);
+ pure vsi __builtin_altivec_lvewx (signed long long, const void *);
LVEWX altivec_lvewx {ldvec}
pure vuc __builtin_altivec_lvsl (signed long long, const void *);
diff --git a/gcc/config/rs6000/rs6000-gen-builtins.c b/gcc/config/rs6000/rs6000-gen-builtins.c
index 57095dde58a..a4495e0c443 100644
--- a/gcc/config/rs6000/rs6000-gen-builtins.c
+++ b/gcc/config/rs6000/rs6000-gen-builtins.c
@@ -930,6 +930,7 @@ match_type (typeinfo *typedata, int voidok)
[const] [[signed|unsigned] <basetype> | <vectype>] [*]
+ #### Lie below ####
where "const" applies only to a <basetype> of "int". Legal values
of <basetype> are (for now):
@@ -1577,7 +1578,9 @@ construct_fntype_id (prototype *protoptr)
{
assert (argptr);
buf[bufi++] = '_';
- if (argptr->info.isconst && argptr->info.base == BT_INT)
+ if (argptr->info.isconst
+ && argptr->info.base == BT_INT
+ && !argptr->info.ispointer)
{
buf[bufi++] = 'c';
buf[bufi++] = 'i';
diff --git a/gcc/config/rs6000/rs6000-overload.def b/gcc/config/rs6000/rs6000-overload.def
index 2109c6ccb56..981e2fe944b 100644
--- a/gcc/config/rs6000/rs6000-overload.def
+++ b/gcc/config/rs6000/rs6000-overload.def
@@ -456,6 +456,7 @@
VCMPBFP
[VEC_CMPEQ, vec_cmpeq, __builtin_vec_cmpeq]
+; #### XVCMPEQSP{TARGET_VSX};VCMPEQFP
vbc __builtin_vec_cmpeq (vsc, vsc);
VCMPEQUB VCMPEQUB_VSC
vbc __builtin_vec_cmpeq (vuc, vuc);
@@ -481,12 +482,13 @@
vbll __builtin_vec_cmpeq (vbll, vbll);
VCMPEQUD VCMPEQUD_VBLL
vbi __builtin_vec_cmpeq (vf, vf);
- XVCMPEQSP
+ VCMPEQFP
vbll __builtin_vec_cmpeq (vd, vd);
XVCMPEQDP
; We skip generating a #define because of the C-versus-C++ complexity
; in altivec.h. Look there for the template-y details.
+; #### XVCMPEQSP_P{TARGET_VSX};VCMPEQFP_P
[VEC_CMPEQ_P, SKIP, __builtin_vec_vcmpeq_p]
signed int __builtin_vec_vcmpeq_p (signed int, vuc, vuc);
VCMPEQUB_P VCMPEQUB_PU
@@ -515,7 +517,7 @@
signed int __builtin_vec_vcmpeq_p (signed int, vbll, vbll);
VCMPEQUD_P VCMPEQUD_PB
signed int __builtin_vec_vcmpeq_p (signed int, vf, vf);
- XVCMPEQSP_P
+ VCMPEQFP_P
signed int __builtin_vec_vcmpeq_p (signed int, vd, vd);
XVCMPEQDP_P
@@ -523,6 +525,7 @@
signed int __builtin_byte_in_set (unsigned char, unsigned long long);
CMPEQB
+; #### XVCMPGESP{TARGET_VSX};VCMPGEFP
[VEC_CMPGE, vec_cmpge, __builtin_vec_cmpge]
vbc __builtin_vec_cmpge (vsc, vsc);
CMPGE_16QI CMPGE_16QI_VSC
@@ -541,7 +544,7 @@
vbll __builtin_vec_cmpge (vull, vull);
CMPGE_2DI CMPGE_2DI_VULL
vbi __builtin_vec_cmpge (vf, vf);
- XVCMPGESP
+ VCMPGEFP
vbll __builtin_vec_cmpge (vd, vd);
XVCMPGEDP
@@ -549,6 +552,7 @@
; in altivec.h. Look there for the template-y details.
; See altivec_build_resolved_builtin for how we deal with VEC_CMPGE_P.
; It's quite strange and horrible!
+; #### XVCMPGESP_P{TARGET_VSX};VCMPGEFP_P
[VEC_CMPGE_P, SKIP, __builtin_vec_vcmpge_p]
signed int __builtin_vec_vcmpge_p (signed int, vuc, vuc);
VCMPGTUB_P VCMPGTUB_PR
@@ -567,10 +571,11 @@
signed int __builtin_vec_vcmpge_p (signed int, vsll, vsll);
VCMPGTSD_P VCMPGTSD_PR
signed int __builtin_vec_vcmpge_p (signed int, vf, vf);
- XVCMPGESP_P
+ VCMPGEFP_P
signed int __builtin_vec_vcmpge_p (signed int, vd, vd);
XVCMPGEDP_P
+; #### XVCMPGTSP{TARGET_VSX};VCMPGTFP
[VEC_CMPGT, vec_cmpgt, __builtin_vec_cmpgt]
vbc __builtin_vec_cmpgt (vsc, vsc);
VCMPGTSB
@@ -589,12 +594,13 @@
vbll __builtin_vec_cmpgt (vull, vull);
VCMPGTUD
vbi __builtin_vec_cmpgt (vf, vf);
- XVCMPGTSP
+ VCMPGTFP
vbll __builtin_vec_cmpgt (vd, vd);
XVCMPGTDP
; We skip generating a #define because of the C-versus-C++ complexity
; in altivec.h. Look there for the template-y details.
+; #### XVCMPGTSP_P{TARGET_VSX};VCMPGTFP_P
[VEC_CMPGT_P, SKIP, __builtin_vec_vcmpgt_p]
signed int __builtin_vec_vcmpgt_p (signed int, vuc, vuc);
VCMPGTUB_P
@@ -613,7 +619,7 @@
signed int __builtin_vec_vcmpgt_p (signed int, vsll, vsll);
VCMPGTSD_P
signed int __builtin_vec_vcmpgt_p (signed int, vf, vf);
- XVCMPGTSP_P
+ VCMPGTFP_P
signed int __builtin_vec_vcmpgt_p (signed int, vd, vd);
XVCMPGTDP_P
@@ -2084,9 +2090,10 @@
vd __builtin_vec_nmadd (vd, vd, vd);
XVNMADDDP
+; #### XVNMSUBDP{TARGET_VSX};VNMSUBFP
[VEC_NMSUB, vec_nmsub, __builtin_vec_nmsub]
vf __builtin_vec_nmsub (vf, vf, vf);
- XVNMSUBSP
+ VNMSUBFP
vd __builtin_vec_nmsub (vd, vd, vd);
XVNMSUBDP
@@ -2354,9 +2361,13 @@
vsi __builtin_vec_promote (vsi);
ABS_V4SI PROMOTE_FAKERY
+; Opportunity for improvement: We can use XVRESP instead of VREFP for
+; TARGET_VSX. We would need conditional dispatch to allow two possibilities.
+; Some syntax like "XVRESP{TARGET_VSX};VREFP".
+; TODO. ####
[VEC_RE, vec_re, __builtin_vec_re]
vf __builtin_vec_re (vf);
- XVRESP
+ VREFP
vd __builtin_vec_re (vd);
XVREDP
^ permalink raw reply [flat|nested] 29+ messages in thread
* [gcc(refs/users/wschmidt/heads/builtins4)] rs6000: More bug fixes
@ 2021-02-24 3:59 William Schmidt
0 siblings, 0 replies; 29+ messages in thread
From: William Schmidt @ 2021-02-24 3:59 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:b8d15e6d2f80a758ea331110e70701adfd8b725c
commit b8d15e6d2f80a758ea331110e70701adfd8b725c
Author: Bill Schmidt <wschmidt@linux.ibm.com>
Date: Tue Feb 23 21:59:11 2021 -0600
rs6000: More bug fixes
2021-02-23 Bill Schmidt <wschmidt@linux.ibm.com>
gcc/
* config/rs6000/rs6000-builtin-new.def
(__builtin_vsx_xvcvsxddp_scale): Add constant restriction.
(__builtin_vsx_xvcvuxddp_scale): Likewise.
* config/rs6000/rs6000-call.c (rs6000_expand_new_builtin): Call
rs6000_invalid_new_builtin and expand calls normally.
Diff:
---
gcc/config/rs6000/rs6000-builtin-new.def | 15 +-----
gcc/config/rs6000/rs6000-call.c | 93 +++++++++++++++++++++++++-------
2 files changed, 75 insertions(+), 33 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-builtin-new.def b/gcc/config/rs6000/rs6000-builtin-new.def
index 6a29726ec09..2e6616dd290 100644
--- a/gcc/config/rs6000/rs6000-builtin-new.def
+++ b/gcc/config/rs6000/rs6000-builtin-new.def
@@ -1727,7 +1727,7 @@
const vd __builtin_vsx_xvcvsxddp (vsll);
XVCVSXDDP vsx_floatv2div2df2 {}
- const vd __builtin_vsx_xvcvsxddp_scale (vsll, const int);
+ const vd __builtin_vsx_xvcvsxddp_scale (vsll, const int<5>);
XVCVSXDDP_SCALE vsx_xvcvsxddp_scale {}
const vf __builtin_vsx_xvcvsxdsp (vsll);
@@ -1742,7 +1742,7 @@
const vd __builtin_vsx_xvcvuxddp (vull);
XVCVUXDDP vsx_floatunsv2div2df2 {}
- const vd __builtin_vsx_xvcvuxddp_scale (vull, const int);
+ const vd __builtin_vsx_xvcvuxddp_scale (vull, const int<5>);
XVCVUXDDP_SCALE vsx_xvcvuxddp_scale {}
; Redundant with __builtin_vsx_xvcvuxddp
@@ -3484,17 +3484,6 @@
PEXTD pextd {}
-; TODO: Land-mine alert.
-;
-; The original built-in support has code that assumes the internal
-; copy of an MMA built-in function appears immediately after the
-; external copy in the built-in table. This is fragile. For the
-; new support, we should transition this to do a name lookup in
-; the built-in hash table, but to start with we will honor the
-; positioning of the built-ins in the table. Note that right now
-; there is going to be breakage with __builtin_mma_disassemble_{acc,pair}
-; since they each require a blank builtin to follow them with icode
-; CODE_FOR_nothing.
[mma]
void __builtin_mma_assemble_acc (v512 *, vuc, vuc, vuc, vuc);
ASSEMBLE_ACC nothing {mma}
diff --git a/gcc/config/rs6000/rs6000-call.c b/gcc/config/rs6000/rs6000-call.c
index 18218206e71..25ccbcc26b8 100644
--- a/gcc/config/rs6000/rs6000-call.c
+++ b/gcc/config/rs6000/rs6000-call.c
@@ -15264,82 +15264,135 @@ rs6000_expand_new_builtin (tree exp, rtx target,
case ENB_P5:
if (!TARGET_POPCNTB)
{
- error ("%qs requires at least %qs\n",
- bifaddr->bifname, "-mcpu=power5");
+ rs6000_invalid_new_builtin (fcode);
return expand_call (exp, target, ignore);
}
break;
case ENB_P6:
if (!TARGET_CMPB)
- return const0_rtx;
+ {
+ rs6000_invalid_new_builtin (fcode);
+ return expand_call (exp, target, ignore);
+ }
break;
case ENB_ALTIVEC:
if (!TARGET_ALTIVEC)
- return const0_rtx;
+ {
+ rs6000_invalid_new_builtin (fcode);
+ return expand_call (exp, target, ignore);
+ }
break;
case ENB_CELL:
if (!TARGET_ALTIVEC || rs6000_cpu != PROCESSOR_CELL)
- return const0_rtx;
+ {
+ rs6000_invalid_new_builtin (fcode);
+ return expand_call (exp, target, ignore);
+ }
break;
case ENB_VSX:
if (!TARGET_VSX)
- return const0_rtx;
+ {
+ rs6000_invalid_new_builtin (fcode);
+ return expand_call (exp, target, ignore);
+ }
break;
case ENB_P7:
if (!TARGET_POPCNTD)
- return const0_rtx;
+ {
+ rs6000_invalid_new_builtin (fcode);
+ return expand_call (exp, target, ignore);
+ }
break;
case ENB_P7_64:
if (!TARGET_POPCNTD || !TARGET_POWERPC64)
- return const0_rtx;
+ {
+ rs6000_invalid_new_builtin (fcode);
+ return expand_call (exp, target, ignore);
+ }
break;
case ENB_P8:
if (!TARGET_DIRECT_MOVE)
- return const0_rtx;
+ {
+ rs6000_invalid_new_builtin (fcode);
+ return expand_call (exp, target, ignore);
+ }
break;
case ENB_P8V:
if (!TARGET_P8_VECTOR)
- return const0_rtx;
+ {
+ rs6000_invalid_new_builtin (fcode);
+ return expand_call (exp, target, ignore);
+ }
break;
case ENB_P9:
if (!TARGET_MODULO)
- return const0_rtx;
+ {
+ rs6000_invalid_new_builtin (fcode);
+ return expand_call (exp, target, ignore);
+ }
break;
case ENB_P9_64:
if (!TARGET_MODULO || !TARGET_POWERPC64)
- return const0_rtx;
+ {
+ rs6000_invalid_new_builtin (fcode);
+ return expand_call (exp, target, ignore);
+ }
break;
case ENB_P9V:
if (!TARGET_P9_VECTOR)
- return const0_rtx;
+ {
+ rs6000_invalid_new_builtin (fcode);
+ return expand_call (exp, target, ignore);
+ }
break;
case ENB_IEEE128_HW:
if (!TARGET_FLOAT128_HW)
- return const0_rtx;
+ {
+ rs6000_invalid_new_builtin (fcode);
+ return expand_call (exp, target, ignore);
+ }
break;
case ENB_DFP:
if (!TARGET_DFP)
- return const0_rtx;
+ {
+ rs6000_invalid_new_builtin (fcode);
+ return expand_call (exp, target, ignore);
+ }
break;
case ENB_CRYPTO:
if (!TARGET_CRYPTO)
- return const0_rtx;
+ {
+ rs6000_invalid_new_builtin (fcode);
+ return expand_call (exp, target, ignore);
+ }
break;
case ENB_HTM:
if (!TARGET_HTM)
- return const0_rtx;
+ {
+ rs6000_invalid_new_builtin (fcode);
+ return expand_call (exp, target, ignore);
+ }
break;
case ENB_P10:
if (!TARGET_POWER10)
- return const0_rtx;
+ {
+ rs6000_invalid_new_builtin (fcode);
+ return expand_call (exp, target, ignore);
+ }
break;
case ENB_P10_64:
if (!TARGET_POWER10 || !TARGET_POWERPC64)
- return const0_rtx;
+ {
+ rs6000_invalid_new_builtin (fcode);
+ return expand_call (exp, target, ignore);
+ }
break;
case ENB_MMA:
if (!TARGET_MMA)
- return const0_rtx;
+ {
+ rs6000_invalid_new_builtin (fcode);
+ return expand_call (exp, target, ignore);
+ }
break;
};
^ permalink raw reply [flat|nested] 29+ messages in thread
* [gcc(refs/users/wschmidt/heads/builtins4)] rs6000: More bug fixes
@ 2021-02-22 20:27 William Schmidt
0 siblings, 0 replies; 29+ messages in thread
From: William Schmidt @ 2021-02-22 20:27 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:f201279ba188c30d47c7c7e4b12e0fb831f89f34
commit f201279ba188c30d47c7c7e4b12e0fb831f89f34
Author: Bill Schmidt <wschmidt@linux.ibm.com>
Date: Mon Feb 22 14:20:48 2021 -0600
rs6000: More bug fixes
2021-02-21 Bill Schmidt <wschmidt@linux.ibm.com>
gcc/
* config/rs6000/rs6000-builtin-new.def (SE_LXVRBX): Fill in icode.
(SE_LXVRHX): Likewise.
(SE_LXVRWX): Likewise.
(SE_LXVRDX): Likewise.
(TR_STXVRBX): Likewise.
(TR_STXVRHX): Likewise.
(TR_STXVRWX): Likewise.
(TR_STXVRDX): Likewise.
* config/rs6000/rs6000-call.c (lxvr_expand_builtin): New function.
(stv_expand_builtin): Add support for truncating stores.
(rs6000_expand_new_builtin): Handle bif_is_lxvr.
Diff:
---
gcc/config/rs6000/rs6000-builtin-new.def | 16 +++---
gcc/config/rs6000/rs6000-call.c | 83 +++++++++++++++++++++++++++++++-
2 files changed, 90 insertions(+), 9 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-builtin-new.def b/gcc/config/rs6000/rs6000-builtin-new.def
index 95dfdf306ab..d325e876308 100644
--- a/gcc/config/rs6000/rs6000-builtin-new.def
+++ b/gcc/config/rs6000/rs6000-builtin-new.def
@@ -3083,28 +3083,28 @@
MTVSRWM vec_mtvsr_v4si {}
pure vsq __builtin_altivec_se_lxvrbx (signed long long, const signed char *);
- SE_LXVRBX nothing {lxvr}
+ SE_LXVRBX vsx_lxvrbx {lxvr}
pure vsq __builtin_altivec_se_lxvrhx (signed long long, const signed short *);
- SE_LXVRHX nothing {lxvr}
+ SE_LXVRHX vsx_lxvrhx {lxvr}
pure vsq __builtin_altivec_se_lxvrwx (signed long long, const signed int *);
- SE_LXVRWX nothing {lxvr}
+ SE_LXVRWX vsx_lxvrwx {lxvr}
pure vsq __builtin_altivec_se_lxvrdx (signed long long, const signed long long *);
- SE_LXVRDX nothing {lxvr}
+ SE_LXVRDX vsx_lxvrdx {lxvr}
void __builtin_altivec_tr_stxvrbx (vsq, signed long long, signed char *);
- TR_STXVRBX nothing {stvec}
+ TR_STXVRBX vsx_stxvrbx {stvec}
void __builtin_altivec_tr_stxvrhx (vsq, signed long long, signed int *);
- TR_STXVRHX nothing {stvec}
+ TR_STXVRHX vsx_stxvrhx {stvec}
void __builtin_altivec_tr_stxvrwx (vsq, signed long long, signed short *);
- TR_STXVRWX nothing {stvec}
+ TR_STXVRWX vsx_stxvrwx {stvec}
void __builtin_altivec_tr_stxvrdx (vsq, signed long long, signed long long *);
- TR_STXVRDX nothing {stvec}
+ TR_STXVRDX vsx_stxvrdx {stvec}
const vull __builtin_altivec_vcfuged (vull, vull);
VCFUGED vcfuged {}
diff --git a/gcc/config/rs6000/rs6000-call.c b/gcc/config/rs6000/rs6000-call.c
index 8907bc96db5..b3265dd2d81 100644
--- a/gcc/config/rs6000/rs6000-call.c
+++ b/gcc/config/rs6000/rs6000-call.c
@@ -13557,11 +13557,70 @@ ldv_expand_builtin (rtx target, insn_code icode, rtx *op, machine_mode tmode)
return target;
}
+static rtx
+lxvr_expand_builtin (rtx target, insn_code icode, rtx *op, machine_mode tmode,
+ machine_mode smode)
+{
+ rtx pat, addr;
+ op[1] = copy_to_mode_reg (Pmode, op[1]);
+
+ if (op[0] == const0_rtx)
+ addr = gen_rtx_MEM (tmode, op[1]);
+ else
+ {
+ op[0] = copy_to_mode_reg (tmode, op[0]);
+ addr = gen_rtx_MEM (smode,
+ gen_rtx_PLUS (Pmode, op[1], op[0]));
+ }
+
+ if (icode == CODE_FOR_vsx_lxvrbx
+ || icode == CODE_FOR_vsx_lxvrhx
+ || icode == CODE_FOR_vsx_lxvrwx
+ || icode == CODE_FOR_vsx_lxvrdx)
+ {
+ rtx discratch = gen_reg_rtx (DImode);
+ rtx tiscratch = gen_reg_rtx (TImode);
+
+ /* Emit the lxvr*x insn. */
+ pat = GEN_FCN (icode) (tiscratch, addr);
+ if (!pat)
+ return 0;
+ emit_insn (pat);
+
+ /* Emit a sign extension from QI,HI,WI to double (DI). */
+ rtx scratch = gen_lowpart (smode, tiscratch);
+ if (icode == CODE_FOR_vsx_lxvrbx)
+ emit_insn (gen_extendqidi2 (discratch, scratch));
+ else if (icode == CODE_FOR_vsx_lxvrhx)
+ emit_insn (gen_extendhidi2 (discratch, scratch));
+ else if (icode == CODE_FOR_vsx_lxvrwx)
+ emit_insn (gen_extendsidi2 (discratch, scratch));
+ /* Assign discratch directly if scratch is already DI. */
+ if (icode == CODE_FOR_vsx_lxvrdx)
+ discratch = scratch;
+
+ /* Emit the sign extension from DI (double) to TI (quad). */
+ emit_insn (gen_extendditi2 (target, discratch));
+
+ return target;
+ }
+ else
+ {
+ /* Zero extend. */
+ pat = GEN_FCN (icode) (target, addr);
+ if (!pat)
+ return 0;
+ emit_insn (pat);
+ return target;
+ }
+ return 0;
+}
+
static rtx
stv_expand_builtin (insn_code icode, rtx *op,
machine_mode tmode, machine_mode smode)
{
- rtx pat, addr, rawaddr;
+ rtx pat, addr, rawaddr, truncrtx;
op[2] = copy_to_mode_reg (Pmode, op[2]);
/* For STVX, express the RTL accurately by ANDing the address with -16.
@@ -13587,6 +13646,25 @@ stv_expand_builtin (insn_code icode, rtx *op,
op[0] = copy_to_mode_reg (tmode, op[0]);
emit_insn (gen_rtx_SET (addr, op[0]));
}
+ else if (icode == CODE_FOR_vsx_stxvrbx
+ || icode == CODE_FOR_vsx_stxvrhx
+ || icode == CODE_FOR_vsx_stxvrwx
+ || icode == CODE_FOR_vsx_stxvrdx)
+ {
+ truncrtx = gen_rtx_TRUNCATE (tmode, op[0]);
+ op[0] = copy_to_mode_reg (E_TImode, truncrtx);
+
+ if (op[1] == const0_rtx)
+ addr = gen_rtx_MEM (Pmode, op[2]);
+ else
+ {
+ op[1] = copy_to_mode_reg (Pmode, op[1]);
+ addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op[2], op[1]));
+ }
+ pat = GEN_FCN (icode) (addr, op[0]);
+ if (pat)
+ emit_insn (pat);
+ }
else
{
if (! (*insn_data[icode].operand[1].predicate) (op[0], smode))
@@ -15412,6 +15490,9 @@ rs6000_expand_new_builtin (tree exp, rtx target,
return ldv_expand_builtin (target, icode, op, mode[0]);
}
+ if (bif_is_lxvr (*bifaddr))
+ return lxvr_expand_builtin (target, icode, op, mode[0], mode[1]);
+
if (bif_is_mma (*bifaddr))
return new_mma_expand_builtin (exp, target, icode);
^ permalink raw reply [flat|nested] 29+ messages in thread
* [gcc(refs/users/wschmidt/heads/builtins4)] rs6000: More bug fixes
@ 2021-02-22 20:27 William Schmidt
0 siblings, 0 replies; 29+ messages in thread
From: William Schmidt @ 2021-02-22 20:27 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:787eac10312bd306726e26ac43efd34aab6c5216
commit 787eac10312bd306726e26ac43efd34aab6c5216
Author: Bill Schmidt <wschmidt@linux.ibm.com>
Date: Mon Feb 22 14:17:57 2021 -0600
rs6000: More bug fixes
2021-02-18 Bill Schmidt <wschmidt@linux.ibm.com>
gcc/
* config/rs6000/altivec.h (vec_vpopcnt): Remove #define.
(vec_vpopcntu): New #define.
* config/rs6000/rs6000-overload.def (VEC_POPCNT): Use
__builtin_vec_vpopcntu, and make all return values unsigned.
(VEC_VAVGUB): Use unsigned params and return values.
(VEC_VAVGUH): Likewise.
(VEC_VAVGUW): Likewise.
(VEC_VMAXUD): Likewise.
(VEC_VMINUD): Likewise.
(VEC_VPOPCNT): New.
(VEC_VPOPCNTU): Remove.
(VEC_VSPLTW): Add vector float support.
gcc/testsuite/
* gcc.target/powerpc/builtins-3-p9-runnable.c: Revert to master.
Diff:
---
gcc/config/rs6000/altivec.h | 2 +-
gcc/config/rs6000/rs6000-overload.def | 74 +++++++++++-----------
.../gcc.target/powerpc/builtins-3-p9-runnable.c | 16 ++---
3 files changed, 47 insertions(+), 45 deletions(-)
diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h
index 0d31f1897ba..3d68b787a75 100644
--- a/gcc/config/rs6000/altivec.h
+++ b/gcc/config/rs6000/altivec.h
@@ -105,7 +105,7 @@
#define vec_vgbbd vec_gb
#define vec_vmrgew vec_mergee
#define vec_vmrgow vec_mergeo
-#define vec_vpopcnt vec_popcnt
+#define vec_vpopcntu vec_popcnt
#define vec_vrld vec_rl
#define vec_vsld vec_sl
#define vec_vsrd vec_sr
diff --git a/gcc/config/rs6000/rs6000-overload.def b/gcc/config/rs6000/rs6000-overload.def
index 11e593e91d4..db881e7bb65 100644
--- a/gcc/config/rs6000/rs6000-overload.def
+++ b/gcc/config/rs6000/rs6000-overload.def
@@ -2933,22 +2933,22 @@
vuq __builtin_vec_vpmsum (vull, vull);
VPMSUMD VPMSUMD_V
-[VEC_POPCNT, vec_popcnt, __builtin_vec_vpopcnt, _ARCH_PWR8]
- vsc __builtin_vec_vpopcnt (vsc);
+[VEC_POPCNT, vec_popcnt, __builtin_vec_vpopcntu, _ARCH_PWR8]
+ vuc __builtin_vec_vpopcntu (vsc);
VPOPCNTB
- vuc __builtin_vec_vpopcnt (vuc);
+ vuc __builtin_vec_vpopcntu (vuc);
VPOPCNTUB
- vss __builtin_vec_vpopcnt (vss);
+ vus __builtin_vec_vpopcntu (vss);
VPOPCNTH
- vus __builtin_vec_vpopcnt (vus);
+ vus __builtin_vec_vpopcntu (vus);
VPOPCNTUH
- vsi __builtin_vec_vpopcnt (vsi);
+ vui __builtin_vec_vpopcntu (vsi);
VPOPCNTW
- vui __builtin_vec_vpopcnt (vui);
+ vui __builtin_vec_vpopcntu (vui);
VPOPCNTUW
- vsll __builtin_vec_vpopcnt (vsll);
+ vull __builtin_vec_vpopcntu (vsll);
VPOPCNTD
- vull __builtin_vec_vpopcnt (vull);
+ vull __builtin_vec_vpopcntu (vull);
VPOPCNTUD
[VEC_PARITY_LSBB, vec_parity_lsbb, __builtin_vec_vparity_lsbb, _ARCH_PWR9]
@@ -5114,15 +5114,15 @@
VAVGSW VAVGSW_DEPR1
[VEC_VAVGUB, vec_vavgub, __builtin_vec_vavgub]
- vsc __builtin_vec_vavgub (vsc, vsc);
+ vuc __builtin_vec_vavgub (vuc, vuc);
VAVGUB VAVGUB_DEPR1
[VEC_VAVGUH, vec_vavguh, __builtin_vec_vavguh]
- vss __builtin_vec_vavguh (vss, vss);
+ vus __builtin_vec_vavguh (vus, vus);
VAVGUH VAVGUH_DEPR1
[VEC_VAVGUW, vec_vavguw, __builtin_vec_vavguw]
- vsi __builtin_vec_vavguw (vsi, vsi);
+ vui __builtin_vec_vavguw (vui, vui);
VAVGUW VAVGUW_DEPR1
[VEC_VBPERMQ, vec_vbpermq, __builtin_vec_vbpermq, _ARCH_PWR8]
@@ -5290,11 +5290,11 @@
VMAXUB VMAXUB_DEPR5
[VEC_VMAXUD, vec_vmaxud, __builtin_vec_vmaxud]
- vsll __builtin_vec_vmaxud (vsll, vsll);
+ vull __builtin_vec_vmaxud (vull, vull);
VMAXUD VMAXUD_DEPR1
- vsll __builtin_vec_vmaxud (vbll, vsll);
+ vull __builtin_vec_vmaxud (vbll, vull);
VMAXUD VMAXUD_DEPR2
- vsll __builtin_vec_vmaxud (vsll, vbll);
+ vull __builtin_vec_vmaxud (vull, vbll);
VMAXUD VMAXUD_DEPR3
[VEC_VMAXUH, vec_vmaxuh, __builtin_vec_vmaxuh]
@@ -5370,11 +5370,11 @@
VMINUB VMINUB_DEPR5
[VEC_VMINUD, vec_vminud, __builtin_vec_vminud]
- vsll __builtin_vec_vminud (vsll, vsll);
+ vull __builtin_vec_vminud (vull, vull);
VMINUD VMINUD_DEPR1
- vsll __builtin_vec_vminud (vbll, vsll);
+ vull __builtin_vec_vminud (vbll, vull);
VMINUD VMINUD_DEPR2
- vsll __builtin_vec_vminud (vsll, vbll);
+ vull __builtin_vec_vminud (vull, vbll);
VMINUD VMINUD_DEPR3
[VEC_VMINUH, vec_vminuh, __builtin_vec_vminuh]
@@ -5589,6 +5589,24 @@
vus __builtin_vec_vpkuwus (vui, vui);
VPKUWUS VPKUWUS_DEPR1
+[VEC_VPOPCNT, vec_vpopcnt, __builtin_vec_vpopcnt, _ARCH_PWR8]
+ vsc __builtin_vec_vpopcnt (vsc);
+ VPOPCNTB VPOPCNT_DEPR1
+ vuc __builtin_vec_vpopcnt (vuc);
+ VPOPCNTB VPOPCNT_DEPR2
+ vss __builtin_vec_vpopcnt (vss);
+ VPOPCNTH VPOPCNT_DEPR3
+ vus __builtin_vec_vpopcnt (vus);
+ VPOPCNTH VPOPCNT_DEPR4
+ vsi __builtin_vec_vpopcnt (vsi);
+ VPOPCNTW VPOPCNT_DEPR5
+ vui __builtin_vec_vpopcnt (vui);
+ VPOPCNTW VPOPCNT_DEPR6
+ vsll __builtin_vec_vpopcnt (vsll);
+ VPOPCNTD VPOPCNT_DEPR7
+ vull __builtin_vec_vpopcnt (vull);
+ VPOPCNTD VPOPCNT_DEPR8
+
[VEC_VPOPCNTB, vec_vpopcntb, __builtin_vec_vpopcntb, _ARCH_PWR8]
vsc __builtin_vec_vpopcntb (vsc);
VPOPCNTB VPOPCNTB_DEPR1
@@ -5607,24 +5625,6 @@
vus __builtin_vec_vpopcnth (vus);
VPOPCNTH VPOPCNTH_DEPR2
-[VEC_VPOPCNTU, SKIP, __builtin_vec_vpopcntu, _ARCH_PWR8]
- vuc __builtin_vec_vpopcntu (vsc);
- VPOPCNTUB VPOPCNTU_DEPR1
- vuc __builtin_vec_vpopcntu (vuc);
- VPOPCNTUB VPOPCNTU_DEPR2
- vus __builtin_vec_vpopcntu (vss);
- VPOPCNTUH VPOPCNTU_DEPR3
- vus __builtin_vec_vpopcntu (vus);
- VPOPCNTUH VPOPCNTU_DEPR4
- vui __builtin_vec_vpopcntu (vsi);
- VPOPCNTUW VPOPCNTU_DEPR5
- vui __builtin_vec_vpopcntu (vui);
- VPOPCNTUW VPOPCNTU_DEPR6
- vull __builtin_vec_vpopcntu (vsll);
- VPOPCNTUD VPOPCNTU_DEPR7
- vull __builtin_vec_vpopcntu (vull);
- VPOPCNTUD VPOPCNTU_DEPR8
-
[VEC_VPOPCNTW, vec_vpopcntw, __builtin_vec_vpopcntw, _ARCH_PWR8]
vsi __builtin_vec_vpopcntw (vsi);
VPOPCNTW VPOPCNTW_DEPR1
@@ -5726,6 +5726,8 @@
VSPLTW VSPLTW_DEPR2
vbi __builtin_vec_vspltw (vbi, const int);
VSPLTW VSPLTW_DEPR3
+ vf __builtin_vec_vspltw (vf, const int);
+ VSPLTW VSPLTW_DEPR4
[VEC_VSRAB, vec_vsrab, __builtin_vec_vsrab]
vsc __builtin_vec_vsrab (vsc, vuc);
diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-3-p9-runnable.c b/gcc/testsuite/gcc.target/powerpc/builtins-3-p9-runnable.c
index 5f9255861bb..44c0397c49a 100644
--- a/gcc/testsuite/gcc.target/powerpc/builtins-3-p9-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/builtins-3-p9-runnable.c
@@ -44,10 +44,10 @@ int main() {
test both builtin function names. */
vfexpt = (vector float){1.0, -2.0, 0.0, 8.5};
- vfr = vec_extract_fp_from_shorth(vusha);
+ vfr = vec_extract_fp32_from_shorth(vusha);
#ifdef DEBUG
- printf ("vec_extract_fp_from_shorth\n");
+ printf ("vec_extract_fp32_from_shorth\n");
for (i=0; i<4; i++)
printf("result[%d] = %f; expected[%d] = %f\n",
i, vfr[i], i, vfexpt[i]);
@@ -59,10 +59,10 @@ int main() {
}
vfexpt = (vector float){1.5, 0.5, 1.25, -0.25};
- vfr = vec_extract_fp_from_shortl(vusha);
+ vfr = vec_extract_fp32_from_shortl(vusha);
#ifdef DEBUG
- printf ("\nvec_extract_fp_from_shortl\n");
+ printf ("\nvec_extract_fp32_from_shortl\n");
for (i=0; i<4; i++)
printf("result[%d] = %f; expected[%d] = %f\n",
i, vfr[i], i, vfexpt[i]);
@@ -73,10 +73,10 @@ int main() {
abort();
}
vfexpt = (vector float){1.0, -2.0, 0.0, 8.5};
- vfr = vec_extract_fp32_from_shorth(vusha);
+ vfr = vec_extract_fp_from_shorth(vusha);
#ifdef DEBUG
- printf ("vec_extract_fp32_from_shorth\n");
+ printf ("vec_extract_fp_from_shorth\n");
for (i=0; i<4; i++)
printf("result[%d] = %f; expected[%d] = %f\n",
i, vfr[i], i, vfexpt[i]);
@@ -88,10 +88,10 @@ int main() {
}
vfexpt = (vector float){1.5, 0.5, 1.25, -0.25};
- vfr = vec_extract_fp32_from_shortl(vusha);
+ vfr = vec_extract_fp_from_shortl(vusha);
#ifdef DEBUG
- printf ("\nvec_extract_fp32_from_shortl\n");
+ printf ("\nvec_extract_fp_from_shortl\n");
for (i=0; i<4; i++)
printf("result[%d] = %f; expected[%d] = %f\n",
i, vfr[i], i, vfexpt[i]);
^ permalink raw reply [flat|nested] 29+ messages in thread
* [gcc(refs/users/wschmidt/heads/builtins4)] rs6000: More bug fixes
@ 2021-02-07 18:18 William Schmidt
0 siblings, 0 replies; 29+ messages in thread
From: William Schmidt @ 2021-02-07 18:18 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:8cebc4fb33ff06d1df128512e67e33a61b348109
commit 8cebc4fb33ff06d1df128512e67e33a61b348109
Author: Bill Schmidt <wschmidt@linux.ibm.com>
Date: Sun Feb 7 11:48:07 2021 -0600
rs6000: More bug fixes
2021-02-07 Bill Schmidt <wschmidt@linux.ibm.com>
gcc/
* config/rs6000/rs6000-builtin-new.def: Clean up.
* config/rs6000/rs6000-gen-builtins.c (write_init_file): Remove
timevar stuff.
* timevar.def (TV_BILL): Remove.
Diff:
---
gcc/config/rs6000/rs6000-builtin-new.def | 8 --------
gcc/config/rs6000/rs6000-gen-builtins.c | 3 ---
gcc/timevar.def | 3 ---
3 files changed, 14 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-builtin-new.def b/gcc/config/rs6000/rs6000-builtin-new.def
index 24fd7ed182d..5e63df13516 100644
--- a/gcc/config/rs6000/rs6000-builtin-new.def
+++ b/gcc/config/rs6000/rs6000-builtin-new.def
@@ -1735,12 +1735,8 @@
const vd __builtin_vsx_xvcvsxwdp (vsi);
XVCVSXWDP vsx_xvcvsxwdp {}
-; Need to pick one or the other here!! ####
-; The first is needed to make vec_float work correctly.
const vf __builtin_vsx_xvcvsxwsp (vsi);
XVCVSXWSP vsx_floatv4siv4sf2 {}
-; const vf __builtin_vsx_xvcvsxwsp (vsi);
-; XVCVSXWSP_V4SF vsx_xvcvsxwdp {}
const vd __builtin_vsx_xvcvuxddp (vull);
XVCVUXDDP vsx_floatunsv2div2df2 {}
@@ -1758,12 +1754,8 @@
const vd __builtin_vsx_xvcvuxwdp (vsi);
XVCVUXWDP vsx_xvcvuxwdp {}
-; Need to pick one or the other here!! ####
-; The first is needed to make vec_float work correctly.
const vf __builtin_vsx_xvcvuxwsp (vui);
XVCVUXWSP vsx_floatunsv4siv4sf2 {}
-; const vf __builtin_vsx_xvcvuxwsp (vui);
-; XVCVUXWSP_V4SF vsx_xvcvuxwsp {}
fpmath vd __builtin_vsx_xvdivdp (vd, vd);
XVDIVDP divv2df3 {}
diff --git a/gcc/config/rs6000/rs6000-gen-builtins.c b/gcc/config/rs6000/rs6000-gen-builtins.c
index b75b29303dd..07222228310 100644
--- a/gcc/config/rs6000/rs6000-gen-builtins.c
+++ b/gcc/config/rs6000/rs6000-gen-builtins.c
@@ -2691,7 +2691,6 @@ write_init_file ()
fprintf (init_file, "#include \"tree.h\"\n");
fprintf (init_file, "#include \"langhooks.h\"\n");
fprintf (init_file, "#include \"insn-codes.h\"\n");
- fprintf (init_file, "#include \"timevar.h\"\n");
fprintf (init_file, "#include \"rs6000-builtins.h\"\n");
fprintf (init_file, "\n");
@@ -2715,7 +2714,6 @@ write_init_file ()
fprintf (init_file, "rs6000_autoinit_builtins ()\n");
fprintf (init_file, "{\n");
fprintf (init_file, " tree t;\n");
- fprintf (init_file, " timevar_start (TV_BILL);\n");
rbt_inorder_callback (&fntype_rbt, fntype_rbt.rbt_root, write_fntype_init);
fprintf (init_file, "\n");
@@ -2729,7 +2727,6 @@ write_init_file ()
write_init_bif_table ();
write_init_ovld_table ();
- fprintf (init_file, " timevar_stop (TV_BILL);\n");
fprintf (init_file, "}\n\n");
fprintf (init_file,
diff --git a/gcc/timevar.def b/gcc/timevar.def
index cea0ffa444d..63c0b3306de 100644
--- a/gcc/timevar.def
+++ b/gcc/timevar.def
@@ -340,6 +340,3 @@ DEFTIMEVAR (TV_ANALYZER_WORKLIST , "analyzer: processing worklist")
DEFTIMEVAR (TV_ANALYZER_DUMP , "analyzer: dump")
DEFTIMEVAR (TV_ANALYZER_DIAGNOSTICS , "analyzer: emitting diagnostics")
DEFTIMEVAR (TV_ANALYZER_SHORTEST_PATHS, "analyzer: shortest paths")
-
-/* Bill's timevar! */
-DEFTIMEVAR (TV_BILL, "builtin initialization")
^ permalink raw reply [flat|nested] 29+ messages in thread
* [gcc(refs/users/wschmidt/heads/builtins4)] rs6000: More bug fixes
@ 2021-02-07 18:18 William Schmidt
0 siblings, 0 replies; 29+ messages in thread
From: William Schmidt @ 2021-02-07 18:18 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:48a505844de0403d3f2a5598335ef40baa7bf0df
commit 48a505844de0403d3f2a5598335ef40baa7bf0df
Author: Bill Schmidt <wschmidt@linux.ibm.com>
Date: Sun Jan 31 18:34:34 2021 -0600
rs6000: More bug fixes
2021-01-31 Bill Schmidt <wschmidt@linux.ibm.com>
gcc/
* config/rs6000/altivec.h: Update deprecated interfaces.
* config/rs6000/rs6000-builtin-new.def: Miscellaneous fixes.
* config/rs6000/rs6000-overload.def: Miscellaneous fixes.
gcc/testsuite/
* gcc.target/powerpc/vec-gnb-2.c: Adjust.
* gcc.target/powerpc/vsu/vec-all-nez-7.c: Adjust.
* gcc.target/powerpc/vsu/vec-any-eqz-7.c: Adjust.
* gcc.target/powerpc/vsu/vec-cmpnez-7.c: Adjust.
* gcc.target/powerpc/vsu/vec-cntlz-lsbb-2.c: Adjust.
* gcc.target/powerpc/vsu/vec-cnttz-lsbb-2.c: Adjust.
* gcc.target/powerpc/vsu/vec-xst-len-12.c: Adjust.
Diff:
---
gcc/config/rs6000/altivec.h | 16 +++++++------
gcc/config/rs6000/rs6000-builtin-new.def | 26 ++++++++++----------
gcc/config/rs6000/rs6000-overload.def | 28 ++++++++++++++--------
gcc/testsuite/gcc.target/powerpc/vec-gnb-2.c | 2 +-
.../gcc.target/powerpc/vsu/vec-all-nez-7.c | 2 +-
.../gcc.target/powerpc/vsu/vec-any-eqz-7.c | 2 +-
.../gcc.target/powerpc/vsu/vec-cmpnez-7.c | 2 +-
.../gcc.target/powerpc/vsu/vec-cntlz-lsbb-2.c | 2 +-
.../gcc.target/powerpc/vsu/vec-cnttz-lsbb-2.c | 2 +-
.../gcc.target/powerpc/vsu/vec-xst-len-12.c | 2 +-
10 files changed, 47 insertions(+), 37 deletions(-)
diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h
index a69e5a398d8..0415e90374d 100644
--- a/gcc/config/rs6000/altivec.h
+++ b/gcc/config/rs6000/altivec.h
@@ -58,18 +58,20 @@
#include "rs6000-vecdefines.h"
/* Deprecated interfaces. */
-#define vec_vsld vec_sld
-#define vec_vsrad vec_srad
-#define vec_vsrd vec_srd
+#ifdef _ARCH_PWR8
+#define vec_vsld vec_sl
+#define vec_vsrd vec_sr
+#define vec_vsrad vec_sra
+#endif
#ifdef _ARCH_PWR9
#define __builtin_vec_vadub __builtin_vec_vadu
#define __builtin_vec_vaduh __builtin_vec_vadu
#define __builtin_vec_vaduw __builtin_vec_vadu
-#define __builtin_vec_vprtybw __builtin_vec_vprtyb
-#define __builtin_vec_vprtybd __builtin_vec_vprtyb
-#define __builtin_vec_vprtybq __builtin_vec_vprtyb
-#define vec_vrlnm vec_rlnm
+#define vec_vprtybw vec_vprtyb
+#define vec_vprtybd vec_vprtyb
+#define vec_vprtybq vec_vprtyb
+#define vec_vrlnm __builtin_vec_rlnm
#endif
/* Synonyms. */
diff --git a/gcc/config/rs6000/rs6000-builtin-new.def b/gcc/config/rs6000/rs6000-builtin-new.def
index 84654e872e0..24fd7ed182d 100644
--- a/gcc/config/rs6000/rs6000-builtin-new.def
+++ b/gcc/config/rs6000/rs6000-builtin-new.def
@@ -1647,37 +1647,37 @@
fpmath vf __builtin_vsx_xvaddsp (vf, vf);
XVADDSP addv4sf3 {}
- const vbll __builtin_vsx_xvcmpeqdp (vd, vd);
+ const vd __builtin_vsx_xvcmpeqdp (vd, vd);
XVCMPEQDP vector_eqv2df {}
const signed int __builtin_vsx_xvcmpeqdp_p (signed int, vd, vd);
XVCMPEQDP_P vector_eq_v2df_p {pred}
- const vbi __builtin_vsx_xvcmpeqsp (vf, vf);
+ const vf __builtin_vsx_xvcmpeqsp (vf, vf);
XVCMPEQSP vector_eqv4sf {}
const signed int __builtin_vsx_xvcmpeqsp_p (signed int, vf, vf);
XVCMPEQSP_P vector_eq_v4sf_p {pred}
- const vbll __builtin_vsx_xvcmpgedp (vd, vd);
+ const vd __builtin_vsx_xvcmpgedp (vd, vd);
XVCMPGEDP vector_gev2df {}
const signed int __builtin_vsx_xvcmpgedp_p (signed int, vd, vd);
XVCMPGEDP_P vector_ge_v2df_p {pred}
- const vbi __builtin_vsx_xvcmpgesp (vf, vf);
+ const vf __builtin_vsx_xvcmpgesp (vf, vf);
XVCMPGESP vector_gev4sf {}
const signed int __builtin_vsx_xvcmpgesp_p (signed int, vf, vf);
XVCMPGESP_P vector_ge_v4sf_p {pred}
- const vbll __builtin_vsx_xvcmpgtdp (vd, vd);
+ const vd __builtin_vsx_xvcmpgtdp (vd, vd);
XVCMPGTDP vector_gtv2df {}
const signed int __builtin_vsx_xvcmpgtdp_p (signed int, vd, vd);
XVCMPGTDP_P vector_gt_v2df_p {pred}
- const vbi __builtin_vsx_xvcmpgtsp (vf, vf);
+ const vf __builtin_vsx_xvcmpgtsp (vf, vf);
XVCMPGTSP vector_gtv4sf {}
const signed int __builtin_vsx_xvcmpgtsp_p (signed int, vf, vf);
@@ -1927,25 +1927,25 @@
const vsi __builtin_vsx_xxmrglw_4si (vsi, vsi);
XXMRGLW_4SI vsx_xxmrglw_v4si {}
- const vsc __builtin_vsx_xxpermdi_16qi (vsc, vsc, const int<1>);
+ const vsc __builtin_vsx_xxpermdi_16qi (vsc, vsc, const int<2>);
XXPERMDI_16QI vsx_xxpermdi_v16qi {}
- const vsq __builtin_vsx_xxpermdi_1ti (vsq, vsq, const int<1>);
+ const vsq __builtin_vsx_xxpermdi_1ti (vsq, vsq, const int<2>);
XXPERMDI_1TI vsx_xxpermdi_v1ti {}
- const vd __builtin_vsx_xxpermdi_2df (vd, vd, const int<1>);
+ const vd __builtin_vsx_xxpermdi_2df (vd, vd, const int<2>);
XXPERMDI_2DF vsx_xxpermdi_v2df {}
- const vsll __builtin_vsx_xxpermdi_2di (vsll, vsll, const int<1>);
+ const vsll __builtin_vsx_xxpermdi_2di (vsll, vsll, const int<2>);
XXPERMDI_2DI vsx_xxpermdi_v2di {}
- const vf __builtin_vsx_xxpermdi_4sf (vf, vf, const int<1>);
+ const vf __builtin_vsx_xxpermdi_4sf (vf, vf, const int<2>);
XXPERMDI_4SF vsx_xxpermdi_v4sf {}
- const vsi __builtin_vsx_xxpermdi_4si (vsi, vsi, const int<1>);
+ const vsi __builtin_vsx_xxpermdi_4si (vsi, vsi, const int<2>);
XXPERMDI_4SI vsx_xxpermdi_v4si {}
- const vss __builtin_vsx_xxpermdi_8hi (vss, vss, const int<1>);
+ const vss __builtin_vsx_xxpermdi_8hi (vss, vss, const int<2>);
XXPERMDI_8HI vsx_xxpermdi_v8hi {}
const vsc __builtin_vsx_xxsel_16qi (vsc, vsc, vsc);
diff --git a/gcc/config/rs6000/rs6000-overload.def b/gcc/config/rs6000/rs6000-overload.def
index a2651e59c9f..90d17ee90e1 100644
--- a/gcc/config/rs6000/rs6000-overload.def
+++ b/gcc/config/rs6000/rs6000-overload.def
@@ -992,7 +992,7 @@
signed int __builtin_vec_vcmpne_p (signed int, vbll, vsll);
VCMPNED_P VCMPNED_P_SB
-[VEC_CMPNEZ, vec_cmpnez, __builtin_vec_cmpnez, _ARCH_PWR9]
+[VEC_CMPNEZ, vec_cmpnez, __builtin_vec_vcmpnez, _ARCH_PWR9]
vbc __builtin_vec_cmpnez (vsc, vsc);
CMPNEZB CMPNEZB_S
vbc __builtin_vec_cmpnez (vuc, vuc);
@@ -1654,19 +1654,19 @@
MTVSRBM
[VEC_GENHM, vec_genhm, __builtin_vec_mtvsrhm, _ARCH_PWR10]
- vuc __builtin_vec_mtvsrhm (unsigned long long);
+ vus __builtin_vec_mtvsrhm (unsigned long long);
MTVSRHM
[VEC_GENWM, vec_genwm, __builtin_vec_mtvsrwm, _ARCH_PWR10]
- vuc __builtin_vec_mtvsrwm (unsigned long long);
+ vui __builtin_vec_mtvsrwm (unsigned long long);
MTVSRWM
[VEC_GENDM, vec_gendm, __builtin_vec_mtvsrdm, _ARCH_PWR10]
- vuc __builtin_vec_mtvsrdm (unsigned long long);
+ vull __builtin_vec_mtvsrdm (unsigned long long);
MTVSRDM
[VEC_GENQM, vec_genqm, __builtin_vec_mtvsrqm, _ARCH_PWR10]
- vuc __builtin_vec_mtvsrqm (unsigned long long);
+ vuq __builtin_vec_mtvsrqm (unsigned long long);
MTVSRQM
[VEC_GENPCVM, vec_genpcvm, __builtin_vec_xxgenpcvm, _ARCH_PWR10]
@@ -3462,7 +3462,7 @@
vf __builtin_vec_xxspltiw (float);
VXXSPLTIW_V4SF
-[VEC_SPLATID, vec_splatid, __builtin_vec_xxspltid, ARCH_PWR10]
+[VEC_SPLATID, vec_splatid, __builtin_vec_xxspltid, _ARCH_PWR10]
vd __builtin_vec_xxspltid (float);
VXXSPLTIDP
@@ -4417,6 +4417,8 @@
LXVW4X_V16QI LXVW4X_VUC
vuc __builtin_vec_vsx_ld (signed long long, const unsigned char *);
LXVW4X_V16QI LXVW4X_UC
+ vbc __builtin_vec_vsx_ld (signed long long, const vbc *);
+ LXVW4X_V16QI LXVW4X_VBC
vss __builtin_vec_vsx_ld (signed long long, const vss *);
LXVW4X_V8HI LXVW4X_VSS
vss __builtin_vec_vsx_ld (signed long long, const signed short *);
@@ -4425,6 +4427,8 @@
LXVW4X_V8HI LXVW4X_VUS
vus __builtin_vec_vsx_ld (signed long long, const unsigned short *);
LXVW4X_V8HI LXVW4X_US
+ vbs __builtin_vec_vsx_ld (signed long long, const vbs *);
+ LXVW4X_V8HI LXVW4X_VBS
vp __builtin_vec_vsx_ld (signed long long, const vp *);
LXVW4X_V8HI LXVW4X_P
vsi __builtin_vec_vsx_ld (signed long long, const vsi *);
@@ -4435,6 +4439,8 @@
LXVW4X_V4SI LXVW4X_VUI
vui __builtin_vec_vsx_ld (signed long long, const unsigned int *);
LXVW4X_V4SI LXVW4X_UI
+ vbi __builtin_vec_vsx_ld (signed long long, const vbi *);
+ LXVW4X_V4SI LXVW4X_VBI
vsll __builtin_vec_vsx_ld (signed long long, const vsll *);
LXVD2X_V2DI LXVD2X_VSLL
vsll __builtin_vec_vsx_ld (signed long long, const signed long long *);
@@ -4443,6 +4449,8 @@
LXVD2X_V2DI LXVD2X_VULL
vull __builtin_vec_vsx_ld (signed long long, const unsigned long long *);
LXVD2X_V2DI LXVD2X_ULL
+ vbll __builtin_vec_vsx_ld (signed long long, const vbll *);
+ LXVD2X_V2DI LXVD2X_VBLL
vsq __builtin_vec_vsx_ld (signed long long, const vsq *);
LXVD2X_V1TI LXVD2X_VSQ
vsq __builtin_vec_vsx_ld (signed long long, const signed __int128 *);
@@ -4519,13 +4527,13 @@
SE_LXVRDX
[VEC_XL_ZEXT, vec_xl_zext, __builtin_vec_xl_zext, _ARCH_PWR10]
- vsq __builtin_vec_xl_zext (signed long long, const signed char *);
+ vuq __builtin_vec_xl_zext (signed long long, const unsigned char *);
ZE_LXVRBX
- vsq __builtin_vec_xl_zext (signed long long, const signed short *);
+ vuq __builtin_vec_xl_zext (signed long long, const unsigned short *);
ZE_LXVRHX
- vsq __builtin_vec_xl_zext (signed long long, const signed int *);
+ vuq __builtin_vec_xl_zext (signed long long, const unsigned int *);
ZE_LXVRWX
- vsq __builtin_vec_xl_zext (signed long long, const signed long long *);
+ vuq __builtin_vec_xl_zext (signed long long, const unsigned long long *);
ZE_LXVRDX
[VEC_XOR, vec_xor, __builtin_vec_xor]
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-gnb-2.c b/gcc/testsuite/gcc.target/powerpc/vec-gnb-2.c
index 895bb953b37..4e59cbffa17 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-gnb-2.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-gnb-2.c
@@ -20,7 +20,7 @@ do_vec_gnb (vector unsigned __int128 source, int stride)
case 5:
return vec_gnb (source, 1); /* { dg-error "between 2 and 7" } */
case 6:
- return vec_gnb (source, stride); /* { dg-error "unsigned literal" } */
+ return vec_gnb (source, stride); /* { dg-error "literal" } */
case 7:
return vec_gnb (source, 7);
diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-7.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-7.c
index f53c6dca0a9..d1ef054b488 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-7.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-7.c
@@ -12,5 +12,5 @@ test_all_not_equal_and_not_zero (vector unsigned short *arg1_p,
vector unsigned short arg_2 = *arg2_p;
return __builtin_vec_vcmpnez_p (__CR6_LT, arg_1, arg_2);
- /* { dg-error "'__builtin_altivec_vcmpnezh_p' requires the '-mcpu=power9' option" "" { target *-*-* } .-1 } */
+ /* { dg-error "'__builtin_altivec_vcmpnezh_p' requires the '-mpower9-vector' option" "" { target *-*-* } .-1 } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-7.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-7.c
index 757acd93110..b5cdea5fb3e 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-7.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-7.c
@@ -11,5 +11,5 @@ test_any_equal (vector unsigned int *arg1_p, vector unsigned int *arg2_p)
vector unsigned int arg_2 = *arg2_p;
return __builtin_vec_vcmpnez_p (__CR6_LT_REV, arg_1, arg_2);
- /* { dg-error "'__builtin_altivec_vcmpnezw_p' requires the '-mcpu=power9' option" "" { target *-*-* } .-1 } */
+ /* { dg-error "'__builtin_altivec_vcmpnezw_p' requires the '-mpower9-vector' option" "" { target *-*-* } .-1 } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-7.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-7.c
index 811b32f1c32..320421e6028 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-7.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-7.c
@@ -10,5 +10,5 @@ fetch_data (vector unsigned int *arg1_p, vector unsigned int *arg2_p)
vector unsigned int arg_1 = *arg1_p;
vector unsigned int arg_2 = *arg2_p;
- return __builtin_vec_vcmpnez (arg_1, arg_2); /* { dg-error "'__builtin_altivec_vcmpnezw' requires the '-mcpu=power9' option" } */
+ return __builtin_vec_vcmpnez (arg_1, arg_2); /* { dg-error "'__builtin_altivec_vcmpnezw' requires the '-mpower9-vector' option" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-2.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-2.c
index 6ee066d1eff..251285536c2 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-2.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-2.c
@@ -9,5 +9,5 @@ count_leading_zero_byte_bits (vector unsigned char *arg1_p)
{
vector unsigned char arg_1 = *arg1_p;
- return __builtin_vec_vclzlsbb (arg_1); /* { dg-error "'__builtin_altivec_vclzlsbb_v16qi' requires the '-mcpu=power9' option" } */
+ return __builtin_vec_vclzlsbb (arg_1); /* { dg-error "'__builtin_altivec_vclzlsbb_v16qi' requires the '-mpower9-vector' option" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-2.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-2.c
index ecd0add70d0..83ca92daced 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-2.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-2.c
@@ -9,5 +9,5 @@ count_trailing_zero_byte_bits (vector unsigned char *arg1_p)
{
vector unsigned char arg_1 = *arg1_p;
- return __builtin_vec_vctzlsbb (arg_1); /* { dg-error "'__builtin_altivec_vctzlsbb_v16qi' requires the '-mcpu=power9' option" } */
+ return __builtin_vec_vctzlsbb (arg_1); /* { dg-error "'__builtin_altivec_vctzlsbb_v16qi' requires the '-mpower9-vector' option" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-12.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-12.c
index 3a51132a5a2..f30d49cb4cc 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-12.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-12.c
@@ -13,5 +13,5 @@ store_data (vector double *datap, double *address, size_t length)
{
vector double data = *datap;
- __builtin_vec_stxvl (data, address, length); /* { dg-error "'__builtin_vec_stxvl' is not supported in this compiler configuration" } */
+ __builtin_vec_stxvl (data, address, length); /* { dg-error "'__builtin_altivec_stxvl' requires the" } */
}
^ permalink raw reply [flat|nested] 29+ messages in thread
* [gcc(refs/users/wschmidt/heads/builtins4)] rs6000: More bug fixes
@ 2021-02-07 18:18 William Schmidt
0 siblings, 0 replies; 29+ messages in thread
From: William Schmidt @ 2021-02-07 18:18 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:ed1b31043199153702c567e0bef36c058440eb11
commit ed1b31043199153702c567e0bef36c058440eb11
Author: Bill Schmidt <wschmidt@linux.ibm.com>
Date: Thu Jan 28 17:21:38 2021 -0600
rs6000: More bug fixes
2021-01-28 Bill Schmidt <wschmidt@linux.ibm.com>
gcc/
* config/rs6000/altivec.h: Add deprecated interfaces.
* config/rs6000/rs6000-builtin-new.def (__builtin_altivec_vgnb):
Fix prototype.
* config/rs6000/rs6000-overload.def: Miscellaneous fixes.
gcc/testsuite/
* gcc.target/powerpc/p9-vparity.c: Revert earlier changes.
Diff:
---
gcc/config/rs6000/altivec.h | 22 ++++++++++++------
gcc/config/rs6000/rs6000-builtin-new.def | 2 +-
gcc/config/rs6000/rs6000-overload.def | 24 ++++++++++++++++++--
gcc/testsuite/gcc.target/powerpc/p9-vparity.c | 32 +++++++++++++--------------
4 files changed, 54 insertions(+), 26 deletions(-)
diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h
index 86464722d07..a69e5a398d8 100644
--- a/gcc/config/rs6000/altivec.h
+++ b/gcc/config/rs6000/altivec.h
@@ -57,6 +57,21 @@
#include "rs6000-vecdefines.h"
+/* Deprecated interfaces. */
+#define vec_vsld vec_sld
+#define vec_vsrad vec_srad
+#define vec_vsrd vec_srd
+
+#ifdef _ARCH_PWR9
+#define __builtin_vec_vadub __builtin_vec_vadu
+#define __builtin_vec_vaduh __builtin_vec_vadu
+#define __builtin_vec_vaduw __builtin_vec_vadu
+#define __builtin_vec_vprtybw __builtin_vec_vprtyb
+#define __builtin_vec_vprtybd __builtin_vec_vprtyb
+#define __builtin_vec_vprtybq __builtin_vec_vprtyb
+#define vec_vrlnm vec_rlnm
+#endif
+
/* Synonyms. */
/* Functions that are resolved by the backend to one of the
typed builtins. */
@@ -264,13 +279,6 @@ __altivec_scalar_pred(vec_any_nle,
to #define vec_step to __builtin_vec_step. */
#define vec_step(x) __builtin_vec_step (* (__typeof__ (x) *) 0)
-/* Deprecated interfaces. */
-#ifdef _ARCH_PWR9
-#define __builtin_vec_vadub __builtin_vec_vadu
-#define __builtin_vec_vaduh __builtin_vec_vadu
-#define __builtin_vec_vaduw __builtin_vec_vadu
-#endif
-
#ifdef _ARCH_PWR10
/* #### TODO: Deal with Carl's new builtins. */
#define vec_mulh(a, b) __builtin_vec_mulh ((a), (b))
diff --git a/gcc/config/rs6000/rs6000-builtin-new.def b/gcc/config/rs6000/rs6000-builtin-new.def
index 417fd2a35dd..84654e872e0 100644
--- a/gcc/config/rs6000/rs6000-builtin-new.def
+++ b/gcc/config/rs6000/rs6000-builtin-new.def
@@ -3183,7 +3183,7 @@
const signed int __builtin_altivec_vextractmw (vui);
VEXTRACTMW vec_extract_v4si {}
- const unsigned long long __builtin_altivec_vgnb (vuq, const int <2,7>);
+ const unsigned long long __builtin_altivec_vgnb (vull, const int <2,7>);
VGNB vgnb {}
const vuc __builtin_altivec_vinsgubvlx (unsigned int, vuc, unsigned int);
diff --git a/gcc/config/rs6000/rs6000-overload.def b/gcc/config/rs6000/rs6000-overload.def
index 344c78b6a83..a2651e59c9f 100644
--- a/gcc/config/rs6000/rs6000-overload.def
+++ b/gcc/config/rs6000/rs6000-overload.def
@@ -3071,7 +3071,7 @@
vull __builtin_vec_rl (vull, vull);
VRLD VRLD_VULL
-[VEC_RLMI, vec_rlmi, __builtin_vec_rlmi]
+[VEC_RLMI, vec_rlmi, __builtin_vec_rlmi, _ARCH_PWR9]
vui __builtin_vec_rlmi (vui, vui, vui);
VRLWMI
vull __builtin_vec_rlmi (vull, vull, vull);
@@ -3079,7 +3079,7 @@
; We SKIP vec_rlnm so that altivec.h can define it as the three-operand
; form we expose to the users.
-[VEC_RLNM, SKIP, __builtin_vec_rlnm]
+[VEC_RLNM, SKIP, __builtin_vec_rlnm, _ARCH_PWR9]
vui __builtin_vec_rlnm (vui, vui);
VRLWNM
vull __builtin_vec_rlnm (vull, vull);
@@ -4320,6 +4320,26 @@
vd __builtin_vec_insert_exp (vull, vull);
VIEDP VIEDP_VULL
+; It is truly unfortunate that vec_vprtyb has an incompatible set of
+; interfaces with vec_parity_lsbb. So we can't even deprecate this.
+[VEC_VPRTYB, vec_vprtyb, __builtin_vec_vprtyb, _ARCH_PWR9]
+ vsi __builtin_vec_vprtyb (vsi);
+ VPRTYBW VPRTYB_VSI
+ vui __builtin_vec_vprtyb (vui);
+ VPRTYBW VPRTYB_VUI
+ vsll __builtin_vec_vprtyb (vsll);
+ VPRTYBD VPRTYB_VSLL
+ vull __builtin_vec_vprtyb (vull);
+ VPRTYBD VPRTYB_VULL
+ vsq __builtin_vec_vprtyb (vsq);
+ VPRTYBQ VPRTYB_VSQ
+ vuq __builtin_vec_vprtyb (vuq);
+ VPRTYBQ VPRTYB_VUQ
+ signed __int128 __builtin_vec_vprtyb (signed __int128);
+ VPRTYBQ VPRTYB_SQ
+ unsigned __int128 __builtin_vec_vprtyb (unsigned __int128);
+ VPRTYBQ VPRTYB_UQ
+
[VEC_VSCEEQ, scalar_cmp_exp_eq, __builtin_vec_scalar_cmp_exp_eq, _ARCH_PWR9]
signed int __builtin_vec_scalar_cmp_exp_eq (double, double);
VSCEDPEQ
diff --git a/gcc/testsuite/gcc.target/powerpc/p9-vparity.c b/gcc/testsuite/gcc.target/powerpc/p9-vparity.c
index 8897a5b6b7f..f4aba1567cd 100644
--- a/gcc/testsuite/gcc.target/powerpc/p9-vparity.c
+++ b/gcc/testsuite/gcc.target/powerpc/p9-vparity.c
@@ -9,97 +9,97 @@
vector int
parity_v4si_1s (vector int a)
{
- return vec_parity_lsbb (a);
+ return vec_vprtyb (a);
}
vector int
parity_v4si_2s (vector int a)
{
- return vec_parity_lsbb (a);
+ return vec_vprtybw (a);
}
vector unsigned int
parity_v4si_1u (vector unsigned int a)
{
- return vec_parity_lsbb (a);
+ return vec_vprtyb (a);
}
vector unsigned int
parity_v4si_2u (vector unsigned int a)
{
- return vec_parity_lsbb (a);
+ return vec_vprtybw (a);
}
vector long long
parity_v2di_1s (vector long long a)
{
- return vec_parity_lsbb (a);
+ return vec_vprtyb (a);
}
vector long long
parity_v2di_2s (vector long long a)
{
- return vec_parity_lsbb (a);
+ return vec_vprtybd (a);
}
vector unsigned long long
parity_v2di_1u (vector unsigned long long a)
{
- return vec_parity_lsbb (a);
+ return vec_vprtyb (a);
}
vector unsigned long long
parity_v2di_2u (vector unsigned long long a)
{
- return vec_parity_lsbb (a);
+ return vec_vprtybd (a);
}
vector __int128_t
parity_v1ti_1s (vector __int128_t a)
{
- return vec_parity_lsbb (a);
+ return vec_vprtyb (a);
}
vector __int128_t
parity_v1ti_2s (vector __int128_t a)
{
- return vec_parity_lsbb (a);
+ return vec_vprtybq (a);
}
__int128_t
parity_ti_3s (__int128_t a)
{
- return vec_parity_lsbb (a);
+ return vec_vprtyb (a);
}
__int128_t
parity_ti_4s (__int128_t a)
{
- return vec_parity_lsbb (a);
+ return vec_vprtybq (a);
}
vector __uint128_t
parity_v1ti_1u (vector __uint128_t a)
{
- return vec_parity_lsbb (a);
+ return vec_vprtyb (a);
}
vector __uint128_t
parity_v1ti_2u (vector __uint128_t a)
{
- return vec_parity_lsbb (a);
+ return vec_vprtybq (a);
}
__uint128_t
parity_ti_3u (__uint128_t a)
{
- return vec_parity_lsbb (a);
+ return vec_vprtyb (a);
}
__uint128_t
parity_ti_4u (__uint128_t a)
{
- return vec_parity_lsbb (a);
+ return vec_vprtybq (a);
}
/* { dg-final { scan-assembler "vprtybd" } } */
^ permalink raw reply [flat|nested] 29+ messages in thread
* [gcc(refs/users/wschmidt/heads/builtins4)] rs6000: More bug fixes
@ 2021-02-07 18:18 William Schmidt
0 siblings, 0 replies; 29+ messages in thread
From: William Schmidt @ 2021-02-07 18:18 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:1d603e60eac3b8aea4d246d7247093b9638c8fc4
commit 1d603e60eac3b8aea4d246d7247093b9638c8fc4
Author: Bill Schmidt <wschmidt@linux.ibm.com>
Date: Wed Jan 27 17:00:50 2021 -0600
rs6000: More bug fixes
2021-01-27 Bill Schmidt <wschmidt@linux.ibm.com>
gcc/
* config/rs6000/altivec.h (__builtin_vec_vaduh): Fix.
(__builtin_vec_vaduw): Fix.
* config/rs6000/rs6000-builtin-new.def: Miscellaneous fixes.
* config/rs6000/rs6000-overload.def: Miscellaneous fixes.
gcc/testsuite/
* gcc.target/powerpc/vadsdub-2.c: Remove deprecated interface.
* gcc.target/powerpc/vadsduh-2.c: Likewise.
* gcc.target/powerpc/vadsduw-2.c: Likewise.
Diff:
---
gcc/config/rs6000/altivec.h | 4 +--
gcc/config/rs6000/rs6000-builtin-new.def | 14 +++++-----
gcc/config/rs6000/rs6000-overload.def | 38 ++++++++++++++--------------
gcc/testsuite/gcc.target/powerpc/vadsdub-2.c | 2 +-
gcc/testsuite/gcc.target/powerpc/vadsduh-2.c | 2 +-
gcc/testsuite/gcc.target/powerpc/vadsduw-2.c | 2 +-
6 files changed, 31 insertions(+), 31 deletions(-)
diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h
index 1625670d24c..86464722d07 100644
--- a/gcc/config/rs6000/altivec.h
+++ b/gcc/config/rs6000/altivec.h
@@ -267,8 +267,8 @@ __altivec_scalar_pred(vec_any_nle,
/* Deprecated interfaces. */
#ifdef _ARCH_PWR9
#define __builtin_vec_vadub __builtin_vec_vadu
-#define __builtin_vec_vaduh __builtin_vec_vaduh
-#define __builtin_vec_vaduw __builtin_vec_vaduw
+#define __builtin_vec_vaduh __builtin_vec_vadu
+#define __builtin_vec_vaduw __builtin_vec_vadu
#endif
#ifdef _ARCH_PWR10
diff --git a/gcc/config/rs6000/rs6000-builtin-new.def b/gcc/config/rs6000/rs6000-builtin-new.def
index 061470d8198..417fd2a35dd 100644
--- a/gcc/config/rs6000/rs6000-builtin-new.def
+++ b/gcc/config/rs6000/rs6000-builtin-new.def
@@ -203,7 +203,7 @@
const __ibm128 __builtin_pack_ibm128 (double, double);
PACK_IF packif {}
- void __builtin_set_fpscr_rn (const int[0,7]);
+ void __builtin_set_fpscr_rn (const int[0,3]);
SET_FPSCR_RN rs6000_set_fpscr_rn {}
const double __builtin_unpack_ibm128 (__ibm128, const int<1>);
@@ -3186,22 +3186,22 @@
const unsigned long long __builtin_altivec_vgnb (vuq, const int <2,7>);
VGNB vgnb {}
- const vuc __builtin_altivec_vinsgubvlx (unsigned char, vuc, unsigned int);
+ const vuc __builtin_altivec_vinsgubvlx (unsigned int, vuc, unsigned int);
VINSERTGPRBL vinsertgl_v16qi {}
- const vuc __builtin_altivec_vinsgubvrx (unsigned char, vuc, unsigned int);
+ const vuc __builtin_altivec_vinsgubvrx (unsigned int, vuc, unsigned int);
VINSERTGPRBR vinsertgr_v16qi {}
- const vull __builtin_altivec_vinsgudvlx (unsigned long long, vull, unsigned int);
+ const vull __builtin_altivec_vinsgudvlx (unsigned int, vull, unsigned int);
VINSERTGPRDL vinsertgl_v2di {}
- const vull __builtin_altivec_vinsgudvrx (unsigned long long, vull, unsigned int);
+ const vull __builtin_altivec_vinsgudvrx (unsigned int, vull, unsigned int);
VINSERTGPRDR vinsertgr_v2di {}
- const vus __builtin_altivec_vinsguhvlx (unsigned short, vus, unsigned int);
+ const vus __builtin_altivec_vinsguhvlx (unsigned int, vus, unsigned int);
VINSERTGPRHL vinsertgl_v8hi {}
- const vus __builtin_altivec_vinsguhvrx (unsigned short, vus, unsigned int);
+ const vus __builtin_altivec_vinsguhvrx (unsigned int, vus, unsigned int);
VINSERTGPRHR vinsertgr_v8hi {}
const vui __builtin_altivec_vinsguwvlx (unsigned int, vui, unsigned int);
diff --git a/gcc/config/rs6000/rs6000-overload.def b/gcc/config/rs6000/rs6000-overload.def
index f9bf995de28..344c78b6a83 100644
--- a/gcc/config/rs6000/rs6000-overload.def
+++ b/gcc/config/rs6000/rs6000-overload.def
@@ -555,7 +555,7 @@
vuc __builtin_vec_clrl (vuc, unsigned int);
VCLRLB VCLRLB_U
-[VEC_CLRR, vec_clrr, __builtin_vec_clrr, ARCH_PWR10]
+[VEC_CLRR, vec_clrr, __builtin_vec_clrr, _ARCH_PWR10]
vsc __builtin_vec_clrr (vsc, unsigned int);
VCLRRB VCLRRB_S
vuc __builtin_vec_clrr (vuc, unsigned int);
@@ -1054,7 +1054,7 @@
[VEC_CNTTZM, vec_cnttzm, __builtin_vec_vctzdm, _ARCH_PWR10]
vull __builtin_vec_vctzdm (vull, vull);
- CNTTZDM
+ VCTZDM
[VEC_CNTLZ_LSBB, vec_cntlz_lsbb, __builtin_vec_vclzlsbb, _ARCH_PWR9]
signed int __builtin_vec_vclzlsbb (vsc);
@@ -1680,7 +1680,7 @@
XXGENPCVM_V2DI
[VEC_GNB, vec_gnb, __builtin_vec_gnb, _ARCH_PWR10]
- vull __builtin_vec_gnb (vuq, unsigned char);
+ unsigned long long __builtin_vec_gnb (vuq, const int);
VGNB
; There are no actual builtins for vec_insert. There is special handling for
@@ -2856,25 +2856,25 @@
[VEC_PERMX, vec_permx, __builtin_vec_xxpermx, _ARCH_PWR10]
vsc __builtin_vec_xxpermx (vsc, vsc, vuc, const int);
- XXPERMX_V16QI
+ XXPERMX_UV2DI XXPERMX_VSC
vuc __builtin_vec_xxpermx (vuc, vuc, vuc, const int);
- XXPERMX_UV16QI
+ XXPERMX_UV2DI XXPERMX_VUC
vss __builtin_vec_xxpermx (vss, vss, vuc, const int);
- XXPERMX_V8HI
+ XXPERMX_UV2DI XXPERMX_VSS
vus __builtin_vec_xxpermx (vus, vus, vuc, const int);
- XXPERMX_UV8HI
+ XXPERMX_UV2DI XXPERMX_VUS
vsi __builtin_vec_xxpermx (vsi, vsi, vuc, const int);
- XXPERMX_V4SI
+ XXPERMX_UV2DI XXPERMX_VSI
vui __builtin_vec_xxpermx (vui, vui, vuc, const int);
- XXPERMX_UV4SI
+ XXPERMX_UV2DI XXPERMX_VUI
vsll __builtin_vec_xxpermx (vsll, vsll, vuc, const int);
- XXPERMX_V2DI
+ XXPERMX_UV2DI XXPERMX_VSLL
vull __builtin_vec_xxpermx (vull, vull, vuc, const int);
- XXPERMX_UV2DI
+ XXPERMX_UV2DI XXPERMX_VULL
vf __builtin_vec_xxpermx (vf, vf, vuc, const int);
- XXPERMX_V4SF
+ XXPERMX_UV2DI XXPERMX_VF
vd __builtin_vec_xxpermx (vd, vd, vuc, const int);
- XXPERMX_V2DF
+ XXPERMX_UV2DI XXPERMX_VD
[VEC_PERMXOR, vec_permxor, __builtin_vec_vpermxor]
vsc __builtin_vec_vpermxor (vsc, vsc, vsc);
@@ -2917,17 +2917,17 @@
VPOPCNTUD
[VEC_PARITY_LSBB, vec_parity_lsbb, __builtin_vec_vparity_lsbb, _ARCH_PWR9]
- vsi __builtin_vec_vparity_lsbb (vsi);
+ vui __builtin_vec_vparity_lsbb (vsi);
VPRTYBW VPRTYBW_S
- vsi __builtin_vec_vparity_lsbb (vui);
+ vui __builtin_vec_vparity_lsbb (vui);
VPRTYBW VPRTYBW_U
- vsll __builtin_vec_vparity_lsbb (vsll);
+ vull __builtin_vec_vparity_lsbb (vsll);
VPRTYBD VPRTYBD_S
- vsll __builtin_vec_vparity_lsbb (vull);
+ vull __builtin_vec_vparity_lsbb (vull);
VPRTYBD VPRTYBD_U
- vsq __builtin_vec_vparity_lsbb (vsq);
+ vuq __builtin_vec_vparity_lsbb (vsq);
VPRTYBQ VPRTYBQ_S
- vsq __builtin_vec_vparity_lsbb (vuq);
+ vuq __builtin_vec_vparity_lsbb (vuq);
VPRTYBQ VPRTYBQ_U
; There are no actual builtins for vec_promote. There is special handling for
diff --git a/gcc/testsuite/gcc.target/powerpc/vadsdub-2.c b/gcc/testsuite/gcc.target/powerpc/vadsdub-2.c
index c3d1bc84ade..53e2d895d46 100644
--- a/gcc/testsuite/gcc.target/powerpc/vadsdub-2.c
+++ b/gcc/testsuite/gcc.target/powerpc/vadsdub-2.c
@@ -15,7 +15,7 @@ doAbsoluteDifferenceUnsigned (__vector unsigned char *p,
source_1 = *p;
source_2 = *q;
- uc_result = vec_absdb (source_1, source_2);
+ uc_result = vec_absd (source_1, source_2);
return uc_result;
}
diff --git a/gcc/testsuite/gcc.target/powerpc/vadsduh-2.c b/gcc/testsuite/gcc.target/powerpc/vadsduh-2.c
index 7f17694cc09..6e28e62c043 100644
--- a/gcc/testsuite/gcc.target/powerpc/vadsduh-2.c
+++ b/gcc/testsuite/gcc.target/powerpc/vadsduh-2.c
@@ -14,7 +14,7 @@ doAbsoluteDifferenceUnsignedMacro (__vector unsigned short *p,
source_1 = *p;
source_2 = *q;
- result = vec_absdh (source_1, source_2);
+ result = vec_absd (source_1, source_2);
return result;
}
diff --git a/gcc/testsuite/gcc.target/powerpc/vadsduw-2.c b/gcc/testsuite/gcc.target/powerpc/vadsduw-2.c
index a330f526c51..0a22ccd9067 100644
--- a/gcc/testsuite/gcc.target/powerpc/vadsduw-2.c
+++ b/gcc/testsuite/gcc.target/powerpc/vadsduw-2.c
@@ -14,7 +14,7 @@ doAbsoluteDifferenceUnsignedMacro (__vector unsigned int *p,
source_1 = *p;
source_2 = *q;
- result = vec_absdw (source_1, source_2);
+ result = vec_absd (source_1, source_2);
return result;
}
^ permalink raw reply [flat|nested] 29+ messages in thread
* [gcc(refs/users/wschmidt/heads/builtins4)] rs6000: More bug fixes
@ 2021-02-07 18:18 William Schmidt
0 siblings, 0 replies; 29+ messages in thread
From: William Schmidt @ 2021-02-07 18:18 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:92a82cec66309dca22b888c31a52cca8b3978061
commit 92a82cec66309dca22b888c31a52cca8b3978061
Author: Bill Schmidt <wschmidt@linux.ibm.com>
Date: Wed Jan 27 10:06:53 2021 -0600
rs6000: More bug fixes
2021-01-27 Bill Schmidt <wschmidt@linux.ibm.com>
gcc/
* config/rs6000/altivec.h: Add some deprecated interfaces.
* config/rs6000/rs6000-builtin-new.def: Miscellaneous fixes.
* config/rs6000/rs6000-c.c
(altivec_resolve_new_overloaded_builtin): Add missing break
statements.
* config/rs6000/rs6000-overload.def: Miscellaneous fixes.
* config/rs6000/rs6000.c
(rs6000_new_builtin_md_vectorized_function): Use
rs6000_gen_builtins.
gcc/testsuite/
* gcc.target/powerpc/p8vector-builtin-2.c: Adjust.
* gcc.target/powerpc/p8vector-builtin-3.c: Adjust.
* gcc.target/powerpc/p8vector-builtin-4.c: Adjust.
* gcc.target/powerpc/p8vector-builtin-8.c: Remove deprecated
builtins.
* gcc.target/powerpc/p8vector-int128-2.c: Likewise.
* gcc.target/powerpc/p8vector-vbpermq.c: Likewise.
* gcc.target/powerpc/p9-vparity.c: Likewise.
* gcc.target/powerpc/pr79544.c: Likewise.
* gcc.target/powerpc/pr80315-1.c: Adjust.
* gcc.target/powerpc/pr80315-2.c: Adjust.
* gcc.target/powerpc/pr80315-3.c: Adjust.
* gcc.target/powerpc/pr80315-4.c: Adjust.
* gcc.target/powerpc/pr88100.c: Adjust.
* gcc.target/powerpc/pragma_misc9.c: Adjust.
* gcc.target/powerpc/pragma_power9.c: Undefine
_RS6000_VECDEFINES_H before including altivec.h.
* gcc.target/powerpc/swaps-p8-46.c: Remove deprecated builtins.
* gcc.target/powerpc/test_fpscr_drn_builtin_error.c: Adjust.
* gcc.target/powerpc/test_fpscr_rn_builtin_error.c: Adjust.
Diff:
---
gcc/config/rs6000/altivec.h | 9 +++--
gcc/config/rs6000/rs6000-builtin-new.def | 10 +++---
gcc/config/rs6000/rs6000-c.c | 9 +++--
gcc/config/rs6000/rs6000-overload.def | 39 +++++++++++-----------
gcc/config/rs6000/rs6000.c | 12 +++----
.../gcc.target/powerpc/p8vector-builtin-2.c | 16 ++++-----
.../gcc.target/powerpc/p8vector-builtin-3.c | 8 ++---
.../gcc.target/powerpc/p8vector-builtin-4.c | 18 +++++-----
.../gcc.target/powerpc/p8vector-builtin-8.c | 4 +--
.../gcc.target/powerpc/p8vector-int128-1.c | 16 ++++-----
.../gcc.target/powerpc/p8vector-int128-2.c | 4 +--
.../gcc.target/powerpc/p8vector-vbpermq.c | 4 +--
gcc/testsuite/gcc.target/powerpc/p9-vparity.c | 32 +++++++++---------
gcc/testsuite/gcc.target/powerpc/pr79544.c | 8 +----
gcc/testsuite/gcc.target/powerpc/pr80315-1.c | 2 +-
gcc/testsuite/gcc.target/powerpc/pr80315-2.c | 2 +-
gcc/testsuite/gcc.target/powerpc/pr80315-3.c | 2 +-
gcc/testsuite/gcc.target/powerpc/pr80315-4.c | 2 +-
gcc/testsuite/gcc.target/powerpc/pr88100.c | 12 +++----
gcc/testsuite/gcc.target/powerpc/pragma_misc9.c | 2 +-
gcc/testsuite/gcc.target/powerpc/pragma_power9.c | 1 +
gcc/testsuite/gcc.target/powerpc/swaps-p8-46.c | 5 +--
.../powerpc/test_fpscr_drn_builtin_error.c | 4 +--
.../powerpc/test_fpscr_rn_builtin_error.c | 12 +++----
24 files changed, 117 insertions(+), 116 deletions(-)
diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h
index 13c1081cd79..1625670d24c 100644
--- a/gcc/config/rs6000/altivec.h
+++ b/gcc/config/rs6000/altivec.h
@@ -264,6 +264,13 @@ __altivec_scalar_pred(vec_any_nle,
to #define vec_step to __builtin_vec_step. */
#define vec_step(x) __builtin_vec_step (* (__typeof__ (x) *) 0)
+/* Deprecated interfaces. */
+#ifdef _ARCH_PWR9
+#define __builtin_vec_vadub __builtin_vec_vadu
+#define __builtin_vec_vaduh __builtin_vec_vaduh
+#define __builtin_vec_vaduw __builtin_vec_vaduw
+#endif
+
#ifdef _ARCH_PWR10
/* #### TODO: Deal with Carl's new builtins. */
#define vec_mulh(a, b) __builtin_vec_mulh ((a), (b))
@@ -271,6 +278,4 @@ __altivec_scalar_pred(vec_any_nle,
#define vec_mod(a, b) __builtin_vec_mod ((a), (b))
#endif
-=======
->>>>>>> rs6000: Revise altivec.h to use rs6000-vecdefines.h
#endif /* _ALTIVEC_H */
diff --git a/gcc/config/rs6000/rs6000-builtin-new.def b/gcc/config/rs6000/rs6000-builtin-new.def
index 449dcd5e257..061470d8198 100644
--- a/gcc/config/rs6000/rs6000-builtin-new.def
+++ b/gcc/config/rs6000/rs6000-builtin-new.def
@@ -203,7 +203,7 @@
const __ibm128 __builtin_pack_ibm128 (double, double);
PACK_IF packif {}
- void __builtin_set_fpscr_rn (signed long long);
+ void __builtin_set_fpscr_rn (const int[0,7]);
SET_FPSCR_RN rs6000_set_fpscr_rn {}
const double __builtin_unpack_ibm128 (__ibm128, const int<1>);
@@ -1698,7 +1698,7 @@
const vull __builtin_vsx_xvcvdpuxds (vd);
XVCVDPUXDS vsx_fixuns_truncv2dfv2di2 {}
- const vull __builtin_vsx_xvcvdpuxds_scale (vd, const int);
+ const vsll __builtin_vsx_xvcvdpuxds_scale (vd, const int);
XVCVDPUXDS_SCALE vsx_xvcvdpuxds_scale {}
; Redundant with __builtin_vsx_xvcvdpuxds
@@ -2946,7 +2946,7 @@
const _Decimal128 __builtin_pack_dec128 (unsigned long long, unsigned long long);
PACK_TD packtd {}
- void __builtin_set_fpscr_drn (signed long long);
+ void __builtin_set_fpscr_drn (const int[0,7]);
SET_FPSCR_DRN rs6000_set_fpscr_drn {}
const unsigned long long __builtin_unpack_dec128 (_Decimal128, const int<1>);
@@ -3348,13 +3348,13 @@
const vuc __builtin_vsx_xxblend_v16qi (vuc, vuc, vuc);
VXXBLEND_V16QI xxblend_v16qi {}
- const vd __builtin_vsx_xxblend_v2df (vd, vd, vull);
+ const vd __builtin_vsx_xxblend_v2df (vd, vd, vd);
VXXBLEND_V2DF xxblend_v2df {}
const vull __builtin_vsx_xxblend_v2di (vull, vull, vull);
VXXBLEND_V2DI xxblend_v2di {}
- const vf __builtin_vsx_xxblend_v4sf (vf, vf, vui);
+ const vf __builtin_vsx_xxblend_v4sf (vf, vf, vf);
VXXBLEND_V4SF xxblend_v4sf {}
const vui __builtin_vsx_xxblend_v4si (vui, vui, vui);
diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c
index a3fe6f2abc9..199e22a7c50 100644
--- a/gcc/config/rs6000/rs6000-c.c
+++ b/gcc/config/rs6000/rs6000-c.c
@@ -2247,10 +2247,9 @@ altivec_resolve_new_overloaded_builtin (location_t loc, tree fndecl,
params);
}
/* For {un}signed __int128s use the vaddeuqm/vsubeuqm instruction
- directly. This is done by the normal processing. */
+ directly. */
case E_TImode:
- {
- }
+ break;
/* Types other than {un}signed int and {un}signed __int128
are errors. */
@@ -2347,8 +2346,8 @@ altivec_resolve_new_overloaded_builtin (location_t loc, tree fndecl,
/* For {un}signed __int128s use the vaddecuq/vsubbecuq
instructions. This occurs through normal processing. */
case E_TImode:
- {
- }
+ break;
+
/* Types other than {un}signed int and {un}signed __int128
are errors. */
default:
diff --git a/gcc/config/rs6000/rs6000-overload.def b/gcc/config/rs6000/rs6000-overload.def
index f6e43b88e07..f9bf995de28 100644
--- a/gcc/config/rs6000/rs6000-overload.def
+++ b/gcc/config/rs6000/rs6000-overload.def
@@ -433,7 +433,7 @@
vui __builtin_vec_andc (vui, vui);
VANDC_V4SI_UNS VANDC_VUI
vbll __builtin_vec_andc (vbll, vbll);
- VANDC_V4SI_UNS VANDC_VBLL
+ VANDC_V2DI_UNS VANDC_VBLL
vsll __builtin_vec_andc (vsll, vsll);
VANDC_V2DI
vull __builtin_vec_andc (vull, vull);
@@ -526,7 +526,9 @@
vull __builtin_vec_vbperm_api (vuq, vuc);
VBPERMD VBPERMD_VUQ
vuc __builtin_vec_vbperm_api (vuc, vuc);
- VBPERMQ2
+ VBPERMQ2 VBPERMQ2_U
+ vsc __builtin_vec_vbperm_api (vsc, vsc);
+ VBPERMQ2 VBPERMQ2_S
; #### XVRSPIP{TARGET_VSX};VRFIP
[VEC_CEIL, vec_ceil, __builtin_vec_ceil]
@@ -2915,17 +2917,17 @@
VPOPCNTUD
[VEC_PARITY_LSBB, vec_parity_lsbb, __builtin_vec_vparity_lsbb, _ARCH_PWR9]
- vui __builtin_vec_vparity_lsbb (vsi);
+ vsi __builtin_vec_vparity_lsbb (vsi);
VPRTYBW VPRTYBW_S
- vui __builtin_vec_vparity_lsbb (vui);
+ vsi __builtin_vec_vparity_lsbb (vui);
VPRTYBW VPRTYBW_U
- vull __builtin_vec_vparity_lsbb (vsll);
+ vsll __builtin_vec_vparity_lsbb (vsll);
VPRTYBD VPRTYBD_S
- vull __builtin_vec_vparity_lsbb (vull);
+ vsll __builtin_vec_vparity_lsbb (vull);
VPRTYBD VPRTYBD_U
- vuq __builtin_vec_vparity_lsbb (vsq);
+ vsq __builtin_vec_vparity_lsbb (vsq);
VPRTYBQ VPRTYBQ_S
- vuq __builtin_vec_vparity_lsbb (vuq);
+ vsq __builtin_vec_vparity_lsbb (vuq);
VPRTYBQ VPRTYBQ_U
; There are no actual builtins for vec_promote. There is special handling for
@@ -3276,17 +3278,17 @@
vuc __builtin_vec_sldw (vuc, vuc, const int);
XXSLDWI_16QI XXSLDWI_VUC
vss __builtin_vec_sldw (vss, vss, const int);
- XXSLDWI_16QI XXSLDWI_VSS
+ XXSLDWI_8HI XXSLDWI_VSS
vus __builtin_vec_sldw (vus, vus, const int);
- XXSLDWI_16QI XXSLDWI_VUS
+ XXSLDWI_8HI XXSLDWI_VUS
vsi __builtin_vec_sldw (vsi, vsi, const int);
- XXSLDWI_16QI XXSLDWI_VSI
+ XXSLDWI_4SI XXSLDWI_VSI
vui __builtin_vec_sldw (vui, vui, const int);
- XXSLDWI_16QI XXSLDWI_VUI
+ XXSLDWI_4SI XXSLDWI_VUI
vsll __builtin_vec_sldw (vsll, vsll, const int);
- XXSLDWI_16QI XXSLDWI_VSLL
+ XXSLDWI_2DI XXSLDWI_VSLL
vull __builtin_vec_sldw (vull, vull, const int);
- XXSLDWI_16QI XXSLDWI_VULL
+ XXSLDWI_2DI XXSLDWI_VULL
[VEC_SLL, vec_sll, __builtin_vec_sll]
vsc __builtin_vec_sll (vsc, vuc);
@@ -4119,11 +4121,8 @@
VSUBCUQ VSUBCUQ_VUQ
; TODO: Note that the entry for VEC_SUBE currently gets ignored in
-; altivec_resolve_overloaded_builtin. There are also forms for
-; vsi and vui arguments, but rather than building a define_expand
-; for the instruction sequence generated for those, we do some RTL
-; hackery. Revisit whether we can remove that. For now, keep this
-; much of the entry here to generate the #define, at least.
+; altivec_resolve_overloaded_builtin. Revisit whether we can remove
+; that. We still need to register the legal builtin forms here.
[VEC_SUBE, vec_sube, __builtin_vec_sube]
vsq __builtin_vec_sube (vsq, vsq, vsq);
VSUBEUQM VSUBEUQM_VSQ
@@ -4406,6 +4405,8 @@
LXVW4X_V8HI LXVW4X_VUS
vus __builtin_vec_vsx_ld (signed long long, const unsigned short *);
LXVW4X_V8HI LXVW4X_US
+ vp __builtin_vec_vsx_ld (signed long long, const vp *);
+ LXVW4X_V8HI LXVW4X_P
vsi __builtin_vec_vsx_ld (signed long long, const vsi *);
LXVW4X_V4SI LXVW4X_VSI
vsi __builtin_vec_vsx_ld (signed long long, const signed int *);
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index fb512fd9f0f..cda871a11ca 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -5583,29 +5583,29 @@ rs6000_new_builtin_md_vectorized_function (tree fndecl, tree type_out,
in_mode = TYPE_MODE (TREE_TYPE (type_in));
in_n = TYPE_VECTOR_SUBPARTS (type_in);
- enum rs6000_builtins fn
- = (enum rs6000_builtins) DECL_MD_FUNCTION_CODE (fndecl);
+ enum rs6000_gen_builtins fn
+ = (enum rs6000_gen_builtins) DECL_MD_FUNCTION_CODE (fndecl);
switch (fn)
{
- case RS6000_BUILTIN_RSQRTF:
+ case RS6000_BIF_RSQRTF:
if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
&& out_mode == SFmode && out_n == 4
&& in_mode == SFmode && in_n == 4)
return rs6000_builtin_decls_x[RS6000_BIF_VRSQRTFP];
break;
- case RS6000_BUILTIN_RSQRT:
+ case RS6000_BIF_RSQRT:
if (VECTOR_UNIT_VSX_P (V2DFmode)
&& out_mode == DFmode && out_n == 2
&& in_mode == DFmode && in_n == 2)
return rs6000_builtin_decls_x[RS6000_BIF_RSQRT_2DF];
break;
- case RS6000_BUILTIN_RECIPF:
+ case RS6000_BIF_RECIPF:
if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
&& out_mode == SFmode && out_n == 4
&& in_mode == SFmode && in_n == 4)
return rs6000_builtin_decls_x[RS6000_BIF_VRECIPFP];
break;
- case RS6000_BUILTIN_RECIP:
+ case RS6000_BIF_RECIP:
if (VECTOR_UNIT_VSX_P (V2DFmode)
&& out_mode == DFmode && out_n == 2
&& in_mode == DFmode && in_n == 2)
diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c
index 0259e364aa6..a1f4e4e9a4e 100644
--- a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c
+++ b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c
@@ -214,17 +214,17 @@ v_bshort vbshort_ne (v_bshort a, v_bshort b)
}
-/* { dg-final { scan-assembler-times "vaddudm" 5 } } */
-/* { dg-final { scan-assembler-times "vsubudm" 6 } } */
-/* { dg-final { scan-assembler-times "vmaxsd" 4 } } */
-/* { dg-final { scan-assembler-times "vminsd" 3 } } */
-/* { dg-final { scan-assembler-times "vmaxud" 2 } } */
-/* { dg-final { scan-assembler-times "vminud" 2 } } */
+/* { dg-final { scan-assembler-times "vaddudm" 3 } } */
+/* { dg-final { scan-assembler-times "vsubudm" 4 } } */
+/* { dg-final { scan-assembler-times "vmaxsd" 3 } } */
+/* { dg-final { scan-assembler-times "vminsd" 2 } } */
+/* { dg-final { scan-assembler-times "vmaxud" 1 } } */
+/* { dg-final { scan-assembler-times "vminud" 1 } } */
/* { dg-final { scan-assembler-times "vcmpequd" 6 } } */
/* { dg-final { scan-assembler-times "vcmpgtsd" 1 } } */
/* { dg-final { scan-assembler-times "vcmpgtud" 1 } } */
/* { dg-final { scan-assembler-times "vrld" 3 } } */
-/* { dg-final { scan-assembler-times "vsld" 5 } } */
-/* { dg-final { scan-assembler-times "vsrad" 3 } } */
+/* { dg-final { scan-assembler-times "vsld" 3 } } */
+/* { dg-final { scan-assembler-times "vsrad" 2 } } */
/* { dg-final { scan-assembler-times "vcmpequb" 3 } } */
/* { dg-final { scan-assembler-times "vcmpequw" 6 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-3.c b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-3.c
index ae6a3a8437b..0b038edfafe 100644
--- a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-3.c
@@ -77,8 +77,8 @@ vll_sign vll_unpack_lo_2 (vi_sign a)
return vec_unpackl (a);
}
-/* { dg-final { scan-assembler-times "vpkudum" 4 } } */
-/* { dg-final { scan-assembler-times "vpkuwum" 3 } } */
-/* { dg-final { scan-assembler-times "vpkuhum" 3 } } */
+/* { dg-final { scan-assembler-times "vpkudum" 3 } } */
+/* { dg-final { scan-assembler-times "vpkuwum" 2 } } */
+/* { dg-final { scan-assembler-times "vpkuhum" 2 } } */
/* { dg-final { scan-assembler-times "vupklsw" 3 } } */
-/* { dg-final { scan-assembler-times "vupkhsw" 3 } } */
+/* { dg-final { scan-assembler-times "vupkhsw" 1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-4.c b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-4.c
index 2d2d141948f..e814c648843 100644
--- a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-4.c
+++ b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-4.c
@@ -156,14 +156,14 @@ vc_uns vc_gbb_3 (vc_uns a)
return vec_gb (a);
}
-/* { dg-final { scan-assembler-times "vclzd" 5 } } */
-/* { dg-final { scan-assembler-times "vclzw" 5 } } */
-/* { dg-final { scan-assembler-times "vclzh" 5 } } */
-/* { dg-final { scan-assembler-times "vclzb" 5 } } */
-
-/* { dg-final { scan-assembler-times "vpopcntd" 5 } } */
-/* { dg-final { scan-assembler-times "vpopcntw" 5 } } */
-/* { dg-final { scan-assembler-times "vpopcnth" 5 } } */
-/* { dg-final { scan-assembler-times "vpopcntb" 5 } } */
+/* { dg-final { scan-assembler-times "vclzd" 3 } } */
+/* { dg-final { scan-assembler-times "vclzw" 3 } } */
+/* { dg-final { scan-assembler-times "vclzh" 3 } } */
+/* { dg-final { scan-assembler-times "vclzb" 3 } } */
+
+/* { dg-final { scan-assembler-times "vpopcntd" 3 } } */
+/* { dg-final { scan-assembler-times "vpopcntw" 3 } } */
+/* { dg-final { scan-assembler-times "vpopcnth" 3 } } */
+/* { dg-final { scan-assembler-times "vpopcntb" 3 } } */
/* { dg-final { scan-assembler-times "vgbbd" 3 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-8.c b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-8.c
index 0cfbe68c3a4..b5c81ab1ace 100644
--- a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-8.c
+++ b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-8.c
@@ -112,7 +112,6 @@ void foo (vector signed char *vscr,
*vsir++ = vec_sum4s (vsca, vsib);
*vsir++ = vec_sum4s (vssa, vsib);
*vuir++ = vec_sum4s (vuca, vuib);
-
}
/* { dg-final { scan-assembler-times "vaddcuq" 2 } } */
@@ -125,7 +124,8 @@ void foo (vector signed char *vscr,
/* { dg-final { scan-assembler-times "vsubecuq" 2 } } */
/* { dg-final { scan-assembler-times "vsubcuw" 4 } } */
/* { dg-final { scan-assembler-times "vsubuwm" 4 } } */
-/* { dg-final { scan-assembler-times "vbpermq" 2 } } */
+/* { dg-final { scan-assembler-times "vbpermq" 1 } } */
+/* { dg-final { scan-assembler-times "vbpermd" 1 } } */
/* { dg-final { scan-assembler-times "xxleqv" 4 } } */
/* { dg-final { scan-assembler-times "vgbbd" 1 } } */
/* { dg-final { scan-assembler-times "xxlnand" 4 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-int128-1.c b/gcc/testsuite/gcc.target/powerpc/p8vector-int128-1.c
index 28b148c692c..8a7484b7144 100644
--- a/gcc/testsuite/gcc.target/powerpc/p8vector-int128-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/p8vector-int128-1.c
@@ -13,49 +13,49 @@
TYPE
do_addcuq (TYPE p, TYPE q)
{
- return __builtin_vec_vaddcuq (p, q);
+ return vec_addc (p, q);
}
TYPE
do_adduqm (TYPE p, TYPE q)
{
- return __builtin_vec_add (p, q);
+ return vec_add (p, q);
}
TYPE
do_addeuqm (TYPE p, TYPE q, TYPE r)
{
- return __builtin_vec_vaddeuqm (p, q, r);
+ return vec_adde (p, q, r);
}
TYPE
do_addecuq (TYPE p, TYPE q, TYPE r)
{
- return __builtin_vec_vaddecuq (p, q, r);
+ return vec_addec (p, q, r);
}
TYPE
do_subeuqm (TYPE p, TYPE q, TYPE r)
{
- return __builtin_vec_vsubeuqm (p, q, r);
+ return vec_sube (p, q, r);
}
TYPE
do_subecuq (TYPE p, TYPE q, TYPE r)
{
- return __builtin_vec_vsubecuq (p, q, r);
+ return vec_subec (p, q, r);
}
TYPE
do_subcuq (TYPE p, TYPE q)
{
- return __builtin_vec_vsubcuq (p, q);
+ return vec_subc (p, q);
}
TYPE
do_subuqm (TYPE p, TYPE q)
{
- return __builtin_vec_vsubuqm (p, q);
+ return vec_sub (p, q);
}
TYPE
diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-int128-2.c b/gcc/testsuite/gcc.target/powerpc/p8vector-int128-2.c
index 72358d616b1..cdeebb36342 100644
--- a/gcc/testsuite/gcc.target/powerpc/p8vector-int128-2.c
+++ b/gcc/testsuite/gcc.target/powerpc/p8vector-int128-2.c
@@ -132,7 +132,7 @@ main (void)
v_reg_in1 = (V_TYPE) { s_reg_in1 };
v_reg_in2 = (V_TYPE) { s_reg_in2 };
- v_reg_res = vec_vadduqm (v_reg_in1, v_reg_in2);
+ v_reg_res = vec_add (v_reg_in1, v_reg_in2);
reg_errors += compare (s_reg_res, v_reg_res, "", "reg, res");
s_mem_in1 = s_reg_in1;
@@ -144,7 +144,7 @@ main (void)
mem_errors += compare (s_mem_in2, (V_TYPE) { s_mem_in2 }, "", "mem, in2");
s_mem_res = s_mem_in1 + s_mem_in2;
- v_mem_res = vec_vadduqm (v_mem_in1, v_mem_in2);
+ v_mem_res = vec_add (v_mem_in1, v_mem_in2);
mem_errors += compare (s_mem_res, v_mem_res, "", "mem, res");
nl = "\n";
diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-vbpermq.c b/gcc/testsuite/gcc.target/powerpc/p8vector-vbpermq.c
index c2ab68ba761..e5601b13b3a 100644
--- a/gcc/testsuite/gcc.target/powerpc/p8vector-vbpermq.c
+++ b/gcc/testsuite/gcc.target/powerpc/p8vector-vbpermq.c
@@ -17,11 +17,11 @@
long foos (vector signed char a, vector signed char b)
{
- return vec_extract (vec_vbpermq (a, b), OFFSET);
+ return vec_extract (vec_bperm (a, b), OFFSET);
}
long foou (vector unsigned char a, vector unsigned char b)
{
- return vec_extract (vec_vbpermq (a, b), OFFSET);
+ return vec_extract (vec_bperm (a, b), OFFSET);
}
diff --git a/gcc/testsuite/gcc.target/powerpc/p9-vparity.c b/gcc/testsuite/gcc.target/powerpc/p9-vparity.c
index f4aba1567cd..8897a5b6b7f 100644
--- a/gcc/testsuite/gcc.target/powerpc/p9-vparity.c
+++ b/gcc/testsuite/gcc.target/powerpc/p9-vparity.c
@@ -9,97 +9,97 @@
vector int
parity_v4si_1s (vector int a)
{
- return vec_vprtyb (a);
+ return vec_parity_lsbb (a);
}
vector int
parity_v4si_2s (vector int a)
{
- return vec_vprtybw (a);
+ return vec_parity_lsbb (a);
}
vector unsigned int
parity_v4si_1u (vector unsigned int a)
{
- return vec_vprtyb (a);
+ return vec_parity_lsbb (a);
}
vector unsigned int
parity_v4si_2u (vector unsigned int a)
{
- return vec_vprtybw (a);
+ return vec_parity_lsbb (a);
}
vector long long
parity_v2di_1s (vector long long a)
{
- return vec_vprtyb (a);
+ return vec_parity_lsbb (a);
}
vector long long
parity_v2di_2s (vector long long a)
{
- return vec_vprtybd (a);
+ return vec_parity_lsbb (a);
}
vector unsigned long long
parity_v2di_1u (vector unsigned long long a)
{
- return vec_vprtyb (a);
+ return vec_parity_lsbb (a);
}
vector unsigned long long
parity_v2di_2u (vector unsigned long long a)
{
- return vec_vprtybd (a);
+ return vec_parity_lsbb (a);
}
vector __int128_t
parity_v1ti_1s (vector __int128_t a)
{
- return vec_vprtyb (a);
+ return vec_parity_lsbb (a);
}
vector __int128_t
parity_v1ti_2s (vector __int128_t a)
{
- return vec_vprtybq (a);
+ return vec_parity_lsbb (a);
}
__int128_t
parity_ti_3s (__int128_t a)
{
- return vec_vprtyb (a);
+ return vec_parity_lsbb (a);
}
__int128_t
parity_ti_4s (__int128_t a)
{
- return vec_vprtybq (a);
+ return vec_parity_lsbb (a);
}
vector __uint128_t
parity_v1ti_1u (vector __uint128_t a)
{
- return vec_vprtyb (a);
+ return vec_parity_lsbb (a);
}
vector __uint128_t
parity_v1ti_2u (vector __uint128_t a)
{
- return vec_vprtybq (a);
+ return vec_parity_lsbb (a);
}
__uint128_t
parity_ti_3u (__uint128_t a)
{
- return vec_vprtyb (a);
+ return vec_parity_lsbb (a);
}
__uint128_t
parity_ti_4u (__uint128_t a)
{
- return vec_vprtybq (a);
+ return vec_parity_lsbb (a);
}
/* { dg-final { scan-assembler "vprtybd" } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/pr79544.c b/gcc/testsuite/gcc.target/powerpc/pr79544.c
index 3f782489bbd..ecdbbcc67bd 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr79544.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr79544.c
@@ -10,11 +10,5 @@ test_sra (vector unsigned long long x, vector unsigned long long y)
return vec_sra (x, y);
}
-vector unsigned long long
-test_vsrad (vector unsigned long long x, vector unsigned long long y)
-{
- return vec_vsrad (x, y);
-}
-
-/* { dg-final { scan-assembler-times {\mvsrad\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mvsrad\M} 1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/pr80315-1.c b/gcc/testsuite/gcc.target/powerpc/pr80315-1.c
index e2db0ff4b5f..f37f1f169a2 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr80315-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr80315-1.c
@@ -10,6 +10,6 @@ main()
int mask;
/* Argument 2 must be 0 or 1. Argument 3 must be in range 0..15. */
- res = __builtin_crypto_vshasigmaw (test, 1, 0xff); /* { dg-error {argument 3 must be in the range \[0, 15\]} } */
+ res = __builtin_crypto_vshasigmaw (test, 1, 0xff); /* { dg-error {argument 3 must be a 4-bit unsigned literal} } */
return 0;
}
diff --git a/gcc/testsuite/gcc.target/powerpc/pr80315-2.c b/gcc/testsuite/gcc.target/powerpc/pr80315-2.c
index 144b705c012..0819a0511b7 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr80315-2.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr80315-2.c
@@ -10,6 +10,6 @@ main ()
int mask;
/* Argument 2 must be 0 or 1. Argument 3 must be in range 0..15. */
- res = __builtin_crypto_vshasigmad (test, 1, 0xff); /* { dg-error {argument 3 must be in the range \[0, 15\]} } */
+ res = __builtin_crypto_vshasigmad (test, 1, 0xff); /* { dg-error {argument 3 must be a 4-bit unsigned literal} } */
return 0;
}
diff --git a/gcc/testsuite/gcc.target/powerpc/pr80315-3.c b/gcc/testsuite/gcc.target/powerpc/pr80315-3.c
index 99a3e24eadd..cc2e46cf5cb 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr80315-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr80315-3.c
@@ -12,6 +12,6 @@ main ()
int mask;
/* Argument 2 must be 0 or 1. Argument 3 must be in range 0..15. */
- res = vec_shasigma_be (test, 1, 0xff); /* { dg-error {argument 3 must be in the range \[0, 15\]} } */
+ res = vec_shasigma_be (test, 1, 0xff); /* { dg-error {argument 3 must be a 4-bit unsigned literal} } */
return res;
}
diff --git a/gcc/testsuite/gcc.target/powerpc/pr80315-4.c b/gcc/testsuite/gcc.target/powerpc/pr80315-4.c
index 7f5f6f75029..ac12910741b 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr80315-4.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr80315-4.c
@@ -12,6 +12,6 @@ main ()
int mask;
/* Argument 2 must be 0 or 1. Argument 3 must be in range 0..15. */
- res = vec_shasigma_be (test, 1, 0xff); /* { dg-error {argument 3 must be in the range \[0, 15\]} } */
+ res = vec_shasigma_be (test, 1, 0xff); /* { dg-error {argument 3 must be a 4-bit unsigned literal} } */
return res;
}
diff --git a/gcc/testsuite/gcc.target/powerpc/pr88100.c b/gcc/testsuite/gcc.target/powerpc/pr88100.c
index 4452145ce95..764c897a497 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr88100.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr88100.c
@@ -10,35 +10,35 @@
vector unsigned char
splatu1 (void)
{
- return vec_splat_u8(0x100);/* { dg-error "argument 1 must be a 5-bit signed literal" } */
+ return vec_splat_u8(0x100);/* { dg-error "argument 1 must be a literal between -16 and 15, inclusive" } */
}
vector unsigned short
splatu2 (void)
{
- return vec_splat_u16(0x10000);/* { dg-error "argument 1 must be a 5-bit signed literal" } */
+ return vec_splat_u16(0x10000);/* { dg-error "argument 1 must be a literal between -16 and 15, inclusive" } */
}
vector unsigned int
splatu3 (void)
{
- return vec_splat_u32(0x10000000);/* { dg-error "argument 1 must be a 5-bit signed literal" } */
+ return vec_splat_u32(0x10000000);/* { dg-error "argument 1 must be a literal between -16 and 15, inclusive" } */
}
vector signed char
splats1 (void)
{
- return vec_splat_s8(0x100);/* { dg-error "argument 1 must be a 5-bit signed literal" } */
+ return vec_splat_s8(0x100);/* { dg-error "argument 1 must be a literal between -16 and 15, inclusive" } */
}
vector signed short
splats2 (void)
{
- return vec_splat_s16(0x10000);/* { dg-error "argument 1 must be a 5-bit signed literal" } */
+ return vec_splat_s16(0x10000);/* { dg-error "argument 1 must be a literal between -16 and 15, inclusive" } */
}
vector signed int
splats3 (void)
{
- return vec_splat_s32(0x10000000);/* { dg-error "argument 1 must be a 5-bit signed literal" } */
+ return vec_splat_s32(0x10000000);/* { dg-error "argument 1 must be a literal between -16 and 15, inclusive" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/pragma_misc9.c b/gcc/testsuite/gcc.target/powerpc/pragma_misc9.c
index e03099bd084..61274463653 100644
--- a/gcc/testsuite/gcc.target/powerpc/pragma_misc9.c
+++ b/gcc/testsuite/gcc.target/powerpc/pragma_misc9.c
@@ -20,7 +20,7 @@ vector bool int
test2 (vector signed int a, vector signed int b)
{
return vec_cmpnez (a, b);
- /* { dg-error "'__builtin_altivec_vcmpnezw' requires the '-mcpu=power9' option" "" { target *-*-* } .-1 } */
+ /* { dg-error "'__builtin_altivec_vcmpnezw' requires the '-mpower9-vector' option" "" { target *-*-* } .-1 } */
}
#pragma GCC target ("cpu=power7")
diff --git a/gcc/testsuite/gcc.target/powerpc/pragma_power9.c b/gcc/testsuite/gcc.target/powerpc/pragma_power9.c
index e33aad1aaf7..5327c8c8cc8 100644
--- a/gcc/testsuite/gcc.target/powerpc/pragma_power9.c
+++ b/gcc/testsuite/gcc.target/powerpc/pragma_power9.c
@@ -50,6 +50,7 @@ test3b (vec_t a, vec_t b)
#pragma GCC target ("cpu=power9,power9-vector")
#undef _ALTIVEC_H
+#undef _RS6000_VECDEFINES_H
#include <altivec.h>
#ifdef _ARCH_PWR9
vector bool int
diff --git a/gcc/testsuite/gcc.target/powerpc/swaps-p8-46.c b/gcc/testsuite/gcc.target/powerpc/swaps-p8-46.c
index 4738d5e0139..3911ac9e713 100644
--- a/gcc/testsuite/gcc.target/powerpc/swaps-p8-46.c
+++ b/gcc/testsuite/gcc.target/powerpc/swaps-p8-46.c
@@ -2,6 +2,7 @@
/* { dg-require-effective-target powerpc_p8vector_ok } */
/* { dg-options "-mdejagnu-cpu=power8 -O2 " } */
+#include <altivec.h>
typedef __attribute__ ((__aligned__ (8))) unsigned long long __m64;
typedef float __m128 __attribute__ ((__vector_size__ (16), __may_alias__));
@@ -17,8 +18,8 @@ _mm_movemask_ps (__m128 *__A)
};
result = (__vector __m64)
- __builtin_vec_vbpermq ((__vector unsigned char) (*__A),
- (__vector unsigned char) perm_mask);
+ vec_bperm ((__vector unsigned char) (*__A),
+ (__vector unsigned char) perm_mask);
return result[1];
}
diff --git a/gcc/testsuite/gcc.target/powerpc/test_fpscr_drn_builtin_error.c b/gcc/testsuite/gcc.target/powerpc/test_fpscr_drn_builtin_error.c
index 028ab0b6d66..4f9d9e08e8a 100644
--- a/gcc/testsuite/gcc.target/powerpc/test_fpscr_drn_builtin_error.c
+++ b/gcc/testsuite/gcc.target/powerpc/test_fpscr_drn_builtin_error.c
@@ -9,8 +9,8 @@ int main ()
__builtin_set_fpscr_drn() also support a variable as an argument but
can't test variable value at compile time. */
- __builtin_set_fpscr_drn(-1); /* { dg-error "Argument must be a value between 0 and 7" } */
- __builtin_set_fpscr_drn(8); /* { dg-error "Argument must be a value between 0 and 7" } */
+ __builtin_set_fpscr_drn(-1); /* { dg-error "argument 1 must be a variable or a literal between 0 and 7, inclusive" } */
+ __builtin_set_fpscr_drn(8); /* { dg-error "argument 1 must be a variable or a literal between 0 and 7, inclusive" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/test_fpscr_rn_builtin_error.c b/gcc/testsuite/gcc.target/powerpc/test_fpscr_rn_builtin_error.c
index aea65091b0c..10391b71008 100644
--- a/gcc/testsuite/gcc.target/powerpc/test_fpscr_rn_builtin_error.c
+++ b/gcc/testsuite/gcc.target/powerpc/test_fpscr_rn_builtin_error.c
@@ -8,13 +8,13 @@ int main ()
int arguments. The builtins __builtin_set_fpscr_rn() also supports a
variable as an argument but can't test variable value at compile time. */
- __builtin_mtfsb0(-1); /* { dg-error "Argument must be a constant between 0 and 31" } */
- __builtin_mtfsb0(32); /* { dg-error "Argument must be a constant between 0 and 31" } */
+ __builtin_mtfsb0(-1); /* { dg-error "argument 1 must be a 5-bit unsigned literal" } */
+ __builtin_mtfsb0(32); /* { dg-error "argument 1 must be a 5-bit unsigned literal" } */
- __builtin_mtfsb1(-1); /* { dg-error "Argument must be a constant between 0 and 31" } */
- __builtin_mtfsb1(32); /* { dg-error "Argument must be a constant between 0 and 31" } */
+ __builtin_mtfsb1(-1); /* { dg-error "argument 1 must be a 5-bit unsigned literal" } */
+ __builtin_mtfsb1(32); /* { dg-error "argument 1 must be a 5-bit unsigned literal" } */
- __builtin_set_fpscr_rn(-1); /* { dg-error "Argument must be a value between 0 and 3" } */
- __builtin_set_fpscr_rn(4); /* { dg-error "Argument must be a value between 0 and 3" } */
+ __builtin_set_fpscr_rn(-1); /* { dg-error "argument 1 must be a variable or a literal between 0 and 3, inclusive" } */
+ __builtin_set_fpscr_rn(4); /* { dg-error "argument 1 must be a variable or a literal between 0 and 3, inclusive" } */
}
^ permalink raw reply [flat|nested] 29+ messages in thread
* [gcc(refs/users/wschmidt/heads/builtins4)] rs6000: More bug fixes
@ 2021-02-07 18:18 William Schmidt
0 siblings, 0 replies; 29+ messages in thread
From: William Schmidt @ 2021-02-07 18:18 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:fe662739412e4c690cdddea8d75d07eac8e006e7
commit fe662739412e4c690cdddea8d75d07eac8e006e7
Author: Bill Schmidt <wschmidt@linux.ibm.com>
Date: Thu Jan 14 17:06:55 2021 -0600
rs6000: More bug fixes
2021-01-14 Bill Schmidt <wschmidt@linux.ibm.com>
gcc/
* config/rs6000/rs6000-builtin-new.def: Assorted fixes.
* config/rs6000/rs6000-overload.def: Assorted fixes.
gcc/testsuite/
* gcc.target/powerpc/altivec-7.c: Adjust.
* gcc.target/powerpc/cmpb-2.c: Adjust.
* gcc.target/powerpc/cmpb32-2.c: Adjust.
* gcc.target/powerpc/fold-vec-mule-misc.c: Adjust.
* gcc.target/powerpc/fold-vec-splat-floatdouble.c: Adjust.
* gcc.target/powerpc/fold-vec-splat-longlong.c: Adjust.
* gcc.target/powerpc/fold-vec-splat-misc-invalid.c: Adjust.
* gcc.target/powerpc/p8vector-builtin-2.c: Adjust.
* gcc.target/powerpc/p8vector-builtin-3.c: Adjust.
* gcc.target/powerpc/p8vector-builtin-4.c: Adjust.
* gcc.target/powerpc/p8vector-builtin-7.c: Adjust.
Diff:
---
gcc/config/rs6000/altivec.h | 2 +
gcc/config/rs6000/rs6000-builtin-new.def | 24 ++--
gcc/config/rs6000/rs6000-overload.def | 11 +-
gcc/testsuite/gcc.target/powerpc/altivec-7.c | 2 +-
gcc/testsuite/gcc.target/powerpc/cmpb-2.c | 2 +-
gcc/testsuite/gcc.target/powerpc/cmpb32-2.c | 2 +-
.../gcc.target/powerpc/fold-vec-mule-misc.c | 8 +-
.../powerpc/fold-vec-splat-floatdouble.c | 4 +-
.../gcc.target/powerpc/fold-vec-splat-longlong.c | 10 +-
.../powerpc/fold-vec-splat-misc-invalid.c | 8 +-
.../gcc.target/powerpc/p8vector-builtin-2.c | 55 ---------
.../gcc.target/powerpc/p8vector-builtin-3.c | 27 +----
.../gcc.target/powerpc/p8vector-builtin-4.c | 124 ++++-----------------
.../gcc.target/powerpc/p8vector-builtin-7.c | 8 +-
14 files changed, 61 insertions(+), 226 deletions(-)
diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h
index 76432d545c4..13c1081cd79 100644
--- a/gcc/config/rs6000/altivec.h
+++ b/gcc/config/rs6000/altivec.h
@@ -66,6 +66,8 @@
/* VSX additions */
#define vec_vsx_ld __builtin_vec_vsx_ld
#define vec_vsx_st __builtin_vec_vsx_st
+#define __builtin_vec_xl __builtin_vec_vsx_ld
+#define __builtin_vec_xst __builtin_vec_vsx_st
#define __builtin_bcdadd_ofl __builtin_vec_bcdadd_ov
#define __builtin_bcdsub_ofl __builtin_vec_bcdsub_ov
diff --git a/gcc/config/rs6000/rs6000-builtin-new.def b/gcc/config/rs6000/rs6000-builtin-new.def
index 9c4470bf400..449dcd5e257 100644
--- a/gcc/config/rs6000/rs6000-builtin-new.def
+++ b/gcc/config/rs6000/rs6000-builtin-new.def
@@ -805,13 +805,13 @@
const vus __builtin_altivec_vpkswus (vsi, vsi);
VPKSWUS altivec_vpkswus {}
- const vuc __builtin_altivec_vpkuhum (vus, vus);
+ const vsc __builtin_altivec_vpkuhum (vss, vss);
VPKUHUM altivec_vpkuhum {}
const vuc __builtin_altivec_vpkuhus (vus, vus);
VPKUHUS altivec_vpkuhus {}
- const vus __builtin_altivec_vpkuwum (vui, vui);
+ const vss __builtin_altivec_vpkuwum (vsi, vsi);
VPKUWUM altivec_vpkuwum {}
const vus __builtin_altivec_vpkuwus (vui, vui);
@@ -1219,7 +1219,7 @@
const vsll __builtin_altivec_vreve_v2di (vsll);
VREVE_V2DI altivec_vrevev2di2 {}
- const vd __builtin_altivec_vsel_2df (vd, vd, vull);
+ const vd __builtin_altivec_vsel_2df (vd, vd, vd);
VSEL_2DF vector_select_v2df {}
const vsll __builtin_altivec_vsel_2di (vsll, vsll, vull);
@@ -2263,7 +2263,7 @@
const vui __builtin_altivec_vpksdus (vsll, vsll);
VPKSDUS altivec_vpksdus {}
- const vui __builtin_altivec_vpkudum (vull, vull);
+ const vsi __builtin_altivec_vpkudum (vsll, vsll);
VPKUDUM altivec_vpkudum {}
const vui __builtin_altivec_vpkudus (vull, vull);
@@ -2285,13 +2285,13 @@
; const vull __builtin_altivec_vpmsumw (vui, vui);
; VPMSUMW crypto_vpmsumw {}
- const vuc __builtin_altivec_vpopcntb (vsc);
+ const vsc __builtin_altivec_vpopcntb (vsc);
VPOPCNTB popcountv16qi2 {}
- const vull __builtin_altivec_vpopcntd (vsll);
+ const vsll __builtin_altivec_vpopcntd (vsll);
VPOPCNTD popcountv2di2 {}
- const vus __builtin_altivec_vpopcnth (vss);
+ const vss __builtin_altivec_vpopcnth (vss);
VPOPCNTH popcountv8hi2 {}
const vuc __builtin_altivec_vpopcntub (vuc);
@@ -2306,16 +2306,16 @@
const vui __builtin_altivec_vpopcntuw (vui);
VPOPCNTUW popcountv4si2 {}
- const vui __builtin_altivec_vpopcntw (vsi);
+ const vsi __builtin_altivec_vpopcntw (vsi);
VPOPCNTW popcountv4si2 {}
- const vsll __builtin_altivec_vrld (vsll, vull);
+ const vsll __builtin_altivec_vrld (vsll, vsll);
VRLD vrotlv2di3 {}
- const vsll __builtin_altivec_vsld (vsll, vull);
+ const vsll __builtin_altivec_vsld (vsll, vsll);
VSLD vashlv2di3 {}
- const vsll __builtin_altivec_vsrad (vsll, vull);
+ const vsll __builtin_altivec_vsrad (vsll, vsll);
VSRAD vashrv2di3 {}
const vsll __builtin_altivec_vsrd (vsll, vull);
@@ -2330,7 +2330,7 @@
const vuq __builtin_altivec_vsubeuqm (vuq, vuq, vuq);
VSUBEUQM altivec_vsubeuqm {}
- const vull __builtin_altivec_vsubudm (vull, vull);
+ const vsll __builtin_altivec_vsubudm (vsll, vsll);
VSUBUDM subv2di3 {}
const vuq __builtin_altivec_vsubuqm (vuq, vuq);
diff --git a/gcc/config/rs6000/rs6000-overload.def b/gcc/config/rs6000/rs6000-overload.def
index e80e163f8ec..f6e43b88e07 100644
--- a/gcc/config/rs6000/rs6000-overload.def
+++ b/gcc/config/rs6000/rs6000-overload.def
@@ -3830,7 +3830,7 @@
void __builtin_vec_stl (vd, signed long long, double *);
STVXL_V2DF STVXL_D
-[VEC_STRIL, vec_stril, __builtin_vec_stril, ARCH_PWR10]
+[VEC_STRIL, vec_stril, __builtin_vec_stril, _ARCH_PWR10]
vuc __builtin_vec_stril (vuc);
VSTRIBL VSTRIBL_U
vsc __builtin_vec_stril (vsc);
@@ -3860,7 +3860,7 @@
vss __builtin_vec_strir (vss);
VSTRIHR VSTRIHR_S
-[VEC_STRIR_P, vec_strir_p, __builtin_vec_strir_p, ARCH_PWR10]
+[VEC_STRIR_P, vec_strir_p, __builtin_vec_strir_p, _ARCH_PWR10]
signed int __builtin_vec_strir_p (vuc);
VSTRIBR_P VSTRIBR_PU
signed int __builtin_vec_strir_p (vsc);
@@ -4131,11 +4131,8 @@
VSUBEUQM VSUBEUQM_VUQ
; TODO: Note that the entry for VEC_SUBEC currently gets ignored in
-; altivec_resolve_overloaded_builtin. There are also forms for
-; vsi and vui arguments, but rather than building a define_expand
-; for the instruction sequence generated for those, we do some RTL
-; hackery. Revisit whether we can remove that. For now, keep this
-; much of the entry here to generate the #define, at least.
+; altivec_resolve_overloaded_builtin. Revisit whether we can remove
+; that. We still need to register the legal builtin forms here.
[VEC_SUBEC, vec_subec, __builtin_vec_subec]
vsq __builtin_vec_subec (vsq, vsq, vsq);
VSUBECUQ VSUBECUQ_VSQ
diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-7.c b/gcc/testsuite/gcc.target/powerpc/altivec-7.c
index 46bf7148b20..52f5ecc8d59 100644
--- a/gcc/testsuite/gcc.target/powerpc/altivec-7.c
+++ b/gcc/testsuite/gcc.target/powerpc/altivec-7.c
@@ -84,7 +84,7 @@ int main ()
/* { dg-final { scan-assembler-times {\mlvx\M} 39 { target { ! powerpc_vsx } } } } */
/* { dg-final { scan-assembler-times {\mlxv} 0 { target { ! powerpc_vsx } } } } */
/* { dg-final { scan-assembler-times {\mlvx\M} 0 { target powerpc_vsx } } } */
-/* { dg-final { scan-assembler-times {\mlxv} 42 { target powerpc_vsx } } } */
+/* { dg-final { scan-assembler-times {\mlxv} 39 { target powerpc_vsx } } } */
/* { dg-final { scan-assembler-times "lvewx" 1 } } */
/* { dg-final { scan-assembler-times "lvxl" 1 } } */
/* { dg-final { scan-assembler-times "vupklsh" 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/cmpb-2.c b/gcc/testsuite/gcc.target/powerpc/cmpb-2.c
index 113ab6a5f99..02b84d0731d 100644
--- a/gcc/testsuite/gcc.target/powerpc/cmpb-2.c
+++ b/gcc/testsuite/gcc.target/powerpc/cmpb-2.c
@@ -8,7 +8,7 @@ void abort ();
unsigned long long int
do_compare (unsigned long long int a, unsigned long long int b)
{
- return __builtin_cmpb (a, b); /* { dg-warning "implicit declaration of function '__builtin_cmpb'" } */
+ return __builtin_cmpb (a, b); /* { dg-error "'__builtin_p6_cmpb' requires the '-mcpu=power6' option" } */
}
void
diff --git a/gcc/testsuite/gcc.target/powerpc/cmpb32-2.c b/gcc/testsuite/gcc.target/powerpc/cmpb32-2.c
index 37b54745e0e..d4264ab6e7d 100644
--- a/gcc/testsuite/gcc.target/powerpc/cmpb32-2.c
+++ b/gcc/testsuite/gcc.target/powerpc/cmpb32-2.c
@@ -7,7 +7,7 @@ void abort ();
unsigned int
do_compare (unsigned int a, unsigned int b)
{
- return __builtin_cmpb (a, b); /* { dg-warning "implicit declaration of function '__builtin_cmpb'" } */
+ return __builtin_cmpb (a, b); /* { dg-error "'__builtin_p6_cmpb_32' requires the '-mcpu=power6' option" } */
}
void
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-mule-misc.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-mule-misc.c
index 7daf30215b8..19a5d044c4d 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-mule-misc.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-mule-misc.c
@@ -11,7 +11,7 @@ test_eub_char ()
{
volatile vector unsigned char v0 = {1, 0, 0, 0, 0, 0, 0, 0};
volatile vector unsigned char v1 = {0xff, 0, 0, 0, 0, 0, 0, 0};
- vector unsigned short res = vec_vmuleub (v0, v1);
+ vector unsigned short res = vec_mule (v0, v1);
if (res[0] != (unsigned short)v0[0] * (unsigned short)v1[0])
__builtin_abort ();
}
@@ -21,7 +21,7 @@ test_oub_char ()
{
volatile vector unsigned char v0 = {0, 1, 0, 0, 0, 0, 0, 0};
volatile vector unsigned char v1 = {0, 0xff, 0, 0, 0, 0, 0, 0};
- vector unsigned short res = vec_vmuloub (v0, v1);
+ vector unsigned short res = vec_mulo (v0, v1);
if (res[0] != (unsigned short)v0[1] * (unsigned short)v1[1])
__builtin_abort ();
}
@@ -31,7 +31,7 @@ test_euh_short ()
{
volatile vector unsigned short v0 = {1, 0, 0, 0};
volatile vector unsigned short v1 = {0xff, 0, 0, 0};
- vector unsigned int res = vec_vmuleuh (v0, v1);
+ vector unsigned int res = vec_mule (v0, v1);
if (res[0] != (unsigned int)v0[0] * (unsigned int)v1[0])
__builtin_abort ();
}
@@ -41,7 +41,7 @@ test_ouh_short ()
{
volatile vector unsigned short v0 = {0, 1, 0, 0};
volatile vector unsigned short v1 = {0, 0xff, 0, 0};
- vector unsigned int res = vec_vmulouh (v0, v1);
+ vector unsigned int res = vec_mulo (v0, v1);
if (res[0] != (unsigned int)v0[1] * (unsigned int)v1[1])
__builtin_abort ();
}
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-floatdouble.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-floatdouble.c
index ab396967c3d..3f22ba31862 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-floatdouble.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-floatdouble.c
@@ -18,7 +18,7 @@ vector float test_fc ()
vector double testd_00 (vector double x) { return vec_splat (x, 0b00000); }
vector double testd_01 (vector double x) { return vec_splat (x, 0b00001); }
vector double test_dc ()
-{ const vector double y = { 3.0, 5.0 }; return vec_splat (y, 0b00010); }
+{ const vector double y = { 3.0, 5.0 }; return vec_splat (y, 0b00001); }
/* If the source vector is a known constant, we will generate a load. */
/* { dg-final { scan-assembler-times {\mlvx\M|\mlxvd2x\M|\mlxv\M} 2 } } */
@@ -27,5 +27,5 @@ vector double test_dc ()
/* { dg-final { scan-assembler-times "vspltw|xxspltw" 3 } } */
/* For double types, we will generate xxpermdi instructions. */
-/* { dg-final { scan-assembler-times "xxpermdi" 3 } } */
+/* { dg-final { scan-assembler-times "xxpermdi" 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-longlong.c
index 4fa06c85ecc..9376f702a7a 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-longlong.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-longlong.c
@@ -9,23 +9,19 @@
vector bool long long testb_00 (vector bool long long x) { return vec_splat (x, 0b00000); }
vector bool long long testb_01 (vector bool long long x) { return vec_splat (x, 0b00001); }
-vector bool long long testb_02 (vector bool long long x) { return vec_splat (x, 0b00010); }
vector signed long long tests_00 (vector signed long long x) { return vec_splat (x, 0b00000); }
vector signed long long tests_01 (vector signed long long x) { return vec_splat (x, 0b00001); }
-vector signed long long tests_02 (vector signed long long x) { return vec_splat (x, 0b00010); }
vector unsigned long long testu_00 (vector unsigned long long x) { return vec_splat (x, 0b00000); }
vector unsigned long long testu_01 (vector unsigned long long x) { return vec_splat (x, 0b00001); }
-vector unsigned long long testu_02 (vector unsigned long long x) { return vec_splat (x, 0b00010); }
/* Similar test as above, but the source vector is a known constant. */
-vector bool long long test_bll () { const vector bool long long y = {12, 23}; return vec_splat (y, 0b00010); }
-vector signed long long test_sll () { const vector signed long long y = {34, 45}; return vec_splat (y, 0b00010); }
-vector unsigned long long test_ull () { const vector unsigned long long y = {56, 67}; return vec_splat (y, 0b00010); }
+vector bool long long test_bll () { const vector bool long long y = {12, 23}; return vec_splat (y, 0b00001); }
+vector signed long long test_sll () { const vector signed long long y = {34, 45}; return vec_splat (y, 0b00001); }
/* Assorted load instructions for the initialization with known constants. */
-/* { dg-final { scan-assembler-times {\mlvx\M|\mlxvd2x\M|\mlxv\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mlvx\M|\mlxvd2x\M|\mlxv\M|\mxxspltib\M} 2 } } */
/* xxpermdi for vec_splat of long long vectors.
At the time of this writing, the number of xxpermdi instructions
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-misc-invalid.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-misc-invalid.c
index 20f5b05561e..263a1723d31 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-misc-invalid.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-misc-invalid.c
@@ -10,24 +10,24 @@
vector signed short
testss_1 (unsigned int ui)
{
- return vec_splat_s16 (ui);/* { dg-error "argument 1 must be a 5-bit signed literal" } */
+ return vec_splat_s16 (ui);/* { dg-error "argument 1 must be a literal between -16 and 15, inclusive" } */
}
vector unsigned short
testss_2 (signed int si)
{
- return vec_splat_u16 (si);/* { dg-error "argument 1 must be a 5-bit signed literal" } */
+ return vec_splat_u16 (si);/* { dg-error "argument 1 must be a literal between -16 and 15, inclusive" } */
}
vector signed char
testsc_1 (unsigned int ui)
{
- return vec_splat_s8 (ui); /* { dg-error "argument 1 must be a 5-bit signed literal" } */
+ return vec_splat_s8 (ui); /* { dg-error "argument 1 must be a literal between -16 and 15, inclusive" } */
}
vector unsigned char
testsc_2 (signed int si)
{
- return vec_splat_u8 (si);/* { dg-error "argument 1 must be a 5-bit signed literal" } */
+ return vec_splat_u8 (si);/* { dg-error "argument 1 must be a literal between -16 and 15, inclusive" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c
index 102e1d1f813..0259e364aa6 100644
--- a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c
+++ b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c
@@ -27,11 +27,6 @@ v_sign sign_add_2 (v_sign a, v_sign b)
return vec_add (a, b);
}
-v_sign sign_add_3 (v_sign a, v_sign b)
-{
- return vec_vaddudm (a, b);
-}
-
v_sign sign_sub_1 (v_sign a, v_sign b)
{
return __builtin_altivec_vsubudm (a, b);
@@ -43,11 +38,6 @@ v_sign sign_sub_2 (v_sign a, v_sign b)
}
-v_sign sign_sub_3 (v_sign a, v_sign b)
-{
- return vec_vsubudm (a, b);
-}
-
v_sign sign_min_1 (v_sign a, v_sign b)
{
return __builtin_altivec_vminsd (a, b);
@@ -58,11 +48,6 @@ v_sign sign_min_2 (v_sign a, v_sign b)
return vec_min (a, b);
}
-v_sign sign_min_3 (v_sign a, v_sign b)
-{
- return vec_vminsd (a, b);
-}
-
v_sign sign_max_1 (v_sign a, v_sign b)
{
return __builtin_altivec_vmaxsd (a, b);
@@ -73,11 +58,6 @@ v_sign sign_max_2 (v_sign a, v_sign b)
return vec_max (a, b);
}
-v_sign sign_max_3 (v_sign a, v_sign b)
-{
- return vec_vmaxsd (a, b);
-}
-
v_sign sign_abs (v_sign a)
{
return vec_abs (a); /* xor, vsubudm, vmaxsd. */
@@ -98,41 +78,21 @@ v_uns uns_add_2 (v_uns a, v_uns b)
return vec_add (a, b);
}
-v_uns uns_add_3 (v_uns a, v_uns b)
-{
- return vec_vaddudm (a, b);
-}
-
v_uns uns_sub_2 (v_uns a, v_uns b)
{
return vec_sub (a, b);
}
-v_uns uns_sub_3 (v_uns a, v_uns b)
-{
- return vec_vsubudm (a, b);
-}
-
v_uns uns_min_2 (v_uns a, v_uns b)
{
return vec_min (a, b);
}
-v_uns uns_min_3 (v_uns a, v_uns b)
-{
- return vec_vminud (a, b);
-}
-
v_uns uns_max_2 (v_uns a, v_uns b)
{
return vec_max (a, b);
}
-v_uns uns_max_3 (v_uns a, v_uns b)
-{
- return vec_vmaxud (a, b);
-}
-
v_bool uns_eq (v_uns a, v_uns b)
{
return vec_cmpeq (a, b);
@@ -168,21 +128,11 @@ v_sign sign_sl_2 (v_sign a, v_uns b)
return vec_sl (a, b);
}
-v_sign sign_sl_3 (v_sign a, v_uns b)
-{
- return vec_vsld (a, b);
-}
-
v_uns uns_sl_2 (v_uns a, v_uns b)
{
return vec_sl (a, b);
}
-v_uns uns_sl_3 (v_uns a, v_uns b)
-{
- return vec_vsld (a, b);
-}
-
v_sign sign_sra_1 (v_sign a, v_sign b)
{
return __builtin_altivec_vsrad (a, b);
@@ -193,11 +143,6 @@ v_sign sign_sra_2 (v_sign a, v_uns b)
return vec_sra (a, b);
}
-v_sign sign_sra_3 (v_sign a, v_uns b)
-{
- return vec_vsrad (a, b);
-}
-
v_bchar vbchar_eq (v_bchar a, v_bchar b)
{
return vec_cmpeq (a, b);
diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-3.c b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-3.c
index 33304fe6132..ae6a3a8437b 100644
--- a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-3.c
@@ -37,11 +37,6 @@ vi_uns vi_pack_3 (vll_uns a, vll_uns b)
return vec_pack (a, b);
}
-vi_sign vi_pack_4 (vll_sign a, vll_sign b)
-{
- return vec_vpkudum (a, b);
-}
-
vs_sign vs_pack_1 (vi_sign a, vi_sign b)
{
return __builtin_altivec_vpkuwum (a, b);
@@ -52,11 +47,6 @@ vs_sign vs_pack_2 (vi_sign a, vi_sign b)
return vec_pack (a, b);
}
-vs_sign vs_pack_3 (vi_sign a, vi_sign b)
-{
- return vec_vpkuwum (a, b);
-}
-
vc_sign vc_pack_1 (vs_sign a, vs_sign b)
{
return __builtin_altivec_vpkuhum (a, b);
@@ -67,11 +57,6 @@ vc_sign vc_pack_2 (vs_sign a, vs_sign b)
return vec_pack (a, b);
}
-vc_sign vc_pack_3 (vs_sign a, vs_sign b)
-{
- return vec_vpkuhum (a, b);
-}
-
vll_sign vll_unpack_hi_1 (vi_sign a)
{
return __builtin_altivec_vupkhsw (a);
@@ -84,12 +69,7 @@ vll_sign vll_unpack_hi_2 (vi_sign a)
vll_sign vll_unpack_hi_3 (vi_sign a)
{
- return __builtin_vec_vupkhsw (a);
-}
-
-vll_sign vll_unpack_lo_1 (vi_sign a)
-{
- return vec_vupklsw (a);
+ return __builtin_altivec_vupkhsw (a);
}
vll_sign vll_unpack_lo_2 (vi_sign a)
@@ -97,11 +77,6 @@ vll_sign vll_unpack_lo_2 (vi_sign a)
return vec_unpackl (a);
}
-vll_sign vll_unpack_lo_3 (vi_sign a)
-{
- return vec_vupklsw (a);
-}
-
/* { dg-final { scan-assembler-times "vpkudum" 4 } } */
/* { dg-final { scan-assembler-times "vpkuwum" 3 } } */
/* { dg-final { scan-assembler-times "vpkuhum" 3 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-4.c b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-4.c
index 8329e2bae5a..2d2d141948f 100644
--- a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-4.c
+++ b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-4.c
@@ -28,22 +28,12 @@ vll_sign vll_clz_1 (vll_sign a)
vll_sign vll_clz_2 (vll_sign a)
{
- return vec_vclz (a);
-}
-
-vll_sign vll_clz_3 (vll_sign a)
-{
- return vec_vclzd (a);
+ return vec_cntlz (a);
}
vll_uns vll_clz_4 (vll_uns a)
{
- return vec_vclz (a);
-}
-
-vll_uns vll_clz_5 (vll_uns a)
-{
- return vec_vclzd (a);
+ return vec_cntlz (a);
}
vi_sign vi_clz_1 (vi_sign a)
@@ -53,22 +43,12 @@ vi_sign vi_clz_1 (vi_sign a)
vi_sign vi_clz_2 (vi_sign a)
{
- return vec_vclz (a);
-}
-
-vi_sign vi_clz_3 (vi_sign a)
-{
- return vec_vclzw (a);
+ return vec_cntlz (a);
}
vi_uns vi_clz_4 (vi_uns a)
{
- return vec_vclz (a);
-}
-
-vi_uns vi_clz_5 (vi_uns a)
-{
- return vec_vclzw (a);
+ return vec_cntlz (a);
}
vs_sign vs_clz_1 (vs_sign a)
@@ -78,22 +58,12 @@ vs_sign vs_clz_1 (vs_sign a)
vs_sign vs_clz_2 (vs_sign a)
{
- return vec_vclz (a);
-}
-
-vs_sign vs_clz_3 (vs_sign a)
-{
- return vec_vclzh (a);
+ return vec_cntlz (a);
}
vs_uns vs_clz_4 (vs_uns a)
{
- return vec_vclz (a);
-}
-
-vs_uns vs_clz_5 (vs_uns a)
-{
- return vec_vclzh (a);
+ return vec_cntlz (a);
}
vc_sign vc_clz_1 (vc_sign a)
@@ -103,22 +73,12 @@ vc_sign vc_clz_1 (vc_sign a)
vc_sign vc_clz_2 (vc_sign a)
{
- return vec_vclz (a);
-}
-
-vc_sign vc_clz_3 (vc_sign a)
-{
- return vec_vclzb (a);
+ return vec_cntlz (a);
}
vc_uns vc_clz_4 (vc_uns a)
{
- return vec_vclz (a);
-}
-
-vc_uns vc_clz_5 (vc_uns a)
-{
- return vec_vclzb (a);
+ return vec_cntlz (a);
}
vll_sign vll_popcnt_1 (vll_sign a)
@@ -126,24 +86,14 @@ vll_sign vll_popcnt_1 (vll_sign a)
return __builtin_altivec_vpopcntd (a);
}
-vll_sign vll_popcnt_2 (vll_sign a)
+vll_uns vll_popcnt_2 (vll_sign a)
{
- return vec_vpopcnt (a);
-}
-
-vll_sign vll_popcnt_3 (vll_sign a)
-{
- return vec_vpopcntd (a);
+ return vec_popcnt (a);
}
vll_uns vll_popcnt_4 (vll_uns a)
{
- return vec_vpopcnt (a);
-}
-
-vll_uns vll_popcnt_5 (vll_uns a)
-{
- return vec_vpopcntd (a);
+ return vec_popcnt (a);
}
vi_sign vi_popcnt_1 (vi_sign a)
@@ -151,24 +101,14 @@ vi_sign vi_popcnt_1 (vi_sign a)
return __builtin_altivec_vpopcntw (a);
}
-vi_sign vi_popcnt_2 (vi_sign a)
+vi_uns vi_popcnt_2 (vi_sign a)
{
- return vec_vpopcnt (a);
-}
-
-vi_sign vi_popcnt_3 (vi_sign a)
-{
- return vec_vpopcntw (a);
+ return vec_popcnt (a);
}
vi_uns vi_popcnt_4 (vi_uns a)
{
- return vec_vpopcnt (a);
-}
-
-vi_uns vi_popcnt_5 (vi_uns a)
-{
- return vec_vpopcntw (a);
+ return vec_popcnt (a);
}
vs_sign vs_popcnt_1 (vs_sign a)
@@ -176,24 +116,14 @@ vs_sign vs_popcnt_1 (vs_sign a)
return __builtin_altivec_vpopcnth (a);
}
-vs_sign vs_popcnt_2 (vs_sign a)
+vs_uns vs_popcnt_2 (vs_sign a)
{
- return vec_vpopcnt (a);
-}
-
-vs_sign vs_popcnt_3 (vs_sign a)
-{
- return vec_vpopcnth (a);
+ return vec_popcnt (a);
}
vs_uns vs_popcnt_4 (vs_uns a)
{
- return vec_vpopcnt (a);
-}
-
-vs_uns vs_popcnt_5 (vs_uns a)
-{
- return vec_vpopcnth (a);
+ return vec_popcnt (a);
}
vc_sign vc_popcnt_1 (vc_sign a)
@@ -201,24 +131,14 @@ vc_sign vc_popcnt_1 (vc_sign a)
return __builtin_altivec_vpopcntb (a);
}
-vc_sign vc_popcnt_2 (vc_sign a)
+vc_uns vc_popcnt_2 (vc_sign a)
{
- return vec_vpopcnt (a);
-}
-
-vc_sign vc_popcnt_3 (vc_sign a)
-{
- return vec_vpopcntb (a);
+ return vec_popcnt (a);
}
vc_uns vc_popcnt_4 (vc_uns a)
{
- return vec_vpopcnt (a);
-}
-
-vc_uns vc_popcnt_5 (vc_uns a)
-{
- return vec_vpopcntb (a);
+ return vec_popcnt (a);
}
vc_uns vc_gbb_1 (vc_uns a)
@@ -228,12 +148,12 @@ vc_uns vc_gbb_1 (vc_uns a)
vc_sign vc_gbb_2 (vc_sign a)
{
- return vec_vgbbd (a);
+ return vec_gb (a);
}
vc_uns vc_gbb_3 (vc_uns a)
{
- return vec_vgbbd (a);
+ return vec_gb (a);
}
/* { dg-final { scan-assembler-times "vclzd" 5 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-7.c b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-7.c
index fcfac7c50b1..f3035000fe7 100644
--- a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-7.c
+++ b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-7.c
@@ -10,22 +10,22 @@ typedef vector unsigned int v_uns;
v_sign even_sign (v_sign a, v_sign b)
{
- return vec_vmrgew (a, b);
+ return vec_mergee (a, b);
}
v_uns even_uns (v_uns a, v_uns b)
{
- return vec_vmrgew (a, b);
+ return vec_mergee (a, b);
}
v_sign odd_sign (v_sign a, v_sign b)
{
- return vec_vmrgow (a, b);
+ return vec_mergeo (a, b);
}
v_uns odd_uns (v_uns a, v_uns b)
{
- return vec_vmrgow (a, b);
+ return vec_mergeo (a, b);
}
/* { dg-final { scan-assembler-times "vmrgew" 2 } } */
^ permalink raw reply [flat|nested] 29+ messages in thread
* [gcc(refs/users/wschmidt/heads/builtins4)] rs6000: More bug fixes
@ 2021-02-07 18:18 William Schmidt
0 siblings, 0 replies; 29+ messages in thread
From: William Schmidt @ 2021-02-07 18:18 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:2edd7484b836aecb6cb3c7796e74864727749330
commit 2edd7484b836aecb6cb3c7796e74864727749330
Author: Bill Schmidt <wschmidt@linux.ibm.com>
Date: Wed Jan 13 15:47:32 2021 -0600
rs6000: More bug fixes
2021-01-13 Bill Schmidt <wschmidt@linux.ibm.com>
gcc/
* config/rs6000/rs6000-builtin-new.def: Assorted fixes.
* config/rs6000/rs6000-c.c
(altivec_resolve_new_overloaded_builtin): Fix thinko.
* config/rs6000/rs6000-call.c (rs6000_invalid_new_builtin): Handle
ENB_P10_64.
(rs6000_new_builtin_is_supported_p): Likewise.
(rs6000_expand_new_builtin): Likewise.
(rs6000_init_builtins): Likewise.
* config/rs6000/rs6000-gen-builtins.c (write_defines_file):
Define _ARCH_PPC64_PWR9 when appropriate.
* config/rs6000/rs6000-overload.def: Assorted fixes.
gcc/testsuite/
* gcc.target/powerpc/altivec-7.c: Remove vec_lvx call and adjust
counts.
* gcc.target/powerpc/ctz-4.c: Don't use deprecated builtins.
Diff:
---
gcc/config/rs6000/rs6000-builtin-new.def | 26 ++++-----
gcc/config/rs6000/rs6000-c.c | 2 +-
gcc/config/rs6000/rs6000-call.c | 14 +++++
gcc/config/rs6000/rs6000-gen-builtins.c | 3 +
gcc/config/rs6000/rs6000-overload.def | 84 ++++++++++++----------------
gcc/testsuite/gcc.target/powerpc/altivec-7.c | 5 +-
gcc/testsuite/gcc.target/powerpc/ctz-4.c | 64 +++------------------
7 files changed, 76 insertions(+), 122 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-builtin-new.def b/gcc/config/rs6000/rs6000-builtin-new.def
index 68d1a7d361a..9c4470bf400 100644
--- a/gcc/config/rs6000/rs6000-builtin-new.def
+++ b/gcc/config/rs6000/rs6000-builtin-new.def
@@ -1087,28 +1087,28 @@
; Cell builtins.
[cell]
- pure vuc __builtin_altivec_lvlx (signed long long, const void *);
+ pure vsc __builtin_altivec_lvlx (signed long long, const void *);
LVLX altivec_lvlx {ldvec}
- pure vuc __builtin_altivec_lvlxl (signed long long, const void *);
+ pure vsc __builtin_altivec_lvlxl (signed long long, const void *);
LVLXL altivec_lvlxl {ldvec}
- pure vuc __builtin_altivec_lvrx (signed long long, const void *);
+ pure vsc __builtin_altivec_lvrx (signed long long, const void *);
LVRX altivec_lvrx {ldvec}
- pure vuc __builtin_altivec_lvrxl (signed long long, const void *);
+ pure vsc __builtin_altivec_lvrxl (signed long long, const void *);
LVRXL altivec_lvrxl {ldvec}
- void __builtin_altivec_stvlx (vuc, signed long long, void *);
+ void __builtin_altivec_stvlx (vsc, signed long long, void *);
STVLX altivec_stvlx {stvec}
- void __builtin_altivec_stvlxl (vuc, signed long long, void *);
+ void __builtin_altivec_stvlxl (vsc, signed long long, void *);
STVLXL altivec_stvlxl {stvec}
- void __builtin_altivec_stvrx (vuc, signed long long, void *);
+ void __builtin_altivec_stvrx (vsc, signed long long, void *);
STVRX altivec_stvrx {stvec}
- void __builtin_altivec_stvrxl (vuc, signed long long, void *);
+ void __builtin_altivec_stvrxl (vsc, signed long long, void *);
STVRXL altivec_stvrxl {stvec}
@@ -2681,10 +2681,10 @@
const vuc __builtin_altivec_vsrv (vuc, vuc);
VSRV vsrv {}
- const signed int __builtin_scalar_byte_in_range (unsigned char, unsigned int);
+ const signed int __builtin_scalar_byte_in_range (unsigned int, unsigned int);
CMPRB cmprb {}
- const signed int __builtin_scalar_byte_in_either_range (unsigned char, unsigned int);
+ const signed int __builtin_scalar_byte_in_either_range (unsigned int, unsigned int);
CMPRB2 cmprb2 {}
const vull __builtin_vsx_extract4b (vuc, const int[0,12]);
@@ -2825,7 +2825,7 @@
void __builtin_altivec_stxvl (vuc, void *, long long);
STXVL stxvl {}
- const signed int __builtin_scalar_byte_in_set (unsigned char, unsigned long long);
+ const signed int __builtin_scalar_byte_in_set (unsigned int, unsigned long long);
CMPEQB cmpeqb {}
pure vuc __builtin_vsx_lxvl (const void *, unsigned long long);
@@ -2904,10 +2904,10 @@
; Decimal floating-point builtins.
[dfp]
- const _Decimal64 __builtin_ddedpd (const int<0,2>, _Decimal64);
+ const _Decimal64 __builtin_ddedpd (const int<2>, _Decimal64);
DDEDPD dfp_ddedpd_dd {}
- const _Decimal128 __builtin_ddedpdq (const int<0,2>, _Decimal128);
+ const _Decimal128 __builtin_ddedpdq (const int<2>, _Decimal128);
DDEDPDQ dfp_ddedpd_td {}
const _Decimal64 __builtin_denbcd (const int<1>, _Decimal64);
diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c
index 15caa86e20c..a3fe6f2abc9 100644
--- a/gcc/config/rs6000/rs6000-c.c
+++ b/gcc/config/rs6000/rs6000-c.c
@@ -2844,7 +2844,7 @@ altivec_resolve_new_overloaded_builtin (location_t loc, tree fndecl,
gcc_assert (instance != NULL);
tree fntype = rs6000_builtin_info_x[instance->bifid].fntype;
tree parmtype0 = TREE_VALUE (TYPE_ARG_TYPES (fntype));
- tree parmtype1 = TREE_VALUE (TREE_CHAIN (parmtype0));
+ tree parmtype1 = TREE_VALUE (TREE_CHAIN (TYPE_ARG_TYPES (fntype)));
if (rs6000_new_builtin_type_compatible (types[0], parmtype0)
&& rs6000_new_builtin_type_compatible (types[1], parmtype1))
diff --git a/gcc/config/rs6000/rs6000-call.c b/gcc/config/rs6000/rs6000-call.c
index 8177035ac8c..eff580b3fa0 100644
--- a/gcc/config/rs6000/rs6000-call.c
+++ b/gcc/config/rs6000/rs6000-call.c
@@ -11818,6 +11818,10 @@ rs6000_invalid_new_builtin (enum rs6000_gen_builtins fncode)
case ENB_P10:
error ("%qs requires the %qs option", name, "-mcpu=power10");
break;
+ case ENB_P10_64:
+ error ("%qs requires the %qs option and either the %qs or %qs option",
+ name, "-mcpu=power10", "-m64", "-mpowerpc64");
+ break;
case ENB_MMA:
error ("%qs requires the %qs option", name, "-mmma");
break;
@@ -14092,6 +14096,10 @@ rs6000_new_builtin_is_supported_p (enum rs6000_gen_builtins fncode)
if (!TARGET_POWER10)
return false;
break;
+ case ENB_P10_64:
+ if (!TARGET_POWER10 || !TARGET_POWERPC64)
+ return false;
+ break;
case ENB_MMA:
if (!TARGET_MMA)
return false;
@@ -15351,6 +15359,10 @@ rs6000_expand_new_builtin (tree exp, rtx target,
if (!TARGET_POWER10)
return const0_rtx;
break;
+ case ENB_P10_64:
+ if (!TARGET_POWER10 || !TARGET_POWERPC64)
+ return const0_rtx;
+ break;
case ENB_MMA:
if (!TARGET_MMA)
return const0_rtx;
@@ -16000,6 +16012,8 @@ rs6000_init_builtins (void)
continue;
if (e == ENB_P10 && !TARGET_POWER10)
continue;
+ if (e == ENB_P10_64 && (!TARGET_POWER10 || !TARGET_POWERPC64))
+ continue;
if (e == ENB_MMA && !TARGET_MMA)
continue;
tree fntype = rs6000_builtin_info_x[i].fntype;
diff --git a/gcc/config/rs6000/rs6000-gen-builtins.c b/gcc/config/rs6000/rs6000-gen-builtins.c
index 8f129f47d8c..b75b29303dd 100644
--- a/gcc/config/rs6000/rs6000-gen-builtins.c
+++ b/gcc/config/rs6000/rs6000-gen-builtins.c
@@ -2768,6 +2768,9 @@ write_defines_file ()
{
fprintf (defines_file, "#ifndef _RS6000_VECDEFINES_H\n");
fprintf (defines_file, "#define _RS6000_VECDEFINES_H 1\n\n");
+ fprintf (defines_file, "#if defined(_ARCH_PPC64) && defined (_ARCH_PWR9)\n");
+ fprintf (defines_file, " #define _ARCH_PPC64_PWR9 1\n");
+ fprintf (defines_file, "#endif\n\n");
for (int i = 0; i < num_ovld_stanzas; i++)
if (strcmp (ovld_stanzas[i].extern_name, "SKIP"))
{
diff --git a/gcc/config/rs6000/rs6000-overload.def b/gcc/config/rs6000/rs6000-overload.def
index ec884b63388..e80e163f8ec 100644
--- a/gcc/config/rs6000/rs6000-overload.def
+++ b/gcc/config/rs6000/rs6000-overload.def
@@ -730,7 +730,7 @@
VCMPEQUD_P VCMPEQUD_P_SB
[VEC_CMPEQB, SKIP, __builtin_byte_in_set]
- signed int __builtin_byte_in_set (unsigned char, unsigned long long);
+ signed int __builtin_byte_in_set (unsigned int, unsigned long long);
CMPEQB
; #### XVCMPGESP{TARGET_VSX};VCMPGEFP
@@ -738,19 +738,19 @@
vbc __builtin_vec_cmpge (vsc, vsc);
CMPGE_16QI CMPGE_16QI_VSC
vbc __builtin_vec_cmpge (vuc, vuc);
- CMPGE_16QI CMPGE_16QI_VUC
+ CMPGE_U16QI CMPGE_16QI_VUC
vbs __builtin_vec_cmpge (vss, vss);
CMPGE_8HI CMPGE_8HI_VSS
vbs __builtin_vec_cmpge (vus, vus);
- CMPGE_8HI CMPGE_8HI_VUS
+ CMPGE_U8HI CMPGE_8HI_VUS
vbi __builtin_vec_cmpge (vsi, vsi);
CMPGE_4SI CMPGE_4SI_VSI
vbi __builtin_vec_cmpge (vui, vui);
- CMPGE_4SI CMPGE_4SI_VUI
+ CMPGE_U4SI CMPGE_4SI_VUI
vbll __builtin_vec_cmpge (vsll, vsll);
CMPGE_2DI CMPGE_2DI_VSLL
vbll __builtin_vec_cmpge (vull, vull);
- CMPGE_2DI CMPGE_2DI_VULL
+ CMPGE_U2DI CMPGE_2DI_VULL
vbi __builtin_vec_cmpge (vf, vf);
VCMPGEFP
vbll __builtin_vec_cmpge (vd, vd);
@@ -1021,11 +1021,11 @@
VCMPNEZW_P VCMPNEZW_VUI_P
[VEC_CMPRB, SKIP, __builtin_byte_in_range]
- signed int __builtin_byte_in_range (unsigned char, unsigned int);
+ signed int __builtin_byte_in_range (unsigned int, unsigned int);
CMPRB
[VEC_CMPRB2, SKIP, __builtin_byte_in_either_range]
- signed int __builtin_byte_in_range (unsigned char, unsigned int);
+ signed int __builtin_byte_in_range (unsigned int, unsigned int);
CMPRB2
[VEC_CNTLZ, vec_cntlz, __builtin_vec_vclz, _ARCH_PWR8]
@@ -4640,6 +4640,10 @@
STXVD2X_V2DI STXVD2X_ULL
void __builtin_vec_vsx_st (vbll, signed long long, vbll *);
STXVD2X_V2DI STXVD2X_VBLL
+ void __builtin_vec_vsx_st (vsq, signed long long, signed __int128 *);
+ STXVD2X_V1TI STXVD2X_SQ
+ void __builtin_vec_vsx_st (vuq, signed long long, unsigned __int128 *);
+ STXVD2X_V1TI STXVD2X_UQ
void __builtin_vec_vsx_st (vf, signed long long, vf *);
STXVW4X_V4SF STXVW4X_VF
void __builtin_vec_vsx_st (vf, signed long long, float *);
@@ -4651,67 +4655,49 @@
[VEC_XST_BE, vec_xst_be, __builtin_vec_xst_be, __VSX__]
void __builtin_vec_xst_be (vsc, signed long long, vsc *);
- STXVW4X_V16QI STXVW4X_VSC_BE
+ ST_ELEMREV_V16QI ST_ELEMREV_VSC
void __builtin_vec_xst_be (vsc, signed long long, signed char *);
- STXVW4X_V16QI STXVW4X_SC_BE
+ ST_ELEMREV_V16QI ST_ELEMREV_SC_
void __builtin_vec_xst_be (vuc, signed long long, vuc *);
- STXVW4X_V16QI STXVW4X_VUC_BE
+ ST_ELEMREV_V16QI ST_ELEMREV_VUC
void __builtin_vec_xst_be (vuc, signed long long, unsigned char *);
- STXVW4X_V16QI STXVW4X_UC_BE
- void __builtin_vec_xst_be (vbc, signed long long, vbc *);
- STXVW4X_V16QI STXVW4X_VBC_BE
- void __builtin_vec_xst_be (vbc, signed long long, signed char *);
- STXVW4X_V16QI STXVW4X_VBC_S_BE
- void __builtin_vec_xst_be (vbc, signed long long, unsigned char *);
- STXVW4X_V16QI STXVW4X_VBC_U_BE
+ ST_ELEMREV_V16QI ST_ELEMREV_UC
void __builtin_vec_xst_be (vss, signed long long, vss *);
- STXVW4X_V8HI STXVW4X_VSS_BE
+ ST_ELEMREV_V8HI ST_ELEMREV_VSS
void __builtin_vec_xst_be (vss, signed long long, signed short *);
- STXVW4X_V8HI STXVW4X_SS_BE
+ ST_ELEMREV_V8HI ST_ELEMREV_SS
void __builtin_vec_xst_be (vus, signed long long, vus *);
- STXVW4X_V8HI STXVW4X_VUS_BE
+ ST_ELEMREV_V8HI ST_ELEMREV_VUS
void __builtin_vec_xst_be (vus, signed long long, unsigned short *);
- STXVW4X_V8HI STXVW4X_US_BE
- void __builtin_vec_xst_be (vbs, signed long long, vbs *);
- STXVW4X_V8HI STXVW4X_VBS_BE
- void __builtin_vec_xst_be (vbs, signed long long, signed short *);
- STXVW4X_V8HI STXVW4X_VBS_S_BE
- void __builtin_vec_xst_be (vbs, signed long long, unsigned short *);
- STXVW4X_V8HI STXVW4X_VBS_U_BE
- void __builtin_vec_xst_be (vp, signed long long, vp *);
- STXVW4X_V8HI STXVW4X_VP_BE
+ ST_ELEMREV_V8HI ST_ELEMREV_US
void __builtin_vec_xst_be (vsi, signed long long, vsi *);
- STXVW4X_V4SI STXVW4X_VSI_BE
+ ST_ELEMREV_V4SI ST_ELEMREV_VSI
void __builtin_vec_xst_be (vsi, signed long long, signed int *);
- STXVW4X_V4SI STXVW4X_SI_BE
+ ST_ELEMREV_V4SI ST_ELEMREV_SI
void __builtin_vec_xst_be (vui, signed long long, vui *);
- STXVW4X_V4SI STXVW4X_VUI_BE
+ ST_ELEMREV_V4SI ST_ELEMREV_VUI
void __builtin_vec_xst_be (vui, signed long long, unsigned int *);
- STXVW4X_V4SI STXVW4X_UI_BE
- void __builtin_vec_xst_be (vbi, signed long long, vbi *);
- STXVW4X_V4SI STXVW4X_VBI_BE
- void __builtin_vec_xst_be (vbi, signed long long, signed int *);
- STXVW4X_V4SI STXVW4X_VBI_S_BE
- void __builtin_vec_xst_be (vbi, signed long long, unsigned int *);
- STXVW4X_V4SI STXVW4X_VBI_U_BE
+ ST_ELEMREV_V4SI ST_ELEMREV_UI
void __builtin_vec_xst_be (vsll, signed long long, vsll *);
- STXVD2X_V2DI STXVD2X_VSLL_BE
+ ST_ELEMREV_V2DI ST_ELEMREV_VSLL
void __builtin_vec_xst_be (vsll, signed long long, signed long long *);
- STXVD2X_V2DI STXVD2X_SLL_BE
+ ST_ELEMREV_V2DI ST_ELEMREV_SLL
void __builtin_vec_xst_be (vull, signed long long, vull *);
- STXVD2X_V2DI STXVD2X_VULL_BE
+ ST_ELEMREV_V2DI ST_ELEMREV_VULL
void __builtin_vec_xst_be (vull, signed long long, unsigned long long *);
- STXVD2X_V2DI STXVD2X_ULL_BE
- void __builtin_vec_xst_be (vbll, signed long long, vbll *);
- STXVD2X_V2DI STXVD2X_VBLL_BE
+ ST_ELEMREV_V2DI ST_ELEMREV_ULL
+ void __builtin_vec_xst_be (vsq, signed long long, signed __int128 *);
+ ST_ELEMREV_V1TI ST_ELEMREV_SQ
+ void __builtin_vec_xst_be (vuq, signed long long, unsigned __int128 *);
+ ST_ELEMREV_V1TI ST_ELEMREV_UQ
void __builtin_vec_xst_be (vf, signed long long, vf *);
- STXVW4X_V4SF STXVW4X_VF_BE
+ ST_ELEMREV_V4SF ST_ELEMREV_VF
void __builtin_vec_xst_be (vf, signed long long, float *);
- STXVW4X_V4SF STXVW4X_F_BE
+ ST_ELEMREV_V4SF ST_ELEMREV_F
void __builtin_vec_xst_be (vd, signed long long, vd *);
- STXVD2X_V2DF STXVD2X_VD_BE
+ ST_ELEMREV_V2DF ST_ELEMREV_VD
void __builtin_vec_xst_be (vd, signed long long, double *);
- STXVD2X_V2DF STXVD2X_D_BE
+ ST_ELEMREV_V2DF ST_ELEMREV_D
[VEC_XST_LEN_R, vec_xst_len_r, __builtin_vec_xst_len_r, _ARCH_PPC64_PWR9]
void __builtin_vsx_xst_len_r (vuc, unsigned char *, unsigned long long);
diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-7.c b/gcc/testsuite/gcc.target/powerpc/altivec-7.c
index 0cef426fcd9..46bf7148b20 100644
--- a/gcc/testsuite/gcc.target/powerpc/altivec-7.c
+++ b/gcc/testsuite/gcc.target/powerpc/altivec-7.c
@@ -41,7 +41,6 @@ int main ()
*vecushort++ = vec_xor((vector bool short)vecshort[0], vecushort[1]);
*vecushort++ = vec_xor(vecushort[0], (vector bool short)vecshort[1]);
*vecuint++ = vec_ld(var_int[0], uintp[1]);
- *vecuint++ = vec_lvx(var_int[0], uintp[1]);
*vecuint++ = vec_msum(vecuchar[0], vecuchar[1], vecuint[2]);
*vecuchar++ = vec_xor(vecuchar[0], (vector unsigned char)vecchar[1]);
@@ -79,10 +78,10 @@ int main ()
vec_ld lvx
*/
-/* { dg-final { scan-assembler-times "vpkpx" 2 } } */
+/* { dg-final { scan-assembler-times "vpkpx" 1 } } */
/* { dg-final { scan-assembler-times "vmulesb" 1 } } */
/* { dg-final { scan-assembler-times "vmulosb" 1 } } */
-/* { dg-final { scan-assembler-times {\mlvx\M} 42 { target { ! powerpc_vsx } } } } */
+/* { dg-final { scan-assembler-times {\mlvx\M} 39 { target { ! powerpc_vsx } } } } */
/* { dg-final { scan-assembler-times {\mlxv} 0 { target { ! powerpc_vsx } } } } */
/* { dg-final { scan-assembler-times {\mlvx\M} 0 { target powerpc_vsx } } } */
/* { dg-final { scan-assembler-times {\mlxv} 42 { target powerpc_vsx } } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/ctz-4.c b/gcc/testsuite/gcc.target/powerpc/ctz-4.c
index 74d305a8fbc..8e5f7699a63 100644
--- a/gcc/testsuite/gcc.target/powerpc/ctz-4.c
+++ b/gcc/testsuite/gcc.target/powerpc/ctz-4.c
@@ -8,97 +8,49 @@
vector signed char
count_trailing_zeros_v16qi_1s (vector signed char a)
{
- return vec_vctz (a);
-}
-
-vector signed char
-count_trailing_zeros_v16qi_2s (vector signed char a)
-{
- return vec_vctzb (a);
+ return vec_cnttz (a);
}
vector unsigned char
count_trailing_zeros_v16qi_1u (vector unsigned char a)
{
- return vec_vctz (a);
-}
-
-vector unsigned char
-count_trailing_zeros_v16qi_2u (vector unsigned char a)
-{
- return vec_vctzb (a);
+ return vec_cnttz (a);
}
vector short
count_trailing_zeros_v8hi_1s (vector short a)
{
- return vec_vctz (a);
-}
-
-vector short
-count_trailing_zeros_v8hi_2s (vector short a)
-{
- return vec_vctzh (a);
+ return vec_cnttz (a);
}
vector unsigned short
count_trailing_zeros_v8hi_1u (vector unsigned short a)
{
- return vec_vctz (a);
-}
-
-vector unsigned short
-count_trailing_zeros_v8hi_2u (vector unsigned short a)
-{
- return vec_vctzh (a);
+ return vec_cnttz (a);
}
vector int
count_trailing_zeros_v4si_1s (vector int a)
{
- return vec_vctz (a);
-}
-
-vector int
-count_trailing_zeros_v4si_2s (vector int a)
-{
- return vec_vctzw (a);
+ return vec_cnttz (a);
}
vector unsigned int
count_trailing_zeros_v4si_1u (vector unsigned int a)
{
- return vec_vctz (a);
-}
-
-vector unsigned int
-count_trailing_zeros_v4si_2u (vector unsigned int a)
-{
- return vec_vctzw (a);
+ return vec_cnttz (a);
}
vector long long
count_trailing_zeros_v2di_1s (vector long long a)
{
- return vec_vctz (a);
-}
-
-vector long long
-count_trailing_zeros_v2di_2s (vector long long a)
-{
- return vec_vctzd (a);
+ return vec_cnttz (a);
}
vector unsigned long long
count_trailing_zeros_v2di_1u (vector unsigned long long a)
{
- return vec_vctz (a);
-}
-
-vector unsigned long long
-count_trailing_zeros_v2di_2u (vector unsigned long long a)
-{
- return vec_vctzd (a);
+ return vec_cnttz (a);
}
/* { dg-final { scan-assembler "vctzb" } } */
^ permalink raw reply [flat|nested] 29+ messages in thread
* [gcc(refs/users/wschmidt/heads/builtins4)] rs6000: More bug fixes
@ 2021-02-07 18:18 William Schmidt
0 siblings, 0 replies; 29+ messages in thread
From: William Schmidt @ 2021-02-07 18:18 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:cf4773483057eb136922d6e0a6e27dc644a76dbb
commit cf4773483057eb136922d6e0a6e27dc644a76dbb
Author: Bill Schmidt <wschmidt@linux.ibm.com>
Date: Wed Jan 13 08:58:23 2021 -0600
rs6000: More bug fixes
2021-01-13 Bill Schmidt <wschmidt@linux.ibm.com>
gcc/
* config/rs6000/rs6000-builtin-new.def: Assorted fixes.
* config/rs6000/rs6000-c.c
(altivec_resolve_new_overloaded_builtin): Remove incorrect
gcc_assert.
* config/rs6000/rs6000-call.c (rs6000_init_builtins): Fix
initialization of ptr_intTI_type_node and ptr_uintTI_type_node.
* config/rs6000/rs6000-gen-builtins.c (typeinfo): Remove isopaque.
(match_type): Remove vop handling.
(construct_fntype_id): Remove isopaque handling.
(parse_ovld_entry): Commentary update.
* config/rs6000/rs6000-overload.def: Assorted fixes.
gcc/testsuite/
* gcc.dg/vmx/ops.c: Remove deprecated calls.
* gcc.target/powerpc/altivec-7.c: Likewise.
* gcc.target/powerpc/bfp/scalar-test-neg-2.c: Adjust.
* gcc.target/powerpc/bfp/scalar-test-neg-3.c: Adjust.
* gcc.target/powerpc/bfp/scalar-test-neg-5.c: Adjust.
* gcc.target/powerpc/builtins-3-p9-runnable.c: Adjust.
Diff:
---
gcc/config/rs6000/rs6000-builtin-new.def | 173 ++++++++++-----------
gcc/config/rs6000/rs6000-c.c | 1 -
gcc/config/rs6000/rs6000-call.c | 5 +-
gcc/config/rs6000/rs6000-gen-builtins.c | 49 ++----
gcc/config/rs6000/rs6000-overload.def | 47 +++---
gcc/testsuite/gcc.dg/vmx/ops.c | 86 ----------
gcc/testsuite/gcc.target/powerpc/altivec-7.c | 29 ++--
.../gcc.target/powerpc/bfp/scalar-test-neg-2.c | 2 +-
.../gcc.target/powerpc/bfp/scalar-test-neg-3.c | 2 +-
.../gcc.target/powerpc/bfp/scalar-test-neg-5.c | 2 +-
.../gcc.target/powerpc/builtins-3-p9-runnable.c | 8 +-
11 files changed, 139 insertions(+), 265 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-builtin-new.def b/gcc/config/rs6000/rs6000-builtin-new.def
index 6fa121bb38d..68d1a7d361a 100644
--- a/gcc/config/rs6000/rs6000-builtin-new.def
+++ b/gcc/config/rs6000/rs6000-builtin-new.def
@@ -81,7 +81,6 @@
; vp vector pixel
; vf vector float
; vd vector double
-; vop opaque vector (matches all vectors)
;
; For simplicity, We don't support "short int" and "long long int".
; We don't currently support a <basetype> of "bool", "long double",
@@ -127,30 +126,20 @@
;
; It is important to note that each entry's <bif-name> must be
; unique. The code generated from this file will call def_builtin
-; for each entry, and this can only happen once per name. This
-; means that in some cases we currently retain some tricks from
-; the old builtin support to aid with overloading. This
-; unfortunately seems to be necessary for backward compatibility.
+; for each entry, and this can only happen once per name.
;
-; The two tricks at our disposal are the void pointer and the "vop"
-; vector type. We use void pointers anywhere that pointer types
-; are accepted (primarily for vector load/store built-ins). In
-; practice this means that we accept pointers to anything, not
-; just to the types that we intend. We use the "vop" vector type
-; anytime that a built-in must accept vector types that have
-; different modes. This is an opaque type that will match any
-; vector type, which may mean matching vector types that we don't
-; intend.
+; The type signature for the builtin must match the modes of the RTL
+; pattern <bif-pattern>. When a builtin is used only as a basis for
+; overloading, you can use an arbitrary type for each mode (for example,
+; for V8HImode, you could use vp, vss, vus, or vbs). The overloading
+; machinery takes care of adding appropriate casts between vectors to
+; satisfy impedance matching. The overloaded prototypes are the ones
+; that must match what users expect. Thus you will often have a small
+; number of entries in this file that correspond to a much greater
+; number of entries in rs6000-overload.def.
;
-; We can improve on "vop" when a vector argument or return type is
-; limited to one mode. For example, "vsll" and "vull" both map to
-; V2DImode. In this case, we can arbitrarily pick one of the
-; acceptable types to use in the prototype. The signature used by
-; def_builtin is based on modes, not types, so this works well.
-; Only use "vop" when there is no alternative. When there is a
-; choice, best practice is to use the signed type ("vsll" in the
-; example above) unless the choices are unsigned and bool, in
-; which case the unsigned type should be used.
+; However, builtins in this file that are expected to be directly called
+; by users must have one version for each expected type combination.
;
; Eventually we want to automatically generate built-in documentation
; from the entries in this file. Documenting of built-ins with more
@@ -354,12 +343,24 @@
vuc __builtin_altivec_mask_for_load (const void *);
MASK_FOR_LOAD altivec_lvsr_direct {ldstmask}
- vus __builtin_altivec_mfvscr ();
+ vss __builtin_altivec_mfvscr ();
MFVSCR altivec_mfvscr {}
- void __builtin_altivec_mtvscr (vop);
+ void __builtin_altivec_mtvscr (vsi);
MTVSCR altivec_mtvscr {}
+ const vsll __builtin_altivec_vmulesw (vsi, vsi);
+ VMULESW vec_widen_smult_even_v4si {}
+
+ const vull __builtin_altivec_vmuleuw (vui, vui);
+ VMULEUW vec_widen_umult_even_v4si {}
+
+ const vsll __builtin_altivec_vmulosw (vsi, vsi);
+ VMULOSW vec_widen_smult_odd_v4si {}
+
+ const vull __builtin_altivec_vmulouw (vui, vui);
+ VMULOUW vec_widen_umult_odd_v4si {}
+
const vsc __builtin_altivec_nabs_v16qi (vsc);
NABS_V16QI nabsv16qi2 {}
@@ -441,7 +442,7 @@
const vus __builtin_altivec_vadduhs (vus, vus);
VADDUHS altivec_vadduhs {}
- const vui __builtin_altivec_vadduwm (vui, vui);
+ const vsi __builtin_altivec_vadduwm (vsi, vsi);
VADDUWM addv4si3 {}
const vui __builtin_altivec_vadduws (vui, vui);
@@ -528,19 +529,19 @@
const vsc __builtin_altivec_vcmpequb (vuc, vuc);
VCMPEQUB vector_eqv16qi {}
- const int __builtin_altivec_vcmpequb_p (int, vuc, vuc);
+ const int __builtin_altivec_vcmpequb_p (int, vsc, vsc);
VCMPEQUB_P vector_eq_v16qi_p {pred}
const vss __builtin_altivec_vcmpequh (vus, vus);
VCMPEQUH vector_eqv8hi {}
- const int __builtin_altivec_vcmpequh_p (int, vus, vus);
+ const int __builtin_altivec_vcmpequh_p (int, vss, vss);
VCMPEQUH_P vector_eq_v8hi_p {pred}
const vsi __builtin_altivec_vcmpequw (vui, vui);
VCMPEQUW vector_eqv4si {}
- const int __builtin_altivec_vcmpequw_p (int, vui, vui);
+ const int __builtin_altivec_vcmpequw_p (int, vsi, vsi);
VCMPEQUW_P vector_eq_v4si_p {pred}
const vf __builtin_altivec_vcmpgefp (vf, vf);
@@ -576,19 +577,19 @@
const vsc __builtin_altivec_vcmpgtub (vuc, vuc);
VCMPGTUB vector_gtuv16qi {}
- const int __builtin_altivec_vcmpgtub_p (int, vuc, vuc);
+ const int __builtin_altivec_vcmpgtub_p (int, vsc, vsc);
VCMPGTUB_P vector_gtu_v16qi_p {pred}
const vss __builtin_altivec_vcmpgtuh (vus, vus);
VCMPGTUH vector_gtuv8hi {}
- const int __builtin_altivec_vcmpgtuh_p (int, vus, vus);
+ const int __builtin_altivec_vcmpgtuh_p (int, vss, vss);
VCMPGTUH_P vector_gtu_v8hi_p {pred}
const vsi __builtin_altivec_vcmpgtuw (vui, vui);
VCMPGTUW vector_gtuv4si {}
- const int __builtin_altivec_vcmpgtuw_p (int, vui, vui);
+ const int __builtin_altivec_vcmpgtuw_p (int, vsi, vsi);
VCMPGTUW_P vector_gtu_v4si_p {pred}
const vsi __builtin_altivec_vctsxs (vf, const int<5>);
@@ -873,7 +874,7 @@
const vuq __builtin_altivec_vsel_1ti_uns (vuq, vuq, vuq);
VSEL_1TI_UNS vector_select_v1ti_uns {}
- const vf __builtin_altivec_vsel_4sf (vf, vf, vui);
+ const vf __builtin_altivec_vsel_4sf (vf, vf, vf);
VSEL_4SF vector_select_v4sf {}
const vsi __builtin_altivec_vsel_4si (vsi, vsi, vui);
@@ -888,7 +889,7 @@
const vus __builtin_altivec_vsel_8hi_uns (vus, vus, vus);
VSEL_8HI_UNS vector_select_v8hi_uns {}
- const vop __builtin_altivec_vsl (vop, vuc);
+ const vsi __builtin_altivec_vsl (vsi, vsi);
VSL altivec_vsl {}
const vsc __builtin_altivec_vslb (vsc, vuc);
@@ -909,7 +910,7 @@
const vss __builtin_altivec_vslh (vss, vus);
VSLH vashlv8hi3 {}
- const vop __builtin_altivec_vslo (vop, vuc);
+ const vsi __builtin_altivec_vslo (vsi, vsi);
VSLO altivec_vslo {}
const vsi __builtin_altivec_vslw (vsi, vui);
@@ -933,7 +934,7 @@
const vsi __builtin_altivec_vspltw (vsi, const int<2>);
VSPLTW altivec_vspltw {}
- const vop __builtin_altivec_vsr (vop, vop);
+ const vsi __builtin_altivec_vsr (vsi, vsi);
VSR altivec_vsr {}
const vsc __builtin_altivec_vsrab (vsc, vuc);
@@ -951,7 +952,7 @@
const vss __builtin_altivec_vsrh (vss, vus);
VSRH vlshrv8hi3 {}
- const vop __builtin_altivec_vsro (vop, vop);
+ const vsi __builtin_altivec_vsro (vsi, vsi);
VSRO altivec_vsro {}
const vsi __builtin_altivec_vsrw (vsi, vui);
@@ -1086,28 +1087,28 @@
; Cell builtins.
[cell]
- pure vop __builtin_altivec_lvlx (signed long long, const void *);
+ pure vuc __builtin_altivec_lvlx (signed long long, const void *);
LVLX altivec_lvlx {ldvec}
- pure vop __builtin_altivec_lvlxl (signed long long, const void *);
+ pure vuc __builtin_altivec_lvlxl (signed long long, const void *);
LVLXL altivec_lvlxl {ldvec}
- pure vop __builtin_altivec_lvrx (signed long long, const void *);
+ pure vuc __builtin_altivec_lvrx (signed long long, const void *);
LVRX altivec_lvrx {ldvec}
- pure vop __builtin_altivec_lvrxl (signed long long, const void *);
+ pure vuc __builtin_altivec_lvrxl (signed long long, const void *);
LVRXL altivec_lvrxl {ldvec}
- void __builtin_altivec_stvlx (vop, signed long long, void *);
+ void __builtin_altivec_stvlx (vuc, signed long long, void *);
STVLX altivec_stvlx {stvec}
- void __builtin_altivec_stvlxl (vop, signed long long, void *);
+ void __builtin_altivec_stvlxl (vuc, signed long long, void *);
STVLXL altivec_stvlxl {stvec}
- void __builtin_altivec_stvrx (vop, signed long long, void *);
+ void __builtin_altivec_stvrx (vuc, signed long long, void *);
STVRX altivec_stvrx {stvec}
- void __builtin_altivec_stvrxl (vop, signed long long, void *);
+ void __builtin_altivec_stvrxl (vuc, signed long long, void *);
STVRXL altivec_stvrxl {stvec}
@@ -1167,6 +1168,24 @@
const vull __builtin_altivec_vandc_v2di_uns (vull, vull);
VANDC_V2DI_UNS andcv2di3 {}
+ const vbll __builtin_altivec_vcmpequd (vull, vull);
+ VCMPEQUD vector_eqv2di {}
+
+ const int __builtin_altivec_vcmpequd_p (int, vsll, vsll);
+ VCMPEQUD_P vector_eq_v2di_p {pred}
+
+ const vsll __builtin_altivec_vcmpgtsd (vsll, vsll);
+ VCMPGTSD vector_gtv2di {}
+
+ const int __builtin_altivec_vcmpgtsd_p (int, vsll, vsll);
+ VCMPGTSD_P vector_gt_v2di_p {pred}
+
+ const vsll __builtin_altivec_vcmpgtud (vull, vull);
+ VCMPGTUD vector_gtuv2di {}
+
+ const int __builtin_altivec_vcmpgtud_p (int, vull, vull);
+ VCMPGTUD_P vector_gtu_v2di_p {pred}
+
const vd __builtin_altivec_vnor_v2df (vd, vd);
VNOR_V2DF norv2df3 {}
@@ -1717,11 +1736,11 @@
XVCVSXWDP vsx_xvcvsxwdp {}
; Need to pick one or the other here!! ####
-; Second one is used in the overload table (old and new) for VEC_FLOAT.
-; const vf __builtin_vsx_xvcvsxwsp (vsi);
-; XVCVSXWSP vsx_floatv4siv4sf2 {}
+; The first is needed to make vec_float work correctly.
const vf __builtin_vsx_xvcvsxwsp (vsi);
- XVCVSXWSP_V4SF vsx_xvcvsxwdp {}
+ XVCVSXWSP vsx_floatv4siv4sf2 {}
+; const vf __builtin_vsx_xvcvsxwsp (vsi);
+; XVCVSXWSP_V4SF vsx_xvcvsxwdp {}
const vd __builtin_vsx_xvcvuxddp (vull);
XVCVUXDDP vsx_floatunsv2div2df2 {}
@@ -1740,11 +1759,11 @@
XVCVUXWDP vsx_xvcvuxwdp {}
; Need to pick one or the other here!! ####
-; Second one is used in the overload table (old and new) for VEC_FLOAT.
-; const vf __builtin_vsx_xvcvuxwsp (vui);
-; XVCVUXWSP vsx_floatunsv4siv4sf2 {}
+; The first is needed to make vec_float work correctly.
const vf __builtin_vsx_xvcvuxwsp (vui);
- XVCVUXWSP_V4SF vsx_xvcvuxwsp {}
+ XVCVUXWSP vsx_floatunsv4siv4sf2 {}
+; const vf __builtin_vsx_xvcvuxwsp (vui);
+; XVCVUXWSP_V4SF vsx_xvcvuxwsp {}
fpmath vd __builtin_vsx_xvdivdp (vd, vd);
XVDIVDP divv2df3 {}
@@ -2199,24 +2218,6 @@
const vuc __builtin_altivec_vbpermq2 (vuc, vuc);
VBPERMQ2 altivec_vbpermq2 {}
- const vbll __builtin_altivec_vcmpequd (vull, vull);
- VCMPEQUD vector_eqv2di {}
-
- const int __builtin_altivec_vcmpequd_p (int, vsll, vsll);
- VCMPEQUD_P vector_eq_v2di_p {pred}
-
- const vsll __builtin_altivec_vcmpgtsd (vsll, vsll);
- VCMPGTSD vector_gtv2di {}
-
- const int __builtin_altivec_vcmpgtsd_p (int, vsll, vsll);
- VCMPGTSD_P vector_gt_v2di_p {pred}
-
- const vsll __builtin_altivec_vcmpgtud (vull, vull);
- VCMPGTUD vector_gtuv2di {}
-
- const int __builtin_altivec_vcmpgtud_p (int, vull, vull);
- VCMPGTUD_P vector_gtu_v2di_p {pred}
-
const vsll __builtin_altivec_vmaxsd (vsll, vsll);
VMAXSD smaxv2di3 {}
@@ -2253,18 +2254,6 @@
const vsi __builtin_altivec_vmrgow_v4si (vsi, vsi);
VMRGOW_V4SI p8_vmrgow_v4si {}
- const vsll __builtin_altivec_vmulesw (vsi, vsi);
- VMULESW vec_widen_smult_even_v4si {}
-
- const vull __builtin_altivec_vmuleuw (vui, vui);
- VMULEUW vec_widen_umult_even_v4si {}
-
- const vsll __builtin_altivec_vmulosw (vsi, vsi);
- VMULOSW vec_widen_smult_odd_v4si {}
-
- const vull __builtin_altivec_vmulouw (vui, vui);
- VMULOUW vec_widen_umult_odd_v4si {}
-
const vsc __builtin_altivec_vpermxor (vsc, vsc, vsc);
VPERMXOR altivec_vpermxor {}
@@ -2296,13 +2285,13 @@
; const vull __builtin_altivec_vpmsumw (vui, vui);
; VPMSUMW crypto_vpmsumw {}
- const vsc __builtin_altivec_vpopcntb (vsc);
+ const vuc __builtin_altivec_vpopcntb (vsc);
VPOPCNTB popcountv16qi2 {}
- const vsll __builtin_altivec_vpopcntd (vsll);
+ const vull __builtin_altivec_vpopcntd (vsll);
VPOPCNTD popcountv2di2 {}
- const vss __builtin_altivec_vpopcnth (vss);
+ const vus __builtin_altivec_vpopcnth (vss);
VPOPCNTH popcountv8hi2 {}
const vuc __builtin_altivec_vpopcntub (vuc);
@@ -2317,7 +2306,7 @@
const vui __builtin_altivec_vpopcntuw (vui);
VPOPCNTUW popcountv4si2 {}
- const vsi __builtin_altivec_vpopcntw (vsi);
+ const vui __builtin_altivec_vpopcntw (vsi);
VPOPCNTW popcountv4si2 {}
const vsll __builtin_altivec_vrld (vsll, vull);
@@ -2716,10 +2705,10 @@
const vuc __builtin_vsx_insert4b (vsi, vuc, const int[0,12]);
INSERT4B insert4b {}
- const vd __builtin_vsx_insert_exp_dp (vop, vull);
+ const vd __builtin_vsx_insert_exp_dp (vd, vd);
VIEDP xviexpdp {}
- const vf __builtin_vsx_insert_exp_sp (vop, vui);
+ const vf __builtin_vsx_insert_exp_sp (vf, vf);
VIESP xviexpsp {}
const signed int __builtin_vsx_scalar_cmp_exp_dp_eq (double, double);
@@ -2833,13 +2822,13 @@
void __builtin_altivec_xst_len_r (vsc, void *, long long);
XST_LEN_R xst_len_r {}
- void __builtin_altivec_stxvl (vop, void *, long long);
+ void __builtin_altivec_stxvl (vuc, void *, long long);
STXVL stxvl {}
const signed int __builtin_scalar_byte_in_set (unsigned char, unsigned long long);
CMPEQB cmpeqb {}
- pure vop __builtin_vsx_lxvl (const void *, unsigned long long);
+ pure vuc __builtin_vsx_lxvl (const void *, unsigned long long);
LXVL lxvl {}
const unsigned int __builtin_vsx_scalar_extract_exp (double);
@@ -3374,7 +3363,7 @@
const vus __builtin_vsx_xxblend_v8hi (vus, vus, vus);
VXXBLEND_V8HI xxblend_v8hi {}
- const vop __builtin_vsx_xxeval (vop, vop, vop, const int <8>);
+ const vull __builtin_vsx_xxeval (vull, vull, vull, const int <8>);
XXEVAL xxeval {}
const vuc __builtin_vsx_xxgenpcvm_v16qi (vuc, const int <2>);
diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c
index 96d20f8d601..15caa86e20c 100644
--- a/gcc/config/rs6000/rs6000-c.c
+++ b/gcc/config/rs6000/rs6000-c.c
@@ -2965,7 +2965,6 @@ altivec_resolve_new_overloaded_builtin (location_t loc, tree fndecl,
break;
}
}
- gcc_assert (unsupported_builtin);
}
if (unsupported_builtin)
diff --git a/gcc/config/rs6000/rs6000-call.c b/gcc/config/rs6000/rs6000-call.c
index 136be4c2753..8177035ac8c 100644
--- a/gcc/config/rs6000/rs6000-call.c
+++ b/gcc/config/rs6000/rs6000-call.c
@@ -15671,6 +15671,7 @@ rs6000_init_builtins (void)
= build_pointer_type (build_qualified_type (unsigned_V4SI_type_node,
TYPE_QUAL_CONST));
+ /* #### Should just always be long long??? */
unsigned_V2DI_type_node = rs6000_vector_type (TARGET_POWERPC64
? "__vector unsigned long"
: "__vector unsigned long long",
@@ -15758,10 +15759,10 @@ rs6000_init_builtins (void)
= build_pointer_type (build_qualified_type (uintDI_type_internal_node,
TYPE_QUAL_CONST));
ptr_intTI_type_node
- = build_pointer_type (build_qualified_type (intDI_type_internal_node,
+ = build_pointer_type (build_qualified_type (intTI_type_internal_node,
TYPE_QUAL_CONST));
ptr_uintTI_type_node
- = build_pointer_type (build_qualified_type (uintDI_type_internal_node,
+ = build_pointer_type (build_qualified_type (uintTI_type_internal_node,
TYPE_QUAL_CONST));
ptr_long_integer_type_node
= build_pointer_type
diff --git a/gcc/config/rs6000/rs6000-gen-builtins.c b/gcc/config/rs6000/rs6000-gen-builtins.c
index 6405b0f7a56..8f129f47d8c 100644
--- a/gcc/config/rs6000/rs6000-gen-builtins.c
+++ b/gcc/config/rs6000/rs6000-gen-builtins.c
@@ -317,7 +317,6 @@ struct typeinfo {
char isbool;
char ispixel;
char ispointer;
- char isopaque;
basetype base;
restriction restr;
int val1;
@@ -474,7 +473,6 @@ static typemap type_map[TYPE_MAP_SIZE] =
{ "if", "ibm128_float" },
{ "ld", "long_double" },
{ "lg", "long_integer" },
- { "opaque", "opaque_V4SI" },
{ "pbv16qi", "ptr_bool_V16QI" },
{ "pbv2di", "ptr_bool_V2DI" },
{ "pbv4si", "ptr_bool_V4SI" },
@@ -972,7 +970,6 @@ match_type (typeinfo *typedata, int voidok)
vd vector double
v256 __vector_pair
v512 __vector_quad
- vop opaque vector (matches all vectors)
For simplicity, We don't support "short int" and "long long int".
We don't support a <basetype> of "bool", "long double", or "_Float16",
@@ -1156,11 +1153,6 @@ match_type (typeinfo *typedata, int voidok)
handle_pointer (typedata);
return 1;
}
- else if (!strcmp (token, "vop"))
- {
- typedata->isopaque = 1;
- return 1;
- }
else if (!strcmp (token, "signed"))
typedata->issigned = 1;
else if (!strcmp (token, "unsigned"))
@@ -1549,20 +1541,12 @@ construct_fntype_id (prototype *protoptr)
buf[bufi++] = 'v';
else
{
- if (protoptr->rettype.isopaque)
- {
- memcpy (&buf[bufi], "opaque", 6);
- bufi += 6;
- }
+ if (protoptr->rettype.isunsigned)
+ buf[bufi++] = 'u';
+ if (protoptr->rettype.isvector)
+ complete_vector_type (&protoptr->rettype, buf, &bufi);
else
- {
- if (protoptr->rettype.isunsigned)
- buf[bufi++] = 'u';
- if (protoptr->rettype.isvector)
- complete_vector_type (&protoptr->rettype, buf, &bufi);
- else
- complete_base_type (&protoptr->rettype, buf, &bufi);
- }
+ complete_base_type (&protoptr->rettype, buf, &bufi);
}
memcpy (&buf[bufi], "_ftype", 6);
@@ -1608,21 +1592,13 @@ construct_fntype_id (prototype *protoptr)
else
buf[bufi++] = 'p';
}
- if (argptr->info.isopaque)
- {
- assert (!argptr->info.ispointer);
- memcpy (&buf[bufi], "opaque", 6);
- bufi += 6;
- }
+
+ if (argptr->info.isunsigned)
+ buf[bufi++] = 'u';
+ if (argptr->info.isvector)
+ complete_vector_type (&argptr->info, buf, &bufi);
else
- {
- if (argptr->info.isunsigned)
- buf[bufi++] = 'u';
- if (argptr->info.isvector)
- complete_vector_type (&argptr->info, buf, &bufi);
- else
- complete_base_type (&argptr->info, buf, &bufi);
- }
+ complete_base_type (&argptr->info, buf, &bufi);
}
assert (!argptr);
}
@@ -1965,8 +1941,7 @@ parse_ovld_entry ()
/* Check for an optional overload id. Usually we use the builtin
function id for that purpose, but sometimes we need multiple
- overload entries for the same builtin id when we use opaque
- vector parameter and return types, and it needs to be unique. */
+ overload entries for the same builtin id, and it needs to be unique. */
consume_whitespace ();
if (linebuf[pos] != '\n')
{
diff --git a/gcc/config/rs6000/rs6000-overload.def b/gcc/config/rs6000/rs6000-overload.def
index 66f5836c444..ec884b63388 100644
--- a/gcc/config/rs6000/rs6000-overload.def
+++ b/gcc/config/rs6000/rs6000-overload.def
@@ -257,7 +257,7 @@
VADDUWM VADDUWM_VSI_VBI
vui __builtin_vec_add (vbi, vui);
VADDUWM VADDUWM_VBI_VUI
- vui __builtin_vec_add (vbi, vui);
+ vui __builtin_vec_add (vui, vbi);
VADDUWM VADDUWM_VUI_VBI
vsll __builtin_vec_add (vbll, vsll);
VADDUDM VADDUDM_VBLL_VSLL
@@ -382,7 +382,7 @@
VAND_V16QI_UNS VAND_VBC_VUC
vss __builtin_vec_and (vss, vbs);
VAND_V8HI VAND_VSS_VBS
- vss __builtin_vec_and (vss, vbs);
+ vss __builtin_vec_and (vbs, vss);
VAND_V8HI VAND_VBS_VSS
vus __builtin_vec_and (vus, vbs);
VAND_V8HI_UNS VAND_VUS_VBS
@@ -1606,9 +1606,9 @@
[VEC_FLOAT, vec_float, __builtin_vec_float]
vf __builtin_vec_float (vsi);
- XVCVSXWSP_V4SF
+ XVCVSXWSP
vf __builtin_vec_float (vui);
- XVCVUXWSP_V4SF
+ XVCVUXWSP
[VEC_FLOAT2, vec_float2, __builtin_vec_float2]
vf __builtin_vec_float2 (vsll, vsll);
@@ -1634,9 +1634,10 @@
vf __builtin_vec_floato (vd);
FLOATO_V2DF
+; #### XVRSPIM{TARGET_VSX}; VRFIM
[VEC_FLOOR, vec_floor, __builtin_vec_floor]
vf __builtin_vec_floor (vf);
- XVRSPIM
+ VRFIM
vd __builtin_vec_floor (vd);
XVRDPIM
@@ -2118,7 +2119,7 @@
VMLADDUHM VMLADDUHM_VSSVUS
vss __builtin_vec_madd (vus, vss, vss);
VMLADDUHM VMLADDUHM_VUSVSS
- vus __builtin_vec_madd (vss, vus, vus);
+ vus __builtin_vec_madd (vus, vus, vus);
VMLADDUHM VMLADDUHM_VUS
vf __builtin_vec_madd (vf, vf, vf);
VMADDFP
@@ -2896,19 +2897,19 @@
VPMSUMD VPMSUMD_V
[VEC_POPCNT, vec_popcnt, __builtin_vec_vpopcnt, _ARCH_PWR8]
- vsc __builtin_vec_vpopcnt (vsc);
+ vuc __builtin_vec_vpopcnt (vsc);
VPOPCNTB
vuc __builtin_vec_vpopcnt (vuc);
VPOPCNTUB
- vss __builtin_vec_vpopcnt (vss);
+ vus __builtin_vec_vpopcnt (vss);
VPOPCNTH
vus __builtin_vec_vpopcnt (vus);
VPOPCNTUH
- vsi __builtin_vec_vpopcnt (vsi);
+ vui __builtin_vec_vpopcnt (vsi);
VPOPCNTW
vui __builtin_vec_vpopcnt (vui);
VPOPCNTUW
- vsll __builtin_vec_vpopcnt (vsll);
+ vull __builtin_vec_vpopcnt (vsll);
VPOPCNTD
vull __builtin_vec_vpopcnt (vull);
VPOPCNTUD
@@ -3082,9 +3083,10 @@
vull __builtin_vec_rlnm (vull, vull);
VRLDNM
+; #### XVRSPI{TARGET_VSX};VRFIN
[VEC_ROUND, vec_round, __builtin_vec_round]
vf __builtin_vec_round (vf);
- XVRSPI
+ VRFIN
vd __builtin_vec_round (vd);
XVRDPI
@@ -3193,11 +3195,11 @@
VEC_VSIGNED2_V2DF
[VEC_SIGNEDE, vec_signede, __builtin_vec_vsignede]
- vui __builtin_vec_vsignede (vd);
+ vsi __builtin_vec_vsignede (vd);
VEC_VSIGNEDE_V2DF
[VEC_SIGNEDO, vec_signedo, __builtin_vec_vsignedo]
- vui __builtin_vec_vsignedo (vd);
+ vsi __builtin_vec_vsignedo (vd);
VEC_VSIGNEDO_V2DF
[VEC_SL, vec_sl, __builtin_vec_sl]
@@ -3356,8 +3358,8 @@
VSL VSL_VBLL_VUC
vbll __builtin_vec_sll (vbll, vus);
VSL VSL_VBLL_VUS
- vbll __builtin_vec_sll (vbll, vui);
- VSL VSL_VBLL_VUI
+ vbll __builtin_vec_sll (vbll, vull);
+ VSL VSL_VBLL_VULL
[VEC_SLO, vec_slo, __builtin_vec_slo]
vsc __builtin_vec_slo (vsc, vsc);
@@ -3686,14 +3688,10 @@
STVX_V4SI STVX_VSI
void __builtin_vec_st (vsi, signed long long, signed int *);
STVX_V4SI STVX_SI
- void __builtin_vec_st (vsi, signed long long, signed long *);
- STVX_V4SI STVX_SL
void __builtin_vec_st (vui, signed long long, vui *);
STVX_V4SI STVX_VUI
void __builtin_vec_st (vui, signed long long, unsigned int *);
STVX_V4SI STVX_UI
- void __builtin_vec_st (vui, signed long long, unsigned long *);
- STVX_V4SI STVX_UL
void __builtin_vec_st (vbi, signed long long, vbi *);
STVX_V4SI STVX_VBI
void __builtin_vec_st (vbi, signed long long, signed int *);
@@ -4190,7 +4188,7 @@
[VEC_SUM4S, vec_sum4s, __builtin_vec_sum4s]
vui __builtin_vec_sum4s (vuc, vui);
VSUM4UBS
- vsi __builtin_vec_sum4s (vsc, vui);
+ vsi __builtin_vec_sum4s (vsc, vsi);
VSUM4SBS
vsi __builtin_vec_sum4s (vss, vsi);
VSUM4SHS
@@ -4219,9 +4217,10 @@
signed int __builtin_vec_xvtlsbb_all_zeros (vuc);
XVTLSBB_ZEROS
+; #### XVRSPIZ{TARGET_VSX}; VRFIZ
[VEC_TRUNC, vec_trunc, __builtin_vec_trunc]
vf __builtin_vec_trunc (vf);
- XVRSPIZ
+ VRFIZ
vd __builtin_vec_trunc (vd);
XVRDPIZ
@@ -4286,13 +4285,13 @@
DOUBLEL_V4SF VUPKLF
[VEC_UNSIGNED, vec_unsigned, __builtin_vec_vunsigned]
- vsi __builtin_vec_vunsigned (vf);
+ vui __builtin_vec_vunsigned (vf);
VEC_VUNSIGNED_V4SF
- vsll __builtin_vec_vunsigned (vd);
+ vull __builtin_vec_vunsigned (vd);
VEC_VUNSIGNED_V2DF
[VEC_UNSIGNED2, vec_unsigned2, __builtin_vec_vunsigned2]
- vsi __builtin_vec_vunsigned2 (vd, vd);
+ vui __builtin_vec_vunsigned2 (vd, vd);
VEC_VUNSIGNED2_V2DF
[VEC_UNSIGNEDE, vec_unsignede, __builtin_vec_vunsignede]
diff --git a/gcc/testsuite/gcc.dg/vmx/ops.c b/gcc/testsuite/gcc.dg/vmx/ops.c
index 735710819f9..b8f80930078 100644
--- a/gcc/testsuite/gcc.dg/vmx/ops.c
+++ b/gcc/testsuite/gcc.dg/vmx/ops.c
@@ -317,8 +317,6 @@ void f2() {
*var_vec_b16++ = vec_cmpgt(var_vec_u16[0], var_vec_u16[1]);
*var_vec_b16++ = vec_ld(var_int[0], var_vec_b16_ptr[1]);
*var_vec_b16++ = vec_ldl(var_int[0], var_vec_b16_ptr[1]);
- *var_vec_b16++ = vec_lvx(var_int[0], var_vec_b16_ptr[1]);
- *var_vec_b16++ = vec_lvxl(var_int[0], var_vec_b16_ptr[1]);
*var_vec_b16++ = vec_mergeh(var_vec_b16[0], var_vec_b16[1]);
*var_vec_b16++ = vec_mergel(var_vec_b16[0], var_vec_b16[1]);
*var_vec_b16++ = vec_nor(var_vec_b16[0], var_vec_b16[1]);
@@ -357,8 +355,6 @@ void f3() {
*var_vec_b32++ = vec_cmpgt(var_vec_u32[0], var_vec_u32[1]);
*var_vec_b32++ = vec_ld(var_int[0], var_vec_b32_ptr[1]);
*var_vec_b32++ = vec_ldl(var_int[0], var_vec_b32_ptr[1]);
- *var_vec_b32++ = vec_lvx(var_int[0], var_vec_b32_ptr[1]);
- *var_vec_b32++ = vec_lvxl(var_int[0], var_vec_b32_ptr[1]);
*var_vec_b32++ = vec_mergeh(var_vec_b32[0], var_vec_b32[1]);
*var_vec_b32++ = vec_mergel(var_vec_b32[0], var_vec_b32[1]);
*var_vec_b32++ = vec_nor(var_vec_b32[0], var_vec_b32[1]);
@@ -389,8 +385,6 @@ void f4() {
*var_vec_b8++ = vec_cmpgt(var_vec_u8[0], var_vec_u8[1]);
*var_vec_b8++ = vec_ld(var_int[0], var_vec_b8_ptr[1]);
*var_vec_b8++ = vec_ldl(var_int[0], var_vec_b8_ptr[1]);
- *var_vec_b8++ = vec_lvx(var_int[0], var_vec_b8_ptr[1]);
- *var_vec_b8++ = vec_lvxl(var_int[0], var_vec_b8_ptr[1]);
}
void f5() {
*var_vec_b8++ = vec_mergeh(var_vec_b8[0], var_vec_b8[1]);
@@ -506,11 +500,6 @@ void f6() {
*var_vec_f32++ = vec_ldl(var_int[0], var_float_ptr[1]);
*var_vec_f32++ = vec_ldl(var_int[0], var_vec_f32_ptr[1]);
*var_vec_f32++ = vec_loge(var_vec_f32[0]);
- *var_vec_f32++ = vec_lvewx(var_int[0], var_float_ptr[1]);
- *var_vec_f32++ = vec_lvx(var_int[0], var_float_ptr[1]);
- *var_vec_f32++ = vec_lvx(var_int[0], var_vec_f32_ptr[1]);
- *var_vec_f32++ = vec_lvxl(var_int[0], var_float_ptr[1]);
- *var_vec_f32++ = vec_lvxl(var_int[0], var_vec_f32_ptr[1]);
*var_vec_f32++ = vec_madd(var_vec_f32[0], var_vec_f32[1], var_vec_f32[2]);
*var_vec_f32++ = vec_max(var_vec_f32[0], var_vec_f32[1]);
*var_vec_f32++ = vec_mergeh(var_vec_f32[0], var_vec_f32[1]);
@@ -562,8 +551,6 @@ void f9() {
*var_vec_f32++ = vec_xor(var_vec_f32[0], var_vec_f32[1]);
*var_vec_p16++ = vec_ld(var_int[0], var_vec_p16_ptr[1]);
*var_vec_p16++ = vec_ldl(var_int[0], var_vec_p16_ptr[1]);
- *var_vec_p16++ = vec_lvx(var_int[0], var_vec_p16_ptr[1]);
- *var_vec_p16++ = vec_lvxl(var_int[0], var_vec_p16_ptr[1]);
*var_vec_p16++ = vec_mergeh(var_vec_p16[0], var_vec_p16[1]);
*var_vec_p16++ = vec_mergel(var_vec_p16[0], var_vec_p16[1]);
*var_vec_p16++ = vec_packpx(var_vec_u32[0], var_vec_u32[1]);
@@ -622,11 +609,6 @@ void f10() {
*var_vec_s16++ = vec_lde(var_int[0], var_short_ptr[1]);
*var_vec_s16++ = vec_ldl(var_int[0], var_short_ptr[1]);
*var_vec_s16++ = vec_ldl(var_int[0], var_vec_s16_ptr[1]);
- *var_vec_s16++ = vec_lvehx(var_int[0], var_short_ptr[1]);
- *var_vec_s16++ = vec_lvx(var_int[0], var_short_ptr[1]);
- *var_vec_s16++ = vec_lvx(var_int[0], var_vec_s16_ptr[1]);
- *var_vec_s16++ = vec_lvxl(var_int[0], var_short_ptr[1]);
- *var_vec_s16++ = vec_lvxl(var_int[0], var_vec_s16_ptr[1]);
*var_vec_s16++ = vec_madds(var_vec_s16[0], var_vec_s16[1], var_vec_s16[2]);
*var_vec_s16++ = vec_max(var_vec_b16[0], var_vec_s16[1]);
*var_vec_s16++ = vec_max(var_vec_s16[0], var_vec_b16[1]);
@@ -787,11 +769,6 @@ void f13() {
*var_vec_s32++ = vec_lde(var_int[0], var_int_ptr[1]);
*var_vec_s32++ = vec_ldl(var_int[0], var_int_ptr[1]);
*var_vec_s32++ = vec_ldl(var_int[0], var_vec_s32_ptr[1]);
- *var_vec_s32++ = vec_lvewx(var_int[0], var_int_ptr[1]);
- *var_vec_s32++ = vec_lvx(var_int[0], var_int_ptr[1]);
- *var_vec_s32++ = vec_lvx(var_int[0], var_vec_s32_ptr[1]);
- *var_vec_s32++ = vec_lvxl(var_int[0], var_int_ptr[1]);
- *var_vec_s32++ = vec_lvxl(var_int[0], var_vec_s32_ptr[1]);
*var_vec_s32++ = vec_max(var_vec_b32[0], var_vec_s32[1]);
*var_vec_s32++ = vec_max(var_vec_s32[0], var_vec_b32[1]);
*var_vec_s32++ = vec_max(var_vec_s32[0], var_vec_s32[1]);
@@ -919,11 +896,6 @@ void f17() {
*var_vec_s8++ = vec_lde(var_int[0], var_signed_char_ptr[1]);
*var_vec_s8++ = vec_ldl(var_int[0], var_signed_char_ptr[1]);
*var_vec_s8++ = vec_ldl(var_int[0], var_vec_s8_ptr[1]);
- *var_vec_s8++ = vec_lvebx(var_int[0], var_signed_char_ptr[1]);
- *var_vec_s8++ = vec_lvx(var_int[0], var_signed_char_ptr[1]);
- *var_vec_s8++ = vec_lvx(var_int[0], var_vec_s8_ptr[1]);
- *var_vec_s8++ = vec_lvxl(var_int[0], var_signed_char_ptr[1]);
- *var_vec_s8++ = vec_lvxl(var_int[0], var_vec_s8_ptr[1]);
*var_vec_s8++ = vec_max(var_vec_b8[0], var_vec_s8[1]);
*var_vec_s8++ = vec_max(var_vec_s8[0], var_vec_b8[1]);
*var_vec_s8++ = vec_max(var_vec_s8[0], var_vec_s8[1]);
@@ -1050,11 +1022,6 @@ void f19() {
*var_vec_u16++ = vec_lde(var_int[0], var_unsigned_short_ptr[1]);
*var_vec_u16++ = vec_ldl(var_int[0], var_unsigned_short_ptr[1]);
*var_vec_u16++ = vec_ldl(var_int[0], var_vec_u16_ptr[1]);
- *var_vec_u16++ = vec_lvehx(var_int[0], var_unsigned_short_ptr[1]);
- *var_vec_u16++ = vec_lvx(var_int[0], var_unsigned_short_ptr[1]);
- *var_vec_u16++ = vec_lvx(var_int[0], var_vec_u16_ptr[1]);
- *var_vec_u16++ = vec_lvxl(var_int[0], var_unsigned_short_ptr[1]);
- *var_vec_u16++ = vec_lvxl(var_int[0], var_vec_u16_ptr[1]);
*var_vec_u16++ = vec_max(var_vec_b16[0], var_vec_u16[1]);
*var_vec_u16++ = vec_max(var_vec_u16[0], var_vec_b16[1]);
*var_vec_u16++ = vec_max(var_vec_u16[0], var_vec_u16[1]);
@@ -1213,11 +1180,6 @@ void f22() {
*var_vec_u32++ = vec_lde(var_int[0], var_unsigned_int_ptr[1]);
*var_vec_u32++ = vec_ldl(var_int[0], var_unsigned_int_ptr[1]);
*var_vec_u32++ = vec_ldl(var_int[0], var_vec_u32_ptr[1]);
- *var_vec_u32++ = vec_lvewx(var_int[0], var_unsigned_int_ptr[1]);
- *var_vec_u32++ = vec_lvx(var_int[0], var_unsigned_int_ptr[1]);
- *var_vec_u32++ = vec_lvx(var_int[0], var_vec_u32_ptr[1]);
- *var_vec_u32++ = vec_lvxl(var_int[0], var_unsigned_int_ptr[1]);
- *var_vec_u32++ = vec_lvxl(var_int[0], var_vec_u32_ptr[1]);
*var_vec_u32++ = vec_max(var_vec_b32[0], var_vec_u32[1]);
*var_vec_u32++ = vec_max(var_vec_u32[0], var_vec_b32[1]);
*var_vec_u32++ = vec_max(var_vec_u32[0], var_vec_u32[1]);
@@ -1341,7 +1303,6 @@ void f25() {
*var_vec_u8++ = vec_lde(var_int[0], var_unsigned_char_ptr[1]);
*var_vec_u8++ = vec_ldl(var_int[0], var_unsigned_char_ptr[1]);
*var_vec_u8++ = vec_ldl(var_int[0], var_vec_u8_ptr[1]);
- *var_vec_u8++ = vec_lvebx(var_int[0], var_unsigned_char_ptr[1]);
*var_vec_u8++ = vec_lvsl(var_int[0], var_float_ptr[1]);
*var_vec_u8++ = vec_lvsl(var_int[0], var_int_ptr[1]);
*var_vec_u8++ = vec_lvsl(var_int[0], var_short_ptr[1]);
@@ -1356,12 +1317,8 @@ void f25() {
*var_vec_u8++ = vec_lvsr(var_int[0], var_unsigned_char_ptr[1]);
*var_vec_u8++ = vec_lvsr(var_int[0], var_unsigned_int_ptr[1]);
*var_vec_u8++ = vec_lvsr(var_int[0], var_unsigned_short_ptr[1]);
- *var_vec_u8++ = vec_lvx(var_int[0], var_unsigned_char_ptr[1]);
- *var_vec_u8++ = vec_lvx(var_int[0], var_vec_u8_ptr[1]);
}
void f26() {
- *var_vec_u8++ = vec_lvxl(var_int[0], var_unsigned_char_ptr[1]);
- *var_vec_u8++ = vec_lvxl(var_int[0], var_vec_u8_ptr[1]);
*var_vec_u8++ = vec_max(var_vec_b8[0], var_vec_u8[1]);
*var_vec_u8++ = vec_max(var_vec_u8[0], var_vec_b8[1]);
*var_vec_u8++ = vec_max(var_vec_u8[0], var_vec_u8[1]);
@@ -2353,47 +2310,4 @@ void f37() {
vec_stl(var_vec_u32[0], var_int[1], var_vec_u32_ptr[2]);
vec_stl(var_vec_u8[0], var_int[1], var_unsigned_char_ptr[2]);
vec_stl(var_vec_u8[0], var_int[1], var_vec_u8_ptr[2]);
- vec_stvebx(var_vec_s8[0], var_int[1], var_signed_char_ptr[2]);
- vec_stvebx(var_vec_u8[0], var_int[1], var_unsigned_char_ptr[2]);
- vec_stvehx(var_vec_s16[0], var_int[1], var_short_ptr[2]);
- vec_stvehx(var_vec_u16[0], var_int[1], var_unsigned_short_ptr[2]);
- vec_stvewx(var_vec_f32[0], var_int[1], var_float_ptr[2]);
- vec_stvewx(var_vec_s32[0], var_int[1], var_int_ptr[2]);
- vec_stvewx(var_vec_u32[0], var_int[1], var_unsigned_int_ptr[2]);
- vec_stvx(var_vec_b16[0], var_int[1], var_vec_b16_ptr[2]);
- vec_stvx(var_vec_b32[0], var_int[1], var_vec_b32_ptr[2]);
- vec_stvx(var_vec_b8[0], var_int[1], var_vec_b8_ptr[2]);
- vec_stvx(var_vec_f32[0], var_int[1], var_float_ptr[2]);
- vec_stvx(var_vec_f32[0], var_int[1], var_vec_f32_ptr[2]);
- vec_stvx(var_vec_p16[0], var_int[1], var_vec_p16_ptr[2]);
- vec_stvx(var_vec_s16[0], var_int[1], var_short_ptr[2]);
- vec_stvx(var_vec_s16[0], var_int[1], var_vec_s16_ptr[2]);
- vec_stvx(var_vec_s32[0], var_int[1], var_int_ptr[2]);
- vec_stvx(var_vec_s32[0], var_int[1], var_vec_s32_ptr[2]);
- vec_stvx(var_vec_s8[0], var_int[1], var_signed_char_ptr[2]);
- vec_stvx(var_vec_s8[0], var_int[1], var_vec_s8_ptr[2]);
- vec_stvx(var_vec_u16[0], var_int[1], var_unsigned_short_ptr[2]);
- vec_stvx(var_vec_u16[0], var_int[1], var_vec_u16_ptr[2]);
- vec_stvx(var_vec_u32[0], var_int[1], var_unsigned_int_ptr[2]);
- vec_stvx(var_vec_u32[0], var_int[1], var_vec_u32_ptr[2]);
- vec_stvx(var_vec_u8[0], var_int[1], var_unsigned_char_ptr[2]);
- vec_stvx(var_vec_u8[0], var_int[1], var_vec_u8_ptr[2]);
- vec_stvxl(var_vec_b16[0], var_int[1], var_vec_b16_ptr[2]);
- vec_stvxl(var_vec_b32[0], var_int[1], var_vec_b32_ptr[2]);
- vec_stvxl(var_vec_b8[0], var_int[1], var_vec_b8_ptr[2]);
- vec_stvxl(var_vec_f32[0], var_int[1], var_float_ptr[2]);
- vec_stvxl(var_vec_f32[0], var_int[1], var_vec_f32_ptr[2]);
- vec_stvxl(var_vec_p16[0], var_int[1], var_vec_p16_ptr[2]);
- vec_stvxl(var_vec_s16[0], var_int[1], var_short_ptr[2]);
- vec_stvxl(var_vec_s16[0], var_int[1], var_vec_s16_ptr[2]);
- vec_stvxl(var_vec_s32[0], var_int[1], var_int_ptr[2]);
- vec_stvxl(var_vec_s32[0], var_int[1], var_vec_s32_ptr[2]);
- vec_stvxl(var_vec_s8[0], var_int[1], var_signed_char_ptr[2]);
- vec_stvxl(var_vec_s8[0], var_int[1], var_vec_s8_ptr[2]);
- vec_stvxl(var_vec_u16[0], var_int[1], var_unsigned_short_ptr[2]);
- vec_stvxl(var_vec_u16[0], var_int[1], var_vec_u16_ptr[2]);
- vec_stvxl(var_vec_u32[0], var_int[1], var_unsigned_int_ptr[2]);
- vec_stvxl(var_vec_u32[0], var_int[1], var_vec_u32_ptr[2]);
- vec_stvxl(var_vec_u8[0], var_int[1], var_unsigned_char_ptr[2]);
- vec_stvxl(var_vec_u8[0], var_int[1], var_vec_u8_ptr[2]);
}
diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-7.c b/gcc/testsuite/gcc.target/powerpc/altivec-7.c
index 42c04a1ed79..0cef426fcd9 100644
--- a/gcc/testsuite/gcc.target/powerpc/altivec-7.c
+++ b/gcc/testsuite/gcc.target/powerpc/altivec-7.c
@@ -26,25 +26,23 @@ int main ()
{
*vecfloat++ = vec_andc((vector bool int)vecint[0], vecfloat[1]);
*vecfloat++ = vec_andc(vecfloat[0], (vector bool int)vecint[1]);
- *vecfloat++ = vec_vxor((vector bool int)vecint[0], vecfloat[1]);
- *vecfloat++ = vec_vxor(vecfloat[0], (vector bool int)vecint[1]);
+ *vecfloat++ = vec_xor((vector bool int)vecint[0], vecfloat[1]);
+ *vecfloat++ = vec_xor(vecfloat[0], (vector bool int)vecint[1]);
*varpixel++ = vec_packpx(vecuint[0], vecuint[1]);
- *varpixel++ = vec_vpkpx(vecuint[0], vecuint[1]);
- *vecshort++ = vec_vmulesb(vecchar[0], vecchar[1]);
- *vecshort++ = vec_vmulosb(vecchar[0], vecchar[1]);
+ *vecshort++ = vec_mule(vecchar[0], vecchar[1]);
+ *vecshort++ = vec_mulo(vecchar[0], vecchar[1]);
*vecint++ = vec_ld(var_int[0], intp[1]);
*vecint++ = vec_lde(var_int[0], intp[1]);
*vecint++ = vec_ldl(var_int[0], intp[1]);
- *vecint++ = vec_lvewx(var_int[0], intp[1]);
*vecint++ = vec_unpackh(vecshort[0]);
*vecint++ = vec_unpackl(vecshort[0]);
*vecushort++ = vec_andc((vector bool short)vecshort[0], vecushort[1]);
*vecushort++ = vec_andc(vecushort[0], (vector bool short)vecshort[1]);
- *vecushort++ = vec_vxor((vector bool short)vecshort[0], vecushort[1]);
- *vecushort++ = vec_vxor(vecushort[0], (vector bool short)vecshort[1]);
+ *vecushort++ = vec_xor((vector bool short)vecshort[0], vecushort[1]);
+ *vecushort++ = vec_xor(vecushort[0], (vector bool short)vecshort[1]);
*vecuint++ = vec_ld(var_int[0], uintp[1]);
*vecuint++ = vec_lvx(var_int[0], uintp[1]);
- *vecuint++ = vec_vmsumubm(vecuchar[0], vecuchar[1], vecuint[2]);
+ *vecuint++ = vec_msum(vecuchar[0], vecuchar[1], vecuint[2]);
*vecuchar++ = vec_xor(vecuchar[0], (vector unsigned char)vecchar[1]);
*vecubi++ = vec_unpackh(vecubsi[0]);
@@ -62,11 +60,10 @@ int main ()
/* Expected results:
vec_packpx vpkpx
- vec_vmulosb vmulesb
+ vec_mulo vmulesb
vec_ld lxv2x
vec_lde lvewx
vec_ldl lxvl
- vec_lvewx lvewx
vec_unpackh vupklsh
vec_unpackh vupklpx
vec_unpackh vupklsb
@@ -75,10 +72,10 @@ int main ()
vec_unpackl vupkhsb
vec_andc xxlnor (vnor AIX)
xxland (vand AIX)
- vec_vxor xxlxor
- vec_vmsumubm vmsumubm
- vec_vmulesb vmulosb
- vec_vmulosb vmulesb
+ vec_xor xxlxor
+ vec_msum vmsumubm
+ vec_mule vmulosb
+ vec_mulo vmulesb
vec_ld lvx
*/
@@ -89,7 +86,7 @@ int main ()
/* { dg-final { scan-assembler-times {\mlxv} 0 { target { ! powerpc_vsx } } } } */
/* { dg-final { scan-assembler-times {\mlvx\M} 0 { target powerpc_vsx } } } */
/* { dg-final { scan-assembler-times {\mlxv} 42 { target powerpc_vsx } } } */
-/* { dg-final { scan-assembler-times "lvewx" 2 } } */
+/* { dg-final { scan-assembler-times "lvewx" 1 } } */
/* { dg-final { scan-assembler-times "lvxl" 1 } } */
/* { dg-final { scan-assembler-times "vupklsh" 2 } } */
/* { dg-final { scan-assembler-times "vupkhsh" 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-2.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-2.c
index 7a1e8e8bd30..46d743a899b 100644
--- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-2.c
+++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-2.c
@@ -10,5 +10,5 @@ test_neg (float *p)
{
float source = *p;
- return __builtin_vec_scalar_test_neg (source); /* { dg-error "'__builtin_vsx_scalar_test_neg' requires" } */
+ return __builtin_vec_scalar_test_neg (source); /* { dg-error "'__builtin_vsx_scalar_test_neg_sp' requires" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-3.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-3.c
index c9b90927693..bfc892b116e 100644
--- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-3.c
@@ -10,5 +10,5 @@ test_neg (double *p)
{
double source = *p;
- return __builtin_vec_scalar_test_neg (source); /* { dg-error "'__builtin_vsx_scalar_test_neg' requires" } */
+ return __builtin_vec_scalar_test_neg (source); /* { dg-error "'__builtin_vsx_scalar_test_neg_dp' requires" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-5.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-5.c
index e70eb2d46f8..8c55c1cfb5c 100644
--- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-5.c
+++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-5.c
@@ -10,5 +10,5 @@ test_neg (__ieee128 *p)
{
__ieee128 source = *p;
- return __builtin_vec_scalar_test_neg (source); /* { dg-error "'__builtin_vsx_scalar_test_neg' requires" } */
+ return __builtin_vec_scalar_test_neg (source); /* { dg-error "'__builtin_vsx_scalar_test_neg_qp' requires" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-3-p9-runnable.c b/gcc/testsuite/gcc.target/powerpc/builtins-3-p9-runnable.c
index 44c0397c49a..e023076bac7 100644
--- a/gcc/testsuite/gcc.target/powerpc/builtins-3-p9-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/builtins-3-p9-runnable.c
@@ -73,10 +73,10 @@ int main() {
abort();
}
vfexpt = (vector float){1.0, -2.0, 0.0, 8.5};
- vfr = vec_extract_fp_from_shorth(vusha);
+ vfr = vec_extract_fp32_from_shorth(vusha);
#ifdef DEBUG
- printf ("vec_extract_fp_from_shorth\n");
+ printf ("vec_extract_fp32_from_shorth\n");
for (i=0; i<4; i++)
printf("result[%d] = %f; expected[%d] = %f\n",
i, vfr[i], i, vfexpt[i]);
@@ -88,10 +88,10 @@ int main() {
}
vfexpt = (vector float){1.5, 0.5, 1.25, -0.25};
- vfr = vec_extract_fp_from_shortl(vusha);
+ vfr = vec_extract_fp32_from_shortl(vusha);
#ifdef DEBUG
- printf ("\nvec_extract_fp_from_shortl\n");
+ printf ("\nvec_extract_fp32_from_shortl\n");
for (i=0; i<4; i++)
printf("result[%d] = %f; expected[%d] = %f\n",
i, vfr[i], i, vfexpt[i]);
^ permalink raw reply [flat|nested] 29+ messages in thread
* [gcc(refs/users/wschmidt/heads/builtins4)] rs6000: More bug fixes
@ 2021-02-07 18:18 William Schmidt
0 siblings, 0 replies; 29+ messages in thread
From: William Schmidt @ 2021-02-07 18:18 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:449fc24a2f1dae96d80ee66bfea303b0225fb203
commit 449fc24a2f1dae96d80ee66bfea303b0225fb203
Author: Bill Schmidt <wschmidt@linux.ibm.com>
Date: Fri Jan 8 17:08:42 2021 -0600
rs6000: More bug fixes
2021-01-08 Bill Schmidt <wschmidt@linux.ibm.com>
gcc/
* config/rs6000/rs6000-builtin-new.def (__builtin_altivec_vsr):
Fix argument types.
(__builtin_altivec_vsro): Likewise.
gcc/testsuite/
* gcc.target/powerpc/dfp/dtstsfi-11.c: Fix expected error message.
* gcc.target/powerpc/dfp/dtstsfi-16.c: Likewise.
* gcc.target/powerpc/dfp/dtstsfi-51.c: Likewise.
* gcc.target/powerpc/dfp/dtstsfi-56.c: Likewise.
* gcc.target/powerpc/dfp/dtstsfi-71.c: Likewise.
* gcc.target/powerpc/dfp/dtstsfi-76.c: Likewise.
Diff:
---
gcc/config/rs6000/rs6000-builtin-new.def | 4 ++--
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-11.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-16.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-31.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-36.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-51.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-56.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-71.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-76.c | 2 +-
9 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-builtin-new.def b/gcc/config/rs6000/rs6000-builtin-new.def
index 645d4b0425f..6fa121bb38d 100644
--- a/gcc/config/rs6000/rs6000-builtin-new.def
+++ b/gcc/config/rs6000/rs6000-builtin-new.def
@@ -933,7 +933,7 @@
const vsi __builtin_altivec_vspltw (vsi, const int<2>);
VSPLTW altivec_vspltw {}
- const vop __builtin_altivec_vsr (vop, vuc);
+ const vop __builtin_altivec_vsr (vop, vop);
VSR altivec_vsr {}
const vsc __builtin_altivec_vsrab (vsc, vuc);
@@ -951,7 +951,7 @@
const vss __builtin_altivec_vsrh (vss, vus);
VSRH vlshrv8hi3 {}
- const vop __builtin_altivec_vsro (vop, vuc);
+ const vop __builtin_altivec_vsro (vop, vop);
VSRO altivec_vsro {}
const vsi __builtin_altivec_vsrw (vsi, vui);
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-11.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-11.c
index b5bea3cf1a0..6338a0e4278 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-11.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-11.c
@@ -8,6 +8,6 @@ int doTestBCDSignificance (_Decimal64 *p)
{
_Decimal64 source = *p;
- return __builtin_dfp_dtstsfi_lt (5, source); /* { dg-error "'__builtin_dtstsfi_lt' requires" } */ /* { dg-error "'__builtin_dtstsfi_lt_dd' requires" } */
+ return __builtin_dfp_dtstsfi_lt (5, source); /* { dg-error "'__builtin_dtstsfi_lt_dd' requires" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-16.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-16.c
index c6a42f089e0..d889bdd385c 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-16.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-16.c
@@ -8,7 +8,7 @@ int doTestBCDSignificance (_Decimal128 *p)
{
_Decimal128 source = *p;
- return __builtin_dfp_dtstsfi_lt (5, source); /* { dg-error "'__builtin_dtstsfi_lt' requires" } */
+ return __builtin_dfp_dtstsfi_lt (5, source); /* { dg-error "'__builtin_dtstsfi_lt_td' requires" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-31.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-31.c
index 5d9d5d61b42..0d47cc27897 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-31.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-31.c
@@ -8,6 +8,6 @@ int doTestBCDSignificance (_Decimal64 *p)
{
_Decimal64 source = *p;
- return __builtin_dfp_dtstsfi_gt (5, source); /* { dg-error "'__builtin_dtstsfi_gt' requires" } */
+ return __builtin_dfp_dtstsfi_gt (5, source); /* { dg-error "'__builtin_dtstsfi_gt_dd' requires" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-36.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-36.c
index ca5e0098411..f070a0c4a7b 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-36.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-36.c
@@ -8,7 +8,7 @@ int doTestBCDSignificance (_Decimal128 *p)
{
_Decimal128 source = *p;
- return __builtin_dfp_dtstsfi_gt (5, source); /* { dg-error "'__builtin_dtstsfi_gt' requires" } */
+ return __builtin_dfp_dtstsfi_gt (5, source); /* { dg-error "'__builtin_dtstsfi_gt_td' requires" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-51.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-51.c
index 5e4f4964aaa..451a9e74c28 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-51.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-51.c
@@ -8,6 +8,6 @@ int doTestBCDSignificance (_Decimal64 *p)
{
_Decimal64 source = *p;
- return __builtin_dfp_dtstsfi_eq (5, source); /* { dg-error "'__builtin_dtstsfi_eq' requires" } */
+ return __builtin_dfp_dtstsfi_eq (5, source); /* { dg-error "'__builtin_dtstsfi_eq_dd' requires" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-56.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-56.c
index 02ff47441e5..d0833c80f60 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-56.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-56.c
@@ -8,7 +8,7 @@ int doTestBCDSignificance (_Decimal128 *p)
{
_Decimal128 source = *p;
- return __builtin_dfp_dtstsfi_eq (5, source); /* { dg-error "'__builtin_dtstsfi_eq' requires" } */
+ return __builtin_dfp_dtstsfi_eq (5, source); /* { dg-error "'__builtin_dtstsfi_eq_td' requires" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-71.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-71.c
index 6c64021a479..1a54150617e 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-71.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-71.c
@@ -8,6 +8,6 @@ int doTestBCDSignificance (_Decimal64 *p)
{
_Decimal64 source = *p;
- return __builtin_dfp_dtstsfi_ov (5, source); /* { dg-error "'__builtin_dtstsfi_ov' requires" } */
+ return __builtin_dfp_dtstsfi_ov (5, source); /* { dg-error "'__builtin_dtstsfi_ov_dd' requires" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-76.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-76.c
index 982ed5d79df..74269fac328 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-76.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-76.c
@@ -8,7 +8,7 @@ int doTestBCDSignificance (_Decimal128 *p)
{
_Decimal128 source = *p;
- return __builtin_dfp_dtstsfi_ov (5, source); /* { dg-error "'__builtin_dtstsfi_ov' requires" } */
+ return __builtin_dfp_dtstsfi_ov (5, source); /* { dg-error "'__builtin_dtstsfi_ov_td' requires" } */
}
^ permalink raw reply [flat|nested] 29+ messages in thread
* [gcc(refs/users/wschmidt/heads/builtins4)] rs6000: More bug fixes
@ 2021-02-07 18:17 William Schmidt
0 siblings, 0 replies; 29+ messages in thread
From: William Schmidt @ 2021-02-07 18:17 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:81f9be479db8a83927e659a7e892fe8ec9af3cc1
commit 81f9be479db8a83927e659a7e892fe8ec9af3cc1
Author: Bill Schmidt <wschmidt@linux.ibm.com>
Date: Fri Jan 8 14:42:22 2021 -0600
rs6000: More bug fixes
2021-01-08 Bill Schmidt <wschmidt@linux.ibm.com>
gcc/
* config/rs6000/emmintrin.h: Change deprecated built-in calls.
* config/rs6000/rs6000-builtin-new.def
(__builtin_altivec_vcmpgtud_p): Fix arguments.
(__builtin_altivec_vcmpaeb_p et al.): Remove {pred}.
gcc/testsuite/
* gcc.target/powerpc/dfp/dtstsfi-11.c: Add second expected error
message.
Diff:
---
gcc/config/rs6000/emmintrin.h | 30 +++++++++++------------
gcc/config/rs6000/rs6000-builtin-new.def | 26 ++++++++++----------
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-11.c | 2 +-
3 files changed, 29 insertions(+), 29 deletions(-)
diff --git a/gcc/config/rs6000/emmintrin.h b/gcc/config/rs6000/emmintrin.h
index ce1287edf78..9c4d5fa13c7 100644
--- a/gcc/config/rs6000/emmintrin.h
+++ b/gcc/config/rs6000/emmintrin.h
@@ -892,8 +892,8 @@ _mm_cvtpd_epi32 (__m128d __A)
#else
temp = vec_mergee (temp, temp);
#endif
- result = (__v4si) vec_vpkudum ((__vector long long) temp,
- (__vector long long) vzero);
+ result = (__v4si) vec_pack ((__vector long long) temp,
+ (__vector long long) vzero);
#else
{
const __v16qu pkperm = {0x00, 0x01, 0x02, 0x03, 0x08, 0x09, 0x0a, 0x0b,
@@ -931,8 +931,8 @@ _mm_cvtpd_ps (__m128d __A)
#else
temp = vec_mergee (temp, temp);
#endif
- result = (__v4sf) vec_vpkudum ((__vector long long) temp,
- (__vector long long) vzero);
+ result = (__v4sf) vec_pack ((__vector long long) temp,
+ (__vector long long) vzero);
#else
{
const __v16qu pkperm = {0x00, 0x01, 0x02, 0x03, 0x08, 0x09, 0x0a, 0x0b,
@@ -964,8 +964,8 @@ _mm_cvttpd_epi32 (__m128d __A)
#else
temp = vec_mergee (temp, temp);
#endif
- result = (__v4si) vec_vpkudum ((__vector long long) temp,
- (__vector long long) vzero);
+ result = (__v4si) vec_pack ((__vector long long) temp,
+ (__vector long long) vzero);
#else
{
const __v16qu pkperm = {0x00, 0x01, 0x02, 0x03, 0x08, 0x09, 0x0a, 0x0b,
@@ -1254,8 +1254,8 @@ _mm_movemask_pd (__m128d __A)
};
result = ((__vector unsigned long long)
- vec_vbpermq ((__vector unsigned char) __A,
- (__vector unsigned char) perm_mask));
+ vec_bperm ((__vector unsigned char) __A,
+ (__vector unsigned char) perm_mask));
#ifdef __LITTLE_ENDIAN__
return result[1];
@@ -1434,7 +1434,7 @@ _mm_madd_epi16 (__m128i __A, __m128i __B)
{
__vector signed int zero = {0, 0, 0, 0};
- return (__m128i) vec_vmsumshm ((__v8hi)__A, (__v8hi)__B, zero);
+ return (__m128i) vec_msum ((__v8hi)__A, (__v8hi)__B, zero);
}
extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
@@ -1452,8 +1452,8 @@ _mm_mulhi_epi16 (__m128i __A, __m128i __B)
#endif
};
- w0 = vec_vmulesh ((__v8hi)__A, (__v8hi)__B);
- w1 = vec_vmulosh ((__v8hi)__A, (__v8hi)__B);
+ w0 = vec_mule ((__v8hi)__A, (__v8hi)__B);
+ w1 = vec_mulo ((__v8hi)__A, (__v8hi)__B);
return (__m128i) vec_perm (w0, w1, xform1);
}
@@ -2046,8 +2046,8 @@ _mm_movemask_epi8 (__m128i __A)
};
result = ((__vector unsigned long long)
- vec_vbpermq ((__vector unsigned char) __A,
- (__vector unsigned char) perm_mask));
+ vec_bperm ((__vector unsigned char) __A,
+ (__vector unsigned char) perm_mask));
#ifdef __LITTLE_ENDIAN__
return result[1];
@@ -2071,8 +2071,8 @@ _mm_mulhi_epu16 (__m128i __A, __m128i __B)
#endif
};
- w0 = vec_vmuleuh ((__v8hu)__A, (__v8hu)__B);
- w1 = vec_vmulouh ((__v8hu)__A, (__v8hu)__B);
+ w0 = vec_mule ((__v8hu)__A, (__v8hu)__B);
+ w1 = vec_mulo ((__v8hu)__A, (__v8hu)__B);
return (__m128i) vec_perm (w0, w1, xform1);
}
diff --git a/gcc/config/rs6000/rs6000-builtin-new.def b/gcc/config/rs6000/rs6000-builtin-new.def
index 2c1eabd4fde..645d4b0425f 100644
--- a/gcc/config/rs6000/rs6000-builtin-new.def
+++ b/gcc/config/rs6000/rs6000-builtin-new.def
@@ -2214,7 +2214,7 @@
const vsll __builtin_altivec_vcmpgtud (vull, vull);
VCMPGTUD vector_gtuv2di {}
- const int __builtin_altivec_vcmpgtud_p (vull, vull);
+ const int __builtin_altivec_vcmpgtud_p (int, vull, vull);
VCMPGTUD_P vector_gtu_v2di_p {pred}
const vsll __builtin_altivec_vmaxsd (vsll, vsll);
@@ -2582,49 +2582,49 @@
VCTZLSBB_V8HI vctzlsbb_v8hi {}
const signed int __builtin_altivec_vcmpaeb_p (vsc, vsc);
- VCMPAEB_P vector_ae_v16qi_p {pred}
+ VCMPAEB_P vector_ae_v16qi_p {}
const signed int __builtin_altivec_vcmpaed_p (vsll, vsll);
- VCMPAED_P vector_ae_v2di_p {pred}
+ VCMPAED_P vector_ae_v2di_p {}
const signed int __builtin_altivec_vcmpaedp_p (vd, vd);
- VCMPAEDP_P vector_ae_v2df_p {pred}
+ VCMPAEDP_P vector_ae_v2df_p {}
const signed int __builtin_altivec_vcmpaefp_p (vf, vf);
- VCMPAEFP_P vector_ae_v4sf_p {pred}
+ VCMPAEFP_P vector_ae_v4sf_p {}
const signed int __builtin_altivec_vcmpaeh_p (vss, vss);
- VCMPAEH_P vector_ae_v8hi_p {pred}
+ VCMPAEH_P vector_ae_v8hi_p {}
const signed int __builtin_altivec_vcmpaew_p (vsi, vsi);
- VCMPAEW_P vector_ae_v4si_p {pred}
+ VCMPAEW_P vector_ae_v4si_p {}
const vsc __builtin_altivec_vcmpneb (vsc, vsc);
VCMPNEB vcmpneb {}
const signed int __builtin_altivec_vcmpneb_p (vsc, vsc);
- VCMPNEB_P vector_ne_v16qi_p {pred}
+ VCMPNEB_P vector_ne_v16qi_p {}
const signed int __builtin_altivec_vcmpned_p (vsll, vsll);
- VCMPNED_P vector_ne_v2di_p {pred}
+ VCMPNED_P vector_ne_v2di_p {}
const signed int __builtin_altivec_vcmpnedp_p (vd, vd);
- VCMPNEDP_P vector_ne_v2df_p {pred}
+ VCMPNEDP_P vector_ne_v2df_p {}
const signed int __builtin_altivec_vcmpnefp_p (vf, vf);
- VCMPNEFP_P vector_ne_v4sf_p {pred}
+ VCMPNEFP_P vector_ne_v4sf_p {}
const vss __builtin_altivec_vcmpneh (vss, vss);
VCMPNEH vcmpneh {}
const signed int __builtin_altivec_vcmpneh_p (vss, vss);
- VCMPNEH_P vector_ne_v8hi_p {pred}
+ VCMPNEH_P vector_ne_v8hi_p {}
const vsi __builtin_altivec_vcmpnew (vsi, vsi);
VCMPNEW vcmpnew {}
const signed int __builtin_altivec_vcmpnew_p (vsi, vsi);
- VCMPNEW_P vector_ne_v4si_p {pred}
+ VCMPNEW_P vector_ne_v4si_p {}
const vsc __builtin_altivec_vcmpnezb (vsc, vsc);
CMPNEZB vcmpnezb {}
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-11.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-11.c
index c56a24e0db4..b5bea3cf1a0 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-11.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-11.c
@@ -8,6 +8,6 @@ int doTestBCDSignificance (_Decimal64 *p)
{
_Decimal64 source = *p;
- return __builtin_dfp_dtstsfi_lt (5, source); /* { dg-error "'__builtin_dtstsfi_lt' requires" } */
+ return __builtin_dfp_dtstsfi_lt (5, source); /* { dg-error "'__builtin_dtstsfi_lt' requires" } */ /* { dg-error "'__builtin_dtstsfi_lt_dd' requires" } */
}
^ permalink raw reply [flat|nested] 29+ messages in thread
* [gcc(refs/users/wschmidt/heads/builtins4)] rs6000: More bug fixes
@ 2021-02-07 18:17 William Schmidt
0 siblings, 0 replies; 29+ messages in thread
From: William Schmidt @ 2021-02-07 18:17 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:7ff8854fbeca0344663b584452d7505ecf7a9a30
commit 7ff8854fbeca0344663b584452d7505ecf7a9a30
Author: Bill Schmidt <wschmidt@linux.ibm.com>
Date: Thu Jan 7 12:17:54 2021 -0600
rs6000: More bug fixes
2021-01-07 Bill Schmidt <wschmidt@linux.ibm.com>
gcc/
* config/rs6000/rs6000-builtin-new.def
* config/rs6000-overload.def
gcc/testsuite/
* gcc.target/powerpc/altivec-10.c: Adjust.
* gcc.target/powerpc/bfp/scalar-test-neg-2.c: Adjust.
* gcc.target/powerpc/bfp/scalar-test-neg-3.c: Adjust.
* gcc.target/powerpc/bfp/scalar-test-neg-5.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-10.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-11.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-12.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-13.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-14.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-15.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-16.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-17.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-18.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-19.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-30.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-31.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-32.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-33.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-34.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-35.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-36.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-37.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-38.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-39.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-50.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-51.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-52.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-53.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-54.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-55.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-56.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-57.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-58.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-59.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-70.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-71.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-72.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-73.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-74.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-75.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-76.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-77.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-78.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-79.c: Adjust.
Diff:
---
gcc/config/rs6000/rs6000-builtin-new.def | 26 ++++++++---------
gcc/config/rs6000/rs6000-overload.def | 34 +++++++++++-----------
gcc/testsuite/gcc.target/powerpc/altivec-10.c | 2 +-
.../gcc.target/powerpc/bfp/scalar-test-neg-2.c | 2 +-
.../gcc.target/powerpc/bfp/scalar-test-neg-3.c | 2 +-
.../gcc.target/powerpc/bfp/scalar-test-neg-5.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-10.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-11.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-12.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-13.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-14.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-15.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-16.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-17.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-18.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-19.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-30.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-31.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-32.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-33.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-34.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-35.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-36.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-37.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-38.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-39.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-50.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-51.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-52.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-53.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-54.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-55.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-56.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-57.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-58.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-59.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-70.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-71.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-72.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-73.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-74.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-75.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-76.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-77.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-78.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-79.c | 2 +-
46 files changed, 74 insertions(+), 74 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-builtin-new.def b/gcc/config/rs6000/rs6000-builtin-new.def
index 8b54b17e1ce..2c1eabd4fde 100644
--- a/gcc/config/rs6000/rs6000-builtin-new.def
+++ b/gcc/config/rs6000/rs6000-builtin-new.def
@@ -2734,10 +2734,10 @@
const signed int __builtin_vsx_scalar_cmp_exp_dp_unordered (double, double);
VSCEDPUO xscmpexpdp_unordered {}
- const unsigned int __builtin_vsx_scalar_test_data_class_dp (double, signed int);
+ const unsigned int __builtin_vsx_scalar_test_data_class_dp (double, const int<7>);
VSTDCDP xststdcdp {}
- const unsigned int __builtin_vsx_scalar_test_data_class_sp (float, signed int);
+ const unsigned int __builtin_vsx_scalar_test_data_class_sp (float, const int<7>);
VSTDCSP xststdcsp {}
const unsigned int __builtin_vsx_scalar_test_neg_dp (double);
@@ -2746,10 +2746,10 @@
const unsigned int __builtin_vsx_scalar_test_neg_sp (float);
VSTDCNSP xststdcnegsp {}
- const vbll __builtin_vsx_test_data_class_dp (vd, signed int);
+ const vbll __builtin_vsx_test_data_class_dp (vd, const int<7>);
VTDCDP xvtstdcdp {}
- const vbi __builtin_vsx_test_data_class_sp (vf, signed int);
+ const vbi __builtin_vsx_test_data_class_sp (vf, const int<7>);
VTDCSP xvtstdcsp {}
const vf __builtin_vsx_vextract_fp_from_shorth (vus);
@@ -2794,28 +2794,28 @@
double __builtin_mffsl ();
MFFSL rs6000_mffsl {}
- const signed int __builtin_dtstsfi_eq_dd (unsigned int, _Decimal64);
+ const signed int __builtin_dtstsfi_eq_dd (const int<6>, _Decimal64);
TSTSFI_EQ_DD dfptstsfi_eq_dd {}
- const signed int __builtin_dtstsfi_eq_td (unsigned int, _Decimal128);
+ const signed int __builtin_dtstsfi_eq_td (const int<6>, _Decimal128);
TSTSFI_EQ_TD dfptstsfi_eq_td {}
- const signed int __builtin_dtstsfi_gt_dd (unsigned int, _Decimal64);
+ const signed int __builtin_dtstsfi_gt_dd (const int<6>, _Decimal64);
TSTSFI_GT_DD dfptstsfi_gt_dd {}
- const signed int __builtin_dtstsfi_gt_td (unsigned int, _Decimal128);
+ const signed int __builtin_dtstsfi_gt_td (const int<6>, _Decimal128);
TSTSFI_GT_TD dfptstsfi_gt_td {}
- const signed int __builtin_dtstsfi_lt_dd (unsigned int, _Decimal64);
+ const signed int __builtin_dtstsfi_lt_dd (const int<6>, _Decimal64);
TSTSFI_LT_DD dfptstsfi_lt_dd {}
- const signed int __builtin_dtstsfi_lt_td (unsigned int, _Decimal128);
+ const signed int __builtin_dtstsfi_lt_td (const int<6>, _Decimal128);
TSTSFI_LT_TD dfptstsfi_lt_td {}
- const signed int __builtin_dtstsfi_ov_dd (unsigned int, _Decimal64);
+ const signed int __builtin_dtstsfi_ov_dd (const int<6>, _Decimal64);
TSTSFI_OV_DD dfptstsfi_unordered_dd {}
- const signed int __builtin_dtstsfi_ov_td (unsigned int, _Decimal128);
+ const signed int __builtin_dtstsfi_ov_td (const int<6>, _Decimal128);
TSTSFI_OV_TD dfptstsfi_unordered_td {}
@@ -2905,7 +2905,7 @@
const _Float128 __builtin_vsx_scalar_insert_exp_qp (_Float128, unsigned long long);
VSIEQPF xsiexpqpf_kf {}
- const unsigned int __builtin_vsx_scalar_test_data_class_qp (_Float128, signed int);
+ const unsigned int __builtin_vsx_scalar_test_data_class_qp (_Float128, const int<7>);
VSTDCQP xststdcqp_kf {}
const unsigned int __builtin_vsx_scalar_test_neg_qp (_Float128);
diff --git a/gcc/config/rs6000/rs6000-overload.def b/gcc/config/rs6000/rs6000-overload.def
index 60a18a79416..45e95ea3063 100644
--- a/gcc/config/rs6000/rs6000-overload.def
+++ b/gcc/config/rs6000/rs6000-overload.def
@@ -3548,27 +3548,27 @@
XVRDPIZ
[VEC_TSTSFI_GT, SKIP, __builtin_dfp_dtstsfi_gt]
- signed int __builtin_dfp_dtstsfi_gt (unsigned int, _Decimal64);
+ signed int __builtin_dfp_dtstsfi_gt (const int, _Decimal64);
TSTSFI_GT_DD
- signed int __builtin_dfp_dtstsfi_gt (unsigned int, _Decimal128);
+ signed int __builtin_dfp_dtstsfi_gt (const int, _Decimal128);
TSTSFI_GT_TD
[VEC_TSTSFI_EQ, SKIP, __builtin_dfp_dtstsfi_eq]
- signed int __builtin_dfp_dtstsfi_eq (unsigned int, _Decimal64);
+ signed int __builtin_dfp_dtstsfi_eq (const int, _Decimal64);
TSTSFI_EQ_DD
- signed int __builtin_dfp_dtstsfi_eq (unsigned int, _Decimal128);
+ signed int __builtin_dfp_dtstsfi_eq (const int, _Decimal128);
TSTSFI_EQ_TD
[VEC_TSTSFI_LT, SKIP, __builtin_dfp_dtstsfi_lt]
- signed int __builtin_dfp_dtstsfi_lt (unsigned int, _Decimal64);
+ signed int __builtin_dfp_dtstsfi_lt (const int, _Decimal64);
TSTSFI_LT_DD
- signed int __builtin_dfp_dtstsfi_lt (unsigned int, _Decimal128);
+ signed int __builtin_dfp_dtstsfi_lt (const int, _Decimal128);
TSTSFI_LT_TD
[VEC_TSTSFI_OV, SKIP, __builtin_dfp_dtstsfi_ov]
- signed int __builtin_dfp_dtstsfi_ov (unsigned int, _Decimal64);
+ signed int __builtin_dfp_dtstsfi_ov (const int, _Decimal64);
TSTSFI_OV_DD
- signed int __builtin_dfp_dtstsfi_ov (unsigned int, _Decimal128);
+ signed int __builtin_dfp_dtstsfi_ov (const int, _Decimal128);
TSTSFI_OV_TD
[VEC_UNPACKH, vec_unpackh, __builtin_vec_unpackh]
@@ -3637,7 +3637,7 @@
vull __builtin_vec_extract_sig (vd);
VESDP
-[VEC_VIE, vec_insert_exp, __builtin_vec_insert_exp, ARCH_PWR9]
+[VEC_VIE, vec_insert_exp, __builtin_vec_insert_exp, _ARCH_PWR9]
vf __builtin_vec_insert_exp (vf, vui);
VIESP VIESP_VF
vf __builtin_vec_insert_exp (vui, vui);
@@ -3694,25 +3694,25 @@
VSIEQPF
[VEC_VSTDC, scalar_test_data_class, __builtin_vec_scalar_test_data_class, _ARCH_PWR9]
- bool __builtin_vec_scalar_test_data_class (float, signed int);
+ unsigned int __builtin_vec_scalar_test_data_class (float, const int);
VSTDCSP
- bool __builtin_vec_scalar_test_data_class (double, signed int);
+ unsigned int __builtin_vec_scalar_test_data_class (double, const int);
VSTDCDP
- bool __builtin_vec_scalar_test_data_class (_Float128, signed int);
+ unsigned int __builtin_vec_scalar_test_data_class (_Float128, const int);
VSTDCQP
[VEC_VSTDCN, scalar_test_neg, __builtin_vec_scalar_test_neg, _ARCH_PWR9]
- bool __builtin_vec_scalar_test_neg (float);
+ unsigned int __builtin_vec_scalar_test_neg (float);
VSTDCNSP
- bool __builtin_vec_scalar_test_neg (double);
+ unsigned int __builtin_vec_scalar_test_neg (double);
VSTDCNDP
- bool __builtin_vec_scalar_test_neg (_Float128);
+ unsigned int __builtin_vec_scalar_test_neg (_Float128);
VSTDCNQP
[VEC_VTDC, vec_test_data_class, __builtin_vec_test_data_class, _ARCH_PWR9]
- vbi __builtin_vec_test_data_class (vf, signed int);
+ vbi __builtin_vec_test_data_class (vf, const int);
VTDCSP
- vbll __builtin_vec_test_data_class (vd, signed int);
+ vbll __builtin_vec_test_data_class (vd, const int);
VTDCDP
[VEC_XL, vec_xl, __builtin_vec_vsx_ld, __VSX__]
diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-10.c b/gcc/testsuite/gcc.target/powerpc/altivec-10.c
index f532eebbfab..e12b88a165b 100644
--- a/gcc/testsuite/gcc.target/powerpc/altivec-10.c
+++ b/gcc/testsuite/gcc.target/powerpc/altivec-10.c
@@ -61,7 +61,7 @@ check_cmple()
vector float a = {1.0, 2.0, 3.0, 4.0};
vector float b = {1.0, 3.0, 2.0, 5.0};
vector bool int aux;
- vector signed int le = {-1, -1, 0, -1};
+ vector bool int le = (vector bool int){-1, -1, 0, -1};
aux = vec_cmple (a, b);
diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-2.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-2.c
index 7d2b4deefc3..7a1e8e8bd30 100644
--- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-2.c
+++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-2.c
@@ -10,5 +10,5 @@ test_neg (float *p)
{
float source = *p;
- return __builtin_vec_scalar_test_neg_sp (source); /* { dg-error "'__builtin_vsx_scalar_test_neg_sp' requires" } */
+ return __builtin_vec_scalar_test_neg (source); /* { dg-error "'__builtin_vsx_scalar_test_neg' requires" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-3.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-3.c
index b503dfa8b56..c9b90927693 100644
--- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-3.c
@@ -10,5 +10,5 @@ test_neg (double *p)
{
double source = *p;
- return __builtin_vec_scalar_test_neg_dp (source); /* { dg-error "'__builtin_vsx_scalar_test_neg_dp' requires" } */
+ return __builtin_vec_scalar_test_neg (source); /* { dg-error "'__builtin_vsx_scalar_test_neg' requires" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-5.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-5.c
index bab86040a7b..e70eb2d46f8 100644
--- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-5.c
+++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-5.c
@@ -10,5 +10,5 @@ test_neg (__ieee128 *p)
{
__ieee128 source = *p;
- return __builtin_vec_scalar_test_neg_qp (source); /* { dg-error "'__builtin_vsx_scalar_test_neg_qp' requires" } */
+ return __builtin_vec_scalar_test_neg (source); /* { dg-error "'__builtin_vsx_scalar_test_neg' requires" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-10.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-10.c
index 822030bf737..4f7562b9c38 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-10.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-10.c
@@ -9,7 +9,7 @@ int doTestBCDSignificance (_Decimal64 *p)
{
_Decimal64 source = *p;
- return __builtin_dfp_dtstsfi_lt_dd (5, source);
+ return __builtin_dfp_dtstsfi_lt (5, source);
}
/* { dg-final { scan-assembler "dtstsfi" } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-11.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-11.c
index 044e7683cf1..c56a24e0db4 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-11.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-11.c
@@ -8,6 +8,6 @@ int doTestBCDSignificance (_Decimal64 *p)
{
_Decimal64 source = *p;
- return __builtin_dfp_dtstsfi_lt_dd (5, source); /* { dg-error "'__builtin_dtstsfi_lt_dd' requires" } */
+ return __builtin_dfp_dtstsfi_lt (5, source); /* { dg-error "'__builtin_dtstsfi_lt' requires" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-12.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-12.c
index 350b4c10205..4b72fa8edc3 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-12.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-12.c
@@ -8,6 +8,6 @@ int doTestBCDSignificance (_Decimal64 *p)
{
_Decimal64 source = *p;
- return __builtin_dfp_dtstsfi_lt_dd (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
+ return __builtin_dfp_dtstsfi_lt (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-13.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-13.c
index cc54c6b265e..af07fbb4a01 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-13.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-13.c
@@ -8,7 +8,7 @@ int doTestBCDSignificance (_Decimal64 *p)
{
_Decimal64 source = *p;
- if (__builtin_dfp_dtstsfi_lt_dd (63, source))
+ if (__builtin_dfp_dtstsfi_lt (63, source))
return 3;
else
return 5;
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-14.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-14.c
index 011d20039d0..6397aae3e56 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-14.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-14.c
@@ -8,6 +8,6 @@ int doTestBCDSignificance (_Decimal64 *p, unsigned int significance)
{
_Decimal64 source = *p;
- return __builtin_dfp_dtstsfi_lt_dd (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
+ return __builtin_dfp_dtstsfi_lt (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-15.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-15.c
index 54d2557fa2f..6f57baf0150 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-15.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-15.c
@@ -9,7 +9,7 @@ int doTestBCDSignificance (_Decimal128 *p)
{
_Decimal128 source = *p;
- return __builtin_dfp_dtstsfi_lt_td (5, source);
+ return __builtin_dfp_dtstsfi_lt (5, source);
}
/* { dg-final { scan-assembler "dtstsfiq" } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-16.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-16.c
index 8626c579a25..c6a42f089e0 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-16.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-16.c
@@ -8,7 +8,7 @@ int doTestBCDSignificance (_Decimal128 *p)
{
_Decimal128 source = *p;
- return __builtin_dfp_dtstsfi_lt_td (5, source); /* { dg-error "'__builtin_dtstsfi_lt_td' requires" } */
+ return __builtin_dfp_dtstsfi_lt (5, source); /* { dg-error "'__builtin_dtstsfi_lt' requires" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-17.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-17.c
index 28033dbac18..ea934ea4652 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-17.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-17.c
@@ -8,7 +8,7 @@ int doTestBCDSignificance (_Decimal128 *p)
{
_Decimal128 source = *p;
- return __builtin_dfp_dtstsfi_lt_td (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
+ return __builtin_dfp_dtstsfi_lt (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-18.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-18.c
index 8ce9390feaf..28bc10c3145 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-18.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-18.c
@@ -8,7 +8,7 @@ int doTestBCDSignificance (_Decimal128 *p)
{
_Decimal128 source = *p;
- if (__builtin_dfp_dtstsfi_lt_td (63, source))
+ if (__builtin_dfp_dtstsfi_lt (63, source))
return 3;
else
return 5;
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-19.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-19.c
index 092b9c0f7c5..b2073f56b05 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-19.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-19.c
@@ -8,5 +8,5 @@ int doTestBCDSignificance (_Decimal128 *p, unsigned int significance)
{
_Decimal128 source = *p;
- return __builtin_dfp_dtstsfi_lt_td (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
+ return __builtin_dfp_dtstsfi_lt (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-30.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-30.c
index 6d8869e5435..ee098bcb999 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-30.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-30.c
@@ -9,7 +9,7 @@ int doTestBCDSignificance (_Decimal64 *p)
{
_Decimal64 source = *p;
- return __builtin_dfp_dtstsfi_gt_dd (5, source);
+ return __builtin_dfp_dtstsfi_gt (5, source);
}
/* { dg-final { scan-assembler "dtstsfi" } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-31.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-31.c
index 439fcb2a548..5d9d5d61b42 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-31.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-31.c
@@ -8,6 +8,6 @@ int doTestBCDSignificance (_Decimal64 *p)
{
_Decimal64 source = *p;
- return __builtin_dfp_dtstsfi_gt_dd (5, source); /* { dg-error "'__builtin_dtstsfi_gt_dd' requires" } */
+ return __builtin_dfp_dtstsfi_gt (5, source); /* { dg-error "'__builtin_dtstsfi_gt' requires" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-32.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-32.c
index d24f3982ee9..15d7a352fdf 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-32.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-32.c
@@ -8,6 +8,6 @@ int doTestBCDSignificance (_Decimal64 *p)
{
_Decimal64 source = *p;
- return __builtin_dfp_dtstsfi_gt_dd (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
+ return __builtin_dfp_dtstsfi_gt (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-33.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-33.c
index 6d978a09750..236f39393e0 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-33.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-33.c
@@ -8,7 +8,7 @@ int doTestBCDSignificance (_Decimal64 *p)
{
_Decimal64 source = *p;
- if (__builtin_dfp_dtstsfi_gt_dd (63, source))
+ if (__builtin_dfp_dtstsfi_gt (63, source))
return 3;
else
return 5;
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-34.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-34.c
index b6620c51f2a..f6ed00a73dd 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-34.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-34.c
@@ -8,6 +8,6 @@ int doTestBCDSignificance (_Decimal64 *p, unsigned int significance)
{
_Decimal64 source = *p;
- return __builtin_dfp_dtstsfi_gt_dd (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
+ return __builtin_dfp_dtstsfi_gt (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-35.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-35.c
index fdafaf9ceb8..1390c8381f8 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-35.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-35.c
@@ -9,7 +9,7 @@ int doTestBCDSignificance (_Decimal128 *p)
{
_Decimal128 source = *p;
- return __builtin_dfp_dtstsfi_gt_td (5, source);
+ return __builtin_dfp_dtstsfi_gt (5, source);
}
/* { dg-final { scan-assembler "dtstsfiq" } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-36.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-36.c
index 822f6d57003..ca5e0098411 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-36.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-36.c
@@ -8,7 +8,7 @@ int doTestBCDSignificance (_Decimal128 *p)
{
_Decimal128 source = *p;
- return __builtin_dfp_dtstsfi_gt_td (5, source); /* { dg-error "'__builtin_dtstsfi_gt_td' requires" } */
+ return __builtin_dfp_dtstsfi_gt (5, source); /* { dg-error "'__builtin_dtstsfi_gt' requires" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-37.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-37.c
index dc4c8ecdd00..8e3954d6b93 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-37.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-37.c
@@ -8,7 +8,7 @@ int doTestBCDSignificance (_Decimal128 *p)
{
_Decimal128 source = *p;
- return __builtin_dfp_dtstsfi_gt_td (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
+ return __builtin_dfp_dtstsfi_gt (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-38.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-38.c
index fce744cd916..a2b922955f6 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-38.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-38.c
@@ -8,7 +8,7 @@ int doTestBCDSignificance (_Decimal128 *p)
{
_Decimal128 source = *p;
- if (__builtin_dfp_dtstsfi_gt_td (63, source))
+ if (__builtin_dfp_dtstsfi_gt (63, source))
return 3;
else
return 5;
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-39.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-39.c
index 1aee9efe919..f6c0ede46cc 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-39.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-39.c
@@ -8,5 +8,5 @@ int doTestBCDSignificance (_Decimal128 *p, unsigned int significance)
{
_Decimal128 source = *p;
- return __builtin_dfp_dtstsfi_gt_td (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
+ return __builtin_dfp_dtstsfi_gt (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-50.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-50.c
index 25b35ed4bc9..4663fc653bb 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-50.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-50.c
@@ -9,7 +9,7 @@ int doTestBCDSignificance (_Decimal64 *p)
{
_Decimal64 source = *p;
- return __builtin_dfp_dtstsfi_eq_dd (5, source);
+ return __builtin_dfp_dtstsfi_eq (5, source);
}
/* { dg-final { scan-assembler "dtstsfi" } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-51.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-51.c
index e6b5fe5469e..5e4f4964aaa 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-51.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-51.c
@@ -8,6 +8,6 @@ int doTestBCDSignificance (_Decimal64 *p)
{
_Decimal64 source = *p;
- return __builtin_dfp_dtstsfi_eq_dd (5, source); /* { dg-error "'__builtin_dtstsfi_eq_dd' requires" } */
+ return __builtin_dfp_dtstsfi_eq (5, source); /* { dg-error "'__builtin_dtstsfi_eq' requires" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-52.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-52.c
index c9431b5ea1a..fc6b3568d09 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-52.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-52.c
@@ -8,6 +8,6 @@ int doTestBCDSignificance (_Decimal64 *p)
{
_Decimal64 source = *p;
- return __builtin_dfp_dtstsfi_eq_dd (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
+ return __builtin_dfp_dtstsfi_eq (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-53.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-53.c
index d11f497b137..9c194374187 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-53.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-53.c
@@ -8,7 +8,7 @@ int doTestBCDSignificance (_Decimal64 *p)
{
_Decimal64 source = *p;
- if (__builtin_dfp_dtstsfi_eq_dd (63, source))
+ if (__builtin_dfp_dtstsfi_eq (63, source))
return 3;
else
return 5;
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-54.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-54.c
index 2fdb58f6748..b896865e6bb 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-54.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-54.c
@@ -8,6 +8,6 @@ int doTestBCDSignificance (_Decimal64 *p, unsigned int significance)
{
_Decimal64 source = *p;
- return __builtin_dfp_dtstsfi_eq_dd (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
+ return __builtin_dfp_dtstsfi_eq (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-55.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-55.c
index 912ae7f3492..5c6fcc4ec83 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-55.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-55.c
@@ -9,7 +9,7 @@ int doTestBCDSignificance (_Decimal128 *p)
{
_Decimal128 source = *p;
- return __builtin_dfp_dtstsfi_eq_td (5, source);
+ return __builtin_dfp_dtstsfi_eq (5, source);
}
/* { dg-final { scan-assembler "dtstsfiq" } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-56.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-56.c
index 218d2f64d3e..02ff47441e5 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-56.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-56.c
@@ -8,7 +8,7 @@ int doTestBCDSignificance (_Decimal128 *p)
{
_Decimal128 source = *p;
- return __builtin_dfp_dtstsfi_eq_td (5, source); /* { dg-error "'__builtin_dtstsfi_eq_td' requires" } */
+ return __builtin_dfp_dtstsfi_eq (5, source); /* { dg-error "'__builtin_dtstsfi_eq' requires" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-57.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-57.c
index 275bf8d0ac2..edfac68b0e8 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-57.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-57.c
@@ -8,7 +8,7 @@ int doTestBCDSignificance (_Decimal128 *p)
{
_Decimal128 source = *p;
- return __builtin_dfp_dtstsfi_eq_td (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
+ return __builtin_dfp_dtstsfi_eq (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-58.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-58.c
index 0626d87d9be..9a94371da35 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-58.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-58.c
@@ -8,7 +8,7 @@ int doTestBCDSignificance (_Decimal128 *p)
{
_Decimal128 source = *p;
- if (__builtin_dfp_dtstsfi_eq_td (63, source))
+ if (__builtin_dfp_dtstsfi_eq (63, source))
return 3;
else
return 5;
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-59.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-59.c
index e1da3d810ef..e7b50dc108e 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-59.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-59.c
@@ -8,5 +8,5 @@ int doTestBCDSignificance (_Decimal128 *p, unsigned int significance)
{
_Decimal128 source = *p;
- return __builtin_dfp_dtstsfi_eq_td (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
+ return __builtin_dfp_dtstsfi_eq (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-70.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-70.c
index 875354c9ab8..c584d988b4b 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-70.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-70.c
@@ -9,7 +9,7 @@ int doTestBCDSignificance (_Decimal64 *p)
{
_Decimal64 source = *p;
- return __builtin_dfp_dtstsfi_ov_dd (5, source);
+ return __builtin_dfp_dtstsfi_ov (5, source);
}
/* { dg-final { scan-assembler "dtstsfi" } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-71.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-71.c
index 68758cf535a..6c64021a479 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-71.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-71.c
@@ -8,6 +8,6 @@ int doTestBCDSignificance (_Decimal64 *p)
{
_Decimal64 source = *p;
- return __builtin_dfp_dtstsfi_ov_dd (5, source); /* { dg-error "'__builtin_dtstsfi_ov_dd' requires" } */
+ return __builtin_dfp_dtstsfi_ov (5, source); /* { dg-error "'__builtin_dtstsfi_ov' requires" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-72.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-72.c
index 725cc5432b9..44aaab201f9 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-72.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-72.c
@@ -8,6 +8,6 @@ int doTestBCDSignificance (_Decimal64 *p)
{
_Decimal64 source = *p;
- return __builtin_dfp_dtstsfi_ov_dd (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
+ return __builtin_dfp_dtstsfi_ov (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-73.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-73.c
index f368c38204b..e7d2a27ecfd 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-73.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-73.c
@@ -8,7 +8,7 @@ int doTestBCDSignificance (_Decimal64 *p)
{
_Decimal64 source = *p;
- if (__builtin_dfp_dtstsfi_ov_dd (63, source))
+ if (__builtin_dfp_dtstsfi_ov (63, source))
return 3;
else
return 5;
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-74.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-74.c
index c6ffd51d9f4..fb3331162c7 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-74.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-74.c
@@ -8,6 +8,6 @@ int doTestBCDSignificance (_Decimal64 *p, unsigned int significance)
{
_Decimal64 source = *p;
- return __builtin_dfp_dtstsfi_ov_dd (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
+ return __builtin_dfp_dtstsfi_ov (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-75.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-75.c
index 910fb7d98c8..7c75265de08 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-75.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-75.c
@@ -9,7 +9,7 @@ int doTestBCDSignificance (_Decimal128 *p)
{
_Decimal128 source = *p;
- return __builtin_dfp_dtstsfi_ov_td (5, source);
+ return __builtin_dfp_dtstsfi_ov (5, source);
}
/* { dg-final { scan-assembler "dtstsfiq" } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-76.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-76.c
index d867a987df8..982ed5d79df 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-76.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-76.c
@@ -8,7 +8,7 @@ int doTestBCDSignificance (_Decimal128 *p)
{
_Decimal128 source = *p;
- return __builtin_dfp_dtstsfi_ov_td (5, source); /* { dg-error "'__builtin_dtstsfi_ov_td' requires" } */
+ return __builtin_dfp_dtstsfi_ov (5, source); /* { dg-error "'__builtin_dtstsfi_ov' requires" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-77.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-77.c
index d279bfb5751..59471cfb645 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-77.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-77.c
@@ -8,7 +8,7 @@ int doTestBCDSignificance (_Decimal128 *p)
{
_Decimal128 source = *p;
- return __builtin_dfp_dtstsfi_ov_td (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
+ return __builtin_dfp_dtstsfi_ov (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-78.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-78.c
index 3034300f72b..1bda795b55a 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-78.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-78.c
@@ -8,7 +8,7 @@ int doTestBCDSignificance (_Decimal128 *p)
{
_Decimal128 source = *p;
- if (__builtin_dfp_dtstsfi_ov_td (63, source))
+ if (__builtin_dfp_dtstsfi_ov (63, source))
return 3;
else
return 5;
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-79.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-79.c
index b88b5a86bcb..c9e1721b3d6 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-79.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-79.c
@@ -8,5 +8,5 @@ int doTestBCDSignificance (_Decimal128 *p, unsigned int significance)
{
_Decimal128 source = *p;
- return __builtin_dfp_dtstsfi_ov_td (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
+ return __builtin_dfp_dtstsfi_ov (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
}
^ permalink raw reply [flat|nested] 29+ messages in thread
* [gcc(refs/users/wschmidt/heads/builtins4)] rs6000: More bug fixes
@ 2021-02-07 18:17 William Schmidt
0 siblings, 0 replies; 29+ messages in thread
From: William Schmidt @ 2021-02-07 18:17 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:f3e9d51bef93c1bcfd139823ea92adc589dcfab1
commit f3e9d51bef93c1bcfd139823ea92adc589dcfab1
Author: Bill Schmidt <wschmidt@linux.ibm.com>
Date: Wed Jan 6 15:06:45 2021 -0600
rs6000: More bug fixes
2021-01-06 Bill Schmidt <wschmidt@linux.ibm.com>
gcc/
* config/rs6000/rs6000-c.c
(altivec_resolve_new_overloaded_builtin): Fix arg access thinko.
* config/rs6000/rs6000-overload-def (VEC_OR): Add missing forms.
(VEC_VSCEUO): Fix typo.
gcc/testsuite/
* gcc.dg/vmx/ops.c: Remove bad srl and vec_v* forms.
Diff:
---
gcc/config/rs6000/rs6000-c.c | 2 +-
gcc/config/rs6000/rs6000-overload.def | 52 +++++++++++++--
gcc/testsuite/gcc.dg/vmx/ops.c | 120 ----------------------------------
3 files changed, 47 insertions(+), 127 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c
index c01470c51c0..96d20f8d601 100644
--- a/gcc/config/rs6000/rs6000-c.c
+++ b/gcc/config/rs6000/rs6000-c.c
@@ -2902,7 +2902,7 @@ altivec_resolve_new_overloaded_builtin (location_t loc, tree fndecl,
gcc_assert (instance != NULL);
tree fntype = rs6000_builtin_info_x[instance->bifid].fntype;
tree parmtype0 = TREE_VALUE (TYPE_ARG_TYPES (fntype));
- tree parmtype1 = TREE_VALUE (TREE_CHAIN (parmtype0));
+ tree parmtype1 = TREE_VALUE (TREE_CHAIN (TYPE_ARG_TYPES (fntype)));
if (rs6000_new_builtin_type_compatible (types[0], parmtype0)
&& rs6000_new_builtin_type_compatible (types[1], parmtype1))
diff --git a/gcc/config/rs6000/rs6000-overload.def b/gcc/config/rs6000/rs6000-overload.def
index 0876b8068bc..60a18a79416 100644
--- a/gcc/config/rs6000/rs6000-overload.def
+++ b/gcc/config/rs6000/rs6000-overload.def
@@ -2175,32 +2175,72 @@
[VEC_OR, vec_or, __builtin_vec_or]
vsc __builtin_vec_or (vsc, vsc);
VOR_V16QI
+ vsc __builtin_vec_or (vsc, vbc);
+ VOR_V16QI VOR_VSC_VBC
+ vsc __builtin_vec_or (vbc, vsc);
+ VOR_V16QI VOR_VBC_VSC
vuc __builtin_vec_or (vuc, vuc);
VOR_V16QI_UNS VOR_V16QI_U
vbc __builtin_vec_or (vbc, vbc);
VOR_V16QI_UNS VOR_V16QI_B
+ vuc __builtin_vec_or (vuc, vbc);
+ VOR_V16QI_UNS VOR_V16QI_UB
+ vuc __builtin_vec_or (vbc, vuc);
+ VOR_V16QI_UNS VOR_V16QI_BU
vss __builtin_vec_or (vss, vss);
VOR_V8HI
+ vss __builtin_vec_or (vss, vbs);
+ VOR_V8HI VOR_VSS_VBS
+ vss __builtin_vec_or (vbs, vss);
+ VOR_V8HI VOR_VBS_VSS
vus __builtin_vec_or (vus, vus);
VOR_V8HI_UNS VOR_V8HI_U
vbs __builtin_vec_or (vbs, vbs);
VOR_V8HI_UNS VOR_V8HI_B
+ vus __builtin_vec_or (vus, vbs);
+ VOR_V8HI_UNS VOR_V8HI_UB
+ vus __builtin_vec_or (vbs, vus);
+ VOR_V8HI_UNS VOR_V8HI_BU
vsi __builtin_vec_or (vsi, vsi);
VOR_V4SI
+ vsi __builtin_vec_or (vsi, vbi);
+ VOR_V4SI VOR_VSI_VBI
+ vsi __builtin_vec_or (vbi, vsi);
+ VOR_V4SI VOR_VBI_VSI
vui __builtin_vec_or (vui, vui);
VOR_V4SI_UNS VOR_V4SI_U
vbi __builtin_vec_or (vbi, vbi);
VOR_V4SI_UNS VOR_V4SI_B
+ vui __builtin_vec_or (vui, vbi);
+ VOR_V4SI_UNS VOR_V4SI_UB
+ vui __builtin_vec_or (vui, vbi);
+ VOR_V4SI_UNS VOR_V4SI_BU
vsll __builtin_vec_or (vsll, vsll);
VOR_V2DI
+ vsll __builtin_vec_or (vsll, vbll);
+ VOR_V2DI VOR_VSLL_VBLL
+ vsll __builtin_vec_or (vbll, vsll);
+ VOR_V2DI VOR_VBLL_VSLL
vull __builtin_vec_or (vull, vull);
VOR_V2DI_UNS VOR_V2DI_U
vbll __builtin_vec_or (vbll, vbll);
VOR_V2DI_UNS VOR_V2DI_B
+ vull __builtin_vec_or (vull, vbll);
+ VOR_V2DI_UNS VOR_V2DI_UB
+ vull __builtin_vec_or (vbll, vull);
+ VOR_V2DI_UNS VOR_V2DI_BU
vf __builtin_vec_or (vf, vf);
VOR_V4SF
+ vf __builtin_vec_or (vf, vbi);
+ VOR_V4SF VOR_VF_VBI
+ vf __builtin_vec_or (vbi, vf);
+ VOR_V4SF VOR_VBI_VF
vd __builtin_vec_or (vd, vd);
VOR_V2DF
+ vd __builtin_vec_or (vd, vbll);
+ VOR_V2DF VOR_VD_VBLL
+ vd __builtin_vec_or (vbll, vd);
+ VOR_V2DF VOR_VBLL_VD
[VEC_ORC, vec_orc, __builtin_vec_orc, _ARCH_PWR8]
vsc __builtin_vec_orc (vsc, vsc);
@@ -3625,7 +3665,7 @@
signed int __builtin_vec_scalar_cmp_exp_lt (_Float128, _Float128);
VSCEQPLT
-[VEC_VSCEUO, scalar_cmp_exp_unordered, __builtin_vec_scalar_cmp_exp_unordered, ARCH_PWR9]
+[VEC_VSCEUO, scalar_cmp_exp_unordered, __builtin_vec_scalar_cmp_exp_unordered, _ARCH_PWR9]
signed int __builtin_vec_scalar_cmp_exp_unordered (double, double);
VSCEDPUO
signed int __builtin_vec_scalar_cmp_exp_unordered (_Float128, _Float128);
@@ -3638,17 +3678,17 @@
VSEEQP
[VEC_VSES, scalar_extract_sig, __builtin_vec_scalar_extract_sig, _ARCH_PWR9]
- unsigned int __builtin_vec_scalar_extract_sig (double);
+ unsigned long long __builtin_vec_scalar_extract_sig (double);
VSESDP
- unsigned int __builtin_vec_scalar_extract_sig (_Float128);
+ unsigned __int128 __builtin_vec_scalar_extract_sig (_Float128);
VSESQP
[VEC_VSIE, scalar_insert_exp, __builtin_vec_scalar_insert_exp, _ARCH_PWR9]
- double __builtin_vec_scalar_insert_exp (unsigned int, unsigned int);
+ double __builtin_vec_scalar_insert_exp (unsigned long long, unsigned long long);
VSIEDP
- double __builtin_vec_scalar_insert_exp (double, unsigned int);
+ double __builtin_vec_scalar_insert_exp (double, unsigned long long);
VSIEDPF
- _Float128 __builtin_vec_scalar_insert_exp (unsigned long long, unsigned long long);
+ _Float128 __builtin_vec_scalar_insert_exp (unsigned __int128, unsigned long long);
VSIEQP
_Float128 __builtin_vec_scalar_insert_exp (_Float128, unsigned long long);
VSIEQPF
diff --git a/gcc/testsuite/gcc.dg/vmx/ops.c b/gcc/testsuite/gcc.dg/vmx/ops.c
index 5ba559e6f4b..7b56e9d8afa 100644
--- a/gcc/testsuite/gcc.dg/vmx/ops.c
+++ b/gcc/testsuite/gcc.dg/vmx/ops.c
@@ -192,42 +192,8 @@ void f2() {
*var_vec_b16++ = vec_splat(var_vec_b16[0], 7);
}
void f3() {
- *var_vec_b16++ = vec_srl(var_vec_b16[0], var_vec_u16[1]);
- *var_vec_b16++ = vec_srl(var_vec_b16[0], var_vec_u32[1]);
- *var_vec_b16++ = vec_srl(var_vec_b16[0], var_vec_u8[1]);
*var_vec_b16++ = vec_unpackh(var_vec_b8[0]);
*var_vec_b16++ = vec_unpackl(var_vec_b8[0]);
- *var_vec_b16++ = vec_vand(var_vec_b16[0], var_vec_b16[1]);
- *var_vec_b16++ = vec_vandc(var_vec_b16[0], var_vec_b16[1]);
- *var_vec_b16++ = vec_vcmpequh(var_vec_s16[0], var_vec_s16[1]);
- *var_vec_b16++ = vec_vcmpequh(var_vec_u16[0], var_vec_u16[1]);
- *var_vec_b16++ = vec_vcmpgtsh(var_vec_s16[0], var_vec_s16[1]);
- *var_vec_b16++ = vec_vcmpgtuh(var_vec_u16[0], var_vec_u16[1]);
- *var_vec_b16++ = vec_vmrghh(var_vec_b16[0], var_vec_b16[1]);
- *var_vec_b16++ = vec_vmrglh(var_vec_b16[0], var_vec_b16[1]);
- *var_vec_b16++ = vec_vnor(var_vec_b16[0], var_vec_b16[1]);
- *var_vec_b16++ = vec_vor(var_vec_b16[0], var_vec_b16[1]);
- *var_vec_b16++ = vec_vperm(var_vec_b16[0], var_vec_b16[1], var_vec_u8[2]);
- *var_vec_b16++ = vec_vpkuwum(var_vec_b32[0], var_vec_b32[1]);
- *var_vec_b16++ = vec_vsel(var_vec_b16[0], var_vec_b16[1], var_vec_b16[2]);
- *var_vec_b16++ = vec_vsel(var_vec_b16[0], var_vec_b16[1], var_vec_u16[2]);
- *var_vec_b16++ = vec_vsl(var_vec_b16[0], var_vec_u16[1]);
- *var_vec_b16++ = vec_vsl(var_vec_b16[0], var_vec_u32[1]);
- *var_vec_b16++ = vec_vsl(var_vec_b16[0], var_vec_u8[1]);
- *var_vec_b16++ = vec_vsplth(var_vec_b16[0], 0);
- *var_vec_b16++ = vec_vsplth(var_vec_b16[0], 1);
- *var_vec_b16++ = vec_vsplth(var_vec_b16[0], 2);
- *var_vec_b16++ = vec_vsplth(var_vec_b16[0], 3);
- *var_vec_b16++ = vec_vsplth(var_vec_b16[0], 4);
- *var_vec_b16++ = vec_vsplth(var_vec_b16[0], 5);
- *var_vec_b16++ = vec_vsplth(var_vec_b16[0], 6);
- *var_vec_b16++ = vec_vsplth(var_vec_b16[0], 7);
- *var_vec_b16++ = vec_vsr(var_vec_b16[0], var_vec_u16[1]);
- *var_vec_b16++ = vec_vsr(var_vec_b16[0], var_vec_u32[1]);
- *var_vec_b16++ = vec_vsr(var_vec_b16[0], var_vec_u8[1]);
- *var_vec_b16++ = vec_vupkhsb(var_vec_b8[0]);
- *var_vec_b16++ = vec_vupklsb(var_vec_b8[0]);
- *var_vec_b16++ = vec_vxor(var_vec_b16[0], var_vec_b16[1]);
*var_vec_b16++ = vec_xor(var_vec_b16[0], var_vec_b16[1]);
*var_vec_b32++ = vec_and(var_vec_b32[0], var_vec_b32[1]);
*var_vec_b32++ = vec_andc(var_vec_b32[0], var_vec_b32[1]);
@@ -255,40 +221,8 @@ void f3() {
*var_vec_b32++ = vec_splat(var_vec_b32[0], 3);
}
void f4() {
- *var_vec_b32++ = vec_srl(var_vec_b32[0], var_vec_u16[1]);
- *var_vec_b32++ = vec_srl(var_vec_b32[0], var_vec_u32[1]);
- *var_vec_b32++ = vec_srl(var_vec_b32[0], var_vec_u8[1]);
*var_vec_b32++ = vec_unpackh(var_vec_b16[0]);
*var_vec_b32++ = vec_unpackl(var_vec_b16[0]);
- *var_vec_b32++ = vec_vand(var_vec_b32[0], var_vec_b32[1]);
- *var_vec_b32++ = vec_vandc(var_vec_b32[0], var_vec_b32[1]);
- *var_vec_b32++ = vec_vcmpeqfp(var_vec_f32[0], var_vec_f32[1]);
- *var_vec_b32++ = vec_vcmpequw(var_vec_s32[0], var_vec_s32[1]);
- *var_vec_b32++ = vec_vcmpequw(var_vec_u32[0], var_vec_u32[1]);
- *var_vec_b32++ = vec_vcmpgefp(var_vec_f32[0], var_vec_f32[1]);
- *var_vec_b32++ = vec_vcmpgtfp(var_vec_f32[0], var_vec_f32[1]);
- *var_vec_b32++ = vec_vcmpgtsw(var_vec_s32[0], var_vec_s32[1]);
- *var_vec_b32++ = vec_vcmpgtuw(var_vec_u32[0], var_vec_u32[1]);
- *var_vec_b32++ = vec_vmrghw(var_vec_b32[0], var_vec_b32[1]);
- *var_vec_b32++ = vec_vmrglw(var_vec_b32[0], var_vec_b32[1]);
- *var_vec_b32++ = vec_vnor(var_vec_b32[0], var_vec_b32[1]);
- *var_vec_b32++ = vec_vor(var_vec_b32[0], var_vec_b32[1]);
- *var_vec_b32++ = vec_vperm(var_vec_b32[0], var_vec_b32[1], var_vec_u8[2]);
- *var_vec_b32++ = vec_vsel(var_vec_b32[0], var_vec_b32[1], var_vec_b32[2]);
- *var_vec_b32++ = vec_vsel(var_vec_b32[0], var_vec_b32[1], var_vec_u32[2]);
- *var_vec_b32++ = vec_vsl(var_vec_b32[0], var_vec_u16[1]);
- *var_vec_b32++ = vec_vsl(var_vec_b32[0], var_vec_u32[1]);
- *var_vec_b32++ = vec_vsl(var_vec_b32[0], var_vec_u8[1]);
- *var_vec_b32++ = vec_vspltw(var_vec_b32[0], 0);
- *var_vec_b32++ = vec_vspltw(var_vec_b32[0], 1);
- *var_vec_b32++ = vec_vspltw(var_vec_b32[0], 2);
- *var_vec_b32++ = vec_vspltw(var_vec_b32[0], 3);
- *var_vec_b32++ = vec_vsr(var_vec_b32[0], var_vec_u16[1]);
- *var_vec_b32++ = vec_vsr(var_vec_b32[0], var_vec_u32[1]);
- *var_vec_b32++ = vec_vsr(var_vec_b32[0], var_vec_u8[1]);
- *var_vec_b32++ = vec_vupkhsh(var_vec_b16[0]);
- *var_vec_b32++ = vec_vupklsh(var_vec_b16[0]);
- *var_vec_b32++ = vec_vxor(var_vec_b32[0], var_vec_b32[1]);
*var_vec_b32++ = vec_xor(var_vec_b32[0], var_vec_b32[1]);
*var_vec_b8++ = vec_and(var_vec_b8[0], var_vec_b8[1]);
*var_vec_b8++ = vec_andc(var_vec_b8[0], var_vec_b8[1]);
@@ -324,46 +258,6 @@ void f5() {
*var_vec_b8++ = vec_splat(var_vec_b8[0], 13);
*var_vec_b8++ = vec_splat(var_vec_b8[0], 14);
*var_vec_b8++ = vec_splat(var_vec_b8[0], 15);
- *var_vec_b8++ = vec_srl(var_vec_b8[0], var_vec_u16[1]);
- *var_vec_b8++ = vec_srl(var_vec_b8[0], var_vec_u32[1]);
- *var_vec_b8++ = vec_srl(var_vec_b8[0], var_vec_u8[1]);
- *var_vec_b8++ = vec_vand(var_vec_b8[0], var_vec_b8[1]);
- *var_vec_b8++ = vec_vandc(var_vec_b8[0], var_vec_b8[1]);
- *var_vec_b8++ = vec_vcmpequb(var_vec_s8[0], var_vec_s8[1]);
- *var_vec_b8++ = vec_vcmpequb(var_vec_u8[0], var_vec_u8[1]);
- *var_vec_b8++ = vec_vcmpgtsb(var_vec_s8[0], var_vec_s8[1]);
- *var_vec_b8++ = vec_vcmpgtub(var_vec_u8[0], var_vec_u8[1]);
- *var_vec_b8++ = vec_vmrghb(var_vec_b8[0], var_vec_b8[1]);
- *var_vec_b8++ = vec_vmrglb(var_vec_b8[0], var_vec_b8[1]);
- *var_vec_b8++ = vec_vnor(var_vec_b8[0], var_vec_b8[1]);
- *var_vec_b8++ = vec_vor(var_vec_b8[0], var_vec_b8[1]);
- *var_vec_b8++ = vec_vperm(var_vec_b8[0], var_vec_b8[1], var_vec_u8[2]);
- *var_vec_b8++ = vec_vpkuhum(var_vec_b16[0], var_vec_b16[1]);
- *var_vec_b8++ = vec_vsel(var_vec_b8[0], var_vec_b8[1], var_vec_b8[2]);
- *var_vec_b8++ = vec_vsel(var_vec_b8[0], var_vec_b8[1], var_vec_u8[2]);
- *var_vec_b8++ = vec_vsl(var_vec_b8[0], var_vec_u16[1]);
- *var_vec_b8++ = vec_vsl(var_vec_b8[0], var_vec_u32[1]);
- *var_vec_b8++ = vec_vsl(var_vec_b8[0], var_vec_u8[1]);
- *var_vec_b8++ = vec_vspltb(var_vec_b8[0], 0);
- *var_vec_b8++ = vec_vspltb(var_vec_b8[0], 1);
- *var_vec_b8++ = vec_vspltb(var_vec_b8[0], 2);
- *var_vec_b8++ = vec_vspltb(var_vec_b8[0], 3);
- *var_vec_b8++ = vec_vspltb(var_vec_b8[0], 4);
- *var_vec_b8++ = vec_vspltb(var_vec_b8[0], 5);
- *var_vec_b8++ = vec_vspltb(var_vec_b8[0], 6);
- *var_vec_b8++ = vec_vspltb(var_vec_b8[0], 7);
- *var_vec_b8++ = vec_vspltb(var_vec_b8[0], 8);
- *var_vec_b8++ = vec_vspltb(var_vec_b8[0], 9);
- *var_vec_b8++ = vec_vspltb(var_vec_b8[0], 10);
- *var_vec_b8++ = vec_vspltb(var_vec_b8[0], 11);
- *var_vec_b8++ = vec_vspltb(var_vec_b8[0], 12);
- *var_vec_b8++ = vec_vspltb(var_vec_b8[0], 13);
- *var_vec_b8++ = vec_vspltb(var_vec_b8[0], 14);
- *var_vec_b8++ = vec_vspltb(var_vec_b8[0], 15);
- *var_vec_b8++ = vec_vsr(var_vec_b8[0], var_vec_u16[1]);
- *var_vec_b8++ = vec_vsr(var_vec_b8[0], var_vec_u32[1]);
- *var_vec_b8++ = vec_vsr(var_vec_b8[0], var_vec_u8[1]);
- *var_vec_b8++ = vec_vxor(var_vec_b8[0], var_vec_b8[1]);
*var_vec_b8++ = vec_xor(var_vec_b8[0], var_vec_b8[1]);
}
void f6() {
@@ -525,8 +419,6 @@ void f9() {
*var_vec_p16++ = vec_splat(var_vec_p16[0], 5);
*var_vec_p16++ = vec_splat(var_vec_p16[0], 6);
*var_vec_p16++ = vec_splat(var_vec_p16[0], 7);
- *var_vec_p16++ = vec_srl(var_vec_p16[0], var_vec_u16[1]);
- *var_vec_p16++ = vec_srl(var_vec_p16[0], var_vec_u32[1]);
*var_vec_p16++ = vec_srl(var_vec_p16[0], var_vec_u8[1]);
*var_vec_p16++ = vec_sro(var_vec_p16[0], var_vec_s8[1]);
*var_vec_p16++ = vec_sro(var_vec_p16[0], var_vec_u8[1]);
@@ -631,8 +523,6 @@ void f11() {
*var_vec_s16++ = vec_splat_s16(-16);
*var_vec_s16++ = vec_sr(var_vec_s16[0], var_vec_u16[1]);
*var_vec_s16++ = vec_sra(var_vec_s16[0], var_vec_u16[1]);
- *var_vec_s16++ = vec_srl(var_vec_s16[0], var_vec_u16[1]);
- *var_vec_s16++ = vec_srl(var_vec_s16[0], var_vec_u32[1]);
*var_vec_s16++ = vec_srl(var_vec_s16[0], var_vec_u8[1]);
*var_vec_s16++ = vec_sro(var_vec_s16[0], var_vec_s8[1]);
*var_vec_s16++ = vec_sro(var_vec_s16[0], var_vec_u8[1]);
@@ -771,8 +661,6 @@ void f14() {
}
void f15() {
*var_vec_s32++ = vec_sra(var_vec_s32[0], var_vec_u32[1]);
- *var_vec_s32++ = vec_srl(var_vec_s32[0], var_vec_u16[1]);
- *var_vec_s32++ = vec_srl(var_vec_s32[0], var_vec_u32[1]);
*var_vec_s32++ = vec_srl(var_vec_s32[0], var_vec_u8[1]);
*var_vec_s32++ = vec_sro(var_vec_s32[0], var_vec_s8[1]);
*var_vec_s32++ = vec_sro(var_vec_s32[0], var_vec_u8[1]);
@@ -891,8 +779,6 @@ void f18() {
*var_vec_s8++ = vec_splat_s8(-16);
*var_vec_s8++ = vec_sr(var_vec_s8[0], var_vec_u8[1]);
*var_vec_s8++ = vec_sra(var_vec_s8[0], var_vec_u8[1]);
- *var_vec_s8++ = vec_srl(var_vec_s8[0], var_vec_u16[1]);
- *var_vec_s8++ = vec_srl(var_vec_s8[0], var_vec_u32[1]);
*var_vec_s8++ = vec_srl(var_vec_s8[0], var_vec_u8[1]);
*var_vec_s8++ = vec_sro(var_vec_s8[0], var_vec_s8[1]);
*var_vec_s8++ = vec_sro(var_vec_s8[0], var_vec_u8[1]);
@@ -1002,8 +888,6 @@ void f21() {
*var_vec_u16++ = vec_splat_u16(-16);
*var_vec_u16++ = vec_sr(var_vec_u16[0], var_vec_u16[1]);
*var_vec_u16++ = vec_sra(var_vec_u16[0], var_vec_u16[1]);
- *var_vec_u16++ = vec_srl(var_vec_u16[0], var_vec_u16[1]);
- *var_vec_u16++ = vec_srl(var_vec_u16[0], var_vec_u32[1]);
*var_vec_u16++ = vec_srl(var_vec_u16[0], var_vec_u8[1]);
*var_vec_u16++ = vec_sro(var_vec_u16[0], var_vec_s8[1]);
*var_vec_u16++ = vec_sro(var_vec_u16[0], var_vec_u8[1]);
@@ -1140,8 +1024,6 @@ void f23() {
*var_vec_u32++ = vec_sra(var_vec_u32[0], var_vec_u32[1]);
}
void f24() {
- *var_vec_u32++ = vec_srl(var_vec_u32[0], var_vec_u16[1]);
- *var_vec_u32++ = vec_srl(var_vec_u32[0], var_vec_u32[1]);
*var_vec_u32++ = vec_srl(var_vec_u32[0], var_vec_u8[1]);
*var_vec_u32++ = vec_sro(var_vec_u32[0], var_vec_s8[1]);
*var_vec_u32++ = vec_sro(var_vec_u32[0], var_vec_u8[1]);
@@ -1274,8 +1156,6 @@ void f27() {
*var_vec_u8++ = vec_splat_u8(-16);
*var_vec_u8++ = vec_sr(var_vec_u8[0], var_vec_u8[1]);
*var_vec_u8++ = vec_sra(var_vec_u8[0], var_vec_u8[1]);
- *var_vec_u8++ = vec_srl(var_vec_u8[0], var_vec_u16[1]);
- *var_vec_u8++ = vec_srl(var_vec_u8[0], var_vec_u32[1]);
*var_vec_u8++ = vec_srl(var_vec_u8[0], var_vec_u8[1]);
*var_vec_u8++ = vec_sro(var_vec_u8[0], var_vec_s8[1]);
*var_vec_u8++ = vec_sro(var_vec_u8[0], var_vec_u8[1]);
^ permalink raw reply [flat|nested] 29+ messages in thread
* [gcc(refs/users/wschmidt/heads/builtins4)] rs6000: More bug fixes
@ 2021-02-07 18:16 William Schmidt
0 siblings, 0 replies; 29+ messages in thread
From: William Schmidt @ 2021-02-07 18:16 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:e5040567804004f3bd8a63baec683fa7ca489d1c
commit e5040567804004f3bd8a63baec683fa7ca489d1c
Author: Bill Schmidt <wschmidt@linux.ibm.com>
Date: Thu Dec 17 16:25:22 2020 -0600
rs6000: More bug fixes
2020-12-17 Bill Schmidt <wschmidt@linux.ibm.com>
* config/rs6000/rs6000-builtin-new.def (LVEBX): Fix return type.
(LVEHX): Likewise.
(LVEWX): Likeiwse.
* config/rs6000/rs6000-gen-builtins.c (construct_fntype_id): Don't
use "ci" for pointers.
* config/rs6000/rs6000-overload.def (VEC_CMPEQ): Use Altivec
forms, not VSX forms, for now.
(VEC_CMPEQ_P): Likewise.
(VEC_CMPGE): Likewise.
(VEC_CMPGE_P): Likewise.
(VEC_CMPGT): Likewise.
(VEC_CMPGT_P): Likewise.
(VEC_NMSUB): Likewise.
(VEC_RE): Likewise.
Diff:
---
gcc/config/rs6000/rs6000-builtin-new.def | 6 +++---
gcc/config/rs6000/rs6000-gen-builtins.c | 5 ++++-
gcc/config/rs6000/rs6000-overload.def | 27 +++++++++++++++++++--------
3 files changed, 26 insertions(+), 12 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-builtin-new.def b/gcc/config/rs6000/rs6000-builtin-new.def
index 3ca7ccab705..8b54b17e1ce 100644
--- a/gcc/config/rs6000/rs6000-builtin-new.def
+++ b/gcc/config/rs6000/rs6000-builtin-new.def
@@ -306,13 +306,13 @@
fpmath vf __builtin_altivec_float_sisf (vsi);
FLOAT_V4SI_V4SF floatv4siv4sf2 {}
- pure vop __builtin_altivec_lvebx (signed long long, const void *);
+ pure vsc __builtin_altivec_lvebx (signed long long, const void *);
LVEBX altivec_lvebx {ldvec}
- pure vop __builtin_altivec_lvehx (signed long long, const void *);
+ pure vss __builtin_altivec_lvehx (signed long long, const void *);
LVEHX altivec_lvehx {ldvec}
- pure vop __builtin_altivec_lvewx (signed long long, const void *);
+ pure vsi __builtin_altivec_lvewx (signed long long, const void *);
LVEWX altivec_lvewx {ldvec}
pure vuc __builtin_altivec_lvsl (signed long long, const void *);
diff --git a/gcc/config/rs6000/rs6000-gen-builtins.c b/gcc/config/rs6000/rs6000-gen-builtins.c
index 57095dde58a..a4495e0c443 100644
--- a/gcc/config/rs6000/rs6000-gen-builtins.c
+++ b/gcc/config/rs6000/rs6000-gen-builtins.c
@@ -930,6 +930,7 @@ match_type (typeinfo *typedata, int voidok)
[const] [[signed|unsigned] <basetype> | <vectype>] [*]
+ #### Lie below ####
where "const" applies only to a <basetype> of "int". Legal values
of <basetype> are (for now):
@@ -1577,7 +1578,9 @@ construct_fntype_id (prototype *protoptr)
{
assert (argptr);
buf[bufi++] = '_';
- if (argptr->info.isconst && argptr->info.base == BT_INT)
+ if (argptr->info.isconst
+ && argptr->info.base == BT_INT
+ && !argptr->info.ispointer)
{
buf[bufi++] = 'c';
buf[bufi++] = 'i';
diff --git a/gcc/config/rs6000/rs6000-overload.def b/gcc/config/rs6000/rs6000-overload.def
index 2109c6ccb56..981e2fe944b 100644
--- a/gcc/config/rs6000/rs6000-overload.def
+++ b/gcc/config/rs6000/rs6000-overload.def
@@ -456,6 +456,7 @@
VCMPBFP
[VEC_CMPEQ, vec_cmpeq, __builtin_vec_cmpeq]
+; #### XVCMPEQSP{TARGET_VSX};VCMPEQFP
vbc __builtin_vec_cmpeq (vsc, vsc);
VCMPEQUB VCMPEQUB_VSC
vbc __builtin_vec_cmpeq (vuc, vuc);
@@ -481,12 +482,13 @@
vbll __builtin_vec_cmpeq (vbll, vbll);
VCMPEQUD VCMPEQUD_VBLL
vbi __builtin_vec_cmpeq (vf, vf);
- XVCMPEQSP
+ VCMPEQFP
vbll __builtin_vec_cmpeq (vd, vd);
XVCMPEQDP
; We skip generating a #define because of the C-versus-C++ complexity
; in altivec.h. Look there for the template-y details.
+; #### XVCMPEQSP_P{TARGET_VSX};VCMPEQFP_P
[VEC_CMPEQ_P, SKIP, __builtin_vec_vcmpeq_p]
signed int __builtin_vec_vcmpeq_p (signed int, vuc, vuc);
VCMPEQUB_P VCMPEQUB_PU
@@ -515,7 +517,7 @@
signed int __builtin_vec_vcmpeq_p (signed int, vbll, vbll);
VCMPEQUD_P VCMPEQUD_PB
signed int __builtin_vec_vcmpeq_p (signed int, vf, vf);
- XVCMPEQSP_P
+ VCMPEQFP_P
signed int __builtin_vec_vcmpeq_p (signed int, vd, vd);
XVCMPEQDP_P
@@ -523,6 +525,7 @@
signed int __builtin_byte_in_set (unsigned char, unsigned long long);
CMPEQB
+; #### XVCMPGESP{TARGET_VSX};VCMPGEFP
[VEC_CMPGE, vec_cmpge, __builtin_vec_cmpge]
vbc __builtin_vec_cmpge (vsc, vsc);
CMPGE_16QI CMPGE_16QI_VSC
@@ -541,7 +544,7 @@
vbll __builtin_vec_cmpge (vull, vull);
CMPGE_2DI CMPGE_2DI_VULL
vbi __builtin_vec_cmpge (vf, vf);
- XVCMPGESP
+ VCMPGEFP
vbll __builtin_vec_cmpge (vd, vd);
XVCMPGEDP
@@ -549,6 +552,7 @@
; in altivec.h. Look there for the template-y details.
; See altivec_build_resolved_builtin for how we deal with VEC_CMPGE_P.
; It's quite strange and horrible!
+; #### XVCMPGESP_P{TARGET_VSX};VCMPGEFP_P
[VEC_CMPGE_P, SKIP, __builtin_vec_vcmpge_p]
signed int __builtin_vec_vcmpge_p (signed int, vuc, vuc);
VCMPGTUB_P VCMPGTUB_PR
@@ -567,10 +571,11 @@
signed int __builtin_vec_vcmpge_p (signed int, vsll, vsll);
VCMPGTSD_P VCMPGTSD_PR
signed int __builtin_vec_vcmpge_p (signed int, vf, vf);
- XVCMPGESP_P
+ VCMPGEFP_P
signed int __builtin_vec_vcmpge_p (signed int, vd, vd);
XVCMPGEDP_P
+; #### XVCMPGTSP{TARGET_VSX};VCMPGTFP
[VEC_CMPGT, vec_cmpgt, __builtin_vec_cmpgt]
vbc __builtin_vec_cmpgt (vsc, vsc);
VCMPGTSB
@@ -589,12 +594,13 @@
vbll __builtin_vec_cmpgt (vull, vull);
VCMPGTUD
vbi __builtin_vec_cmpgt (vf, vf);
- XVCMPGTSP
+ VCMPGTFP
vbll __builtin_vec_cmpgt (vd, vd);
XVCMPGTDP
; We skip generating a #define because of the C-versus-C++ complexity
; in altivec.h. Look there for the template-y details.
+; #### XVCMPGTSP_P{TARGET_VSX};VCMPGTFP_P
[VEC_CMPGT_P, SKIP, __builtin_vec_vcmpgt_p]
signed int __builtin_vec_vcmpgt_p (signed int, vuc, vuc);
VCMPGTUB_P
@@ -613,7 +619,7 @@
signed int __builtin_vec_vcmpgt_p (signed int, vsll, vsll);
VCMPGTSD_P
signed int __builtin_vec_vcmpgt_p (signed int, vf, vf);
- XVCMPGTSP_P
+ VCMPGTFP_P
signed int __builtin_vec_vcmpgt_p (signed int, vd, vd);
XVCMPGTDP_P
@@ -2084,9 +2090,10 @@
vd __builtin_vec_nmadd (vd, vd, vd);
XVNMADDDP
+; #### XVNMSUBDP{TARGET_VSX};VNMSUBFP
[VEC_NMSUB, vec_nmsub, __builtin_vec_nmsub]
vf __builtin_vec_nmsub (vf, vf, vf);
- XVNMSUBSP
+ VNMSUBFP
vd __builtin_vec_nmsub (vd, vd, vd);
XVNMSUBDP
@@ -2354,9 +2361,13 @@
vsi __builtin_vec_promote (vsi);
ABS_V4SI PROMOTE_FAKERY
+; Opportunity for improvement: We can use XVRESP instead of VREFP for
+; TARGET_VSX. We would need conditional dispatch to allow two possibilities.
+; Some syntax like "XVRESP{TARGET_VSX};VREFP".
+; TODO. ####
[VEC_RE, vec_re, __builtin_vec_re]
vf __builtin_vec_re (vf);
- XVRESP
+ VREFP
vd __builtin_vec_re (vd);
XVREDP
^ permalink raw reply [flat|nested] 29+ messages in thread
* [gcc(refs/users/wschmidt/heads/builtins4)] rs6000: More bug fixes
@ 2021-02-07 17:48 William Schmidt
0 siblings, 0 replies; 29+ messages in thread
From: William Schmidt @ 2021-02-07 17:48 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:906a91028d5862497ca6957353c2ee8ffded5aad
commit 906a91028d5862497ca6957353c2ee8ffded5aad
Author: Bill Schmidt <wschmidt@linux.ibm.com>
Date: Sun Feb 7 11:48:07 2021 -0600
rs6000: More bug fixes
2021-02-07 Bill Schmidt <wschmidt@linux.ibm.com>
gcc/
* config/rs6000/rs6000-builtin-new.def: Clean up.
* config/rs6000/rs6000-gen-builtins.c (write_init_file): Remove
timevar stuff.
* timevar.def (TV_BILL): Remove.
Diff:
---
gcc/config/rs6000/rs6000-builtin-new.def | 8 --------
gcc/config/rs6000/rs6000-gen-builtins.c | 3 ---
gcc/timevar.def | 3 ---
3 files changed, 14 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-builtin-new.def b/gcc/config/rs6000/rs6000-builtin-new.def
index 24fd7ed182d..5e63df13516 100644
--- a/gcc/config/rs6000/rs6000-builtin-new.def
+++ b/gcc/config/rs6000/rs6000-builtin-new.def
@@ -1735,12 +1735,8 @@
const vd __builtin_vsx_xvcvsxwdp (vsi);
XVCVSXWDP vsx_xvcvsxwdp {}
-; Need to pick one or the other here!! ####
-; The first is needed to make vec_float work correctly.
const vf __builtin_vsx_xvcvsxwsp (vsi);
XVCVSXWSP vsx_floatv4siv4sf2 {}
-; const vf __builtin_vsx_xvcvsxwsp (vsi);
-; XVCVSXWSP_V4SF vsx_xvcvsxwdp {}
const vd __builtin_vsx_xvcvuxddp (vull);
XVCVUXDDP vsx_floatunsv2div2df2 {}
@@ -1758,12 +1754,8 @@
const vd __builtin_vsx_xvcvuxwdp (vsi);
XVCVUXWDP vsx_xvcvuxwdp {}
-; Need to pick one or the other here!! ####
-; The first is needed to make vec_float work correctly.
const vf __builtin_vsx_xvcvuxwsp (vui);
XVCVUXWSP vsx_floatunsv4siv4sf2 {}
-; const vf __builtin_vsx_xvcvuxwsp (vui);
-; XVCVUXWSP_V4SF vsx_xvcvuxwsp {}
fpmath vd __builtin_vsx_xvdivdp (vd, vd);
XVDIVDP divv2df3 {}
diff --git a/gcc/config/rs6000/rs6000-gen-builtins.c b/gcc/config/rs6000/rs6000-gen-builtins.c
index b75b29303dd..07222228310 100644
--- a/gcc/config/rs6000/rs6000-gen-builtins.c
+++ b/gcc/config/rs6000/rs6000-gen-builtins.c
@@ -2691,7 +2691,6 @@ write_init_file ()
fprintf (init_file, "#include \"tree.h\"\n");
fprintf (init_file, "#include \"langhooks.h\"\n");
fprintf (init_file, "#include \"insn-codes.h\"\n");
- fprintf (init_file, "#include \"timevar.h\"\n");
fprintf (init_file, "#include \"rs6000-builtins.h\"\n");
fprintf (init_file, "\n");
@@ -2715,7 +2714,6 @@ write_init_file ()
fprintf (init_file, "rs6000_autoinit_builtins ()\n");
fprintf (init_file, "{\n");
fprintf (init_file, " tree t;\n");
- fprintf (init_file, " timevar_start (TV_BILL);\n");
rbt_inorder_callback (&fntype_rbt, fntype_rbt.rbt_root, write_fntype_init);
fprintf (init_file, "\n");
@@ -2729,7 +2727,6 @@ write_init_file ()
write_init_bif_table ();
write_init_ovld_table ();
- fprintf (init_file, " timevar_stop (TV_BILL);\n");
fprintf (init_file, "}\n\n");
fprintf (init_file,
diff --git a/gcc/timevar.def b/gcc/timevar.def
index 371b831449c..1f85e2db558 100644
--- a/gcc/timevar.def
+++ b/gcc/timevar.def
@@ -340,6 +340,3 @@ DEFTIMEVAR (TV_ANALYZER_WORKLIST , "analyzer: processing worklist")
DEFTIMEVAR (TV_ANALYZER_DUMP , "analyzer: dump")
DEFTIMEVAR (TV_ANALYZER_DIAGNOSTICS , "analyzer: emitting diagnostics")
DEFTIMEVAR (TV_ANALYZER_SHORTEST_PATHS, "analyzer: shortest paths")
-
-/* Bill's timevar! */
-DEFTIMEVAR (TV_BILL, "builtin initialization")
^ permalink raw reply [flat|nested] 29+ messages in thread
* [gcc(refs/users/wschmidt/heads/builtins4)] rs6000: More bug fixes
@ 2021-02-01 0:34 William Schmidt
0 siblings, 0 replies; 29+ messages in thread
From: William Schmidt @ 2021-02-01 0:34 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:57d39f823dcf59d28b7badf42431fdaadcf7e91a
commit 57d39f823dcf59d28b7badf42431fdaadcf7e91a
Author: Bill Schmidt <wschmidt@linux.ibm.com>
Date: Sun Jan 31 18:34:34 2021 -0600
rs6000: More bug fixes
2021-01-31 Bill Schmidt <wschmidt@linux.ibm.com>
gcc/
* config/rs6000/altivec.h: Update deprecated interfaces.
* config/rs6000/rs6000-builtin-new.def: Miscellaneous fixes.
* config/rs6000/rs6000-overload.def: Miscellaneous fixes.
gcc/testsuite/
* gcc.target/powerpc/vec-gnb-2.c: Adjust.
* gcc.target/powerpc/vsu/vec-all-nez-7.c: Adjust.
* gcc.target/powerpc/vsu/vec-any-eqz-7.c: Adjust.
* gcc.target/powerpc/vsu/vec-cmpnez-7.c: Adjust.
* gcc.target/powerpc/vsu/vec-cntlz-lsbb-2.c: Adjust.
* gcc.target/powerpc/vsu/vec-cnttz-lsbb-2.c: Adjust.
* gcc.target/powerpc/vsu/vec-xst-len-12.c: Adjust.
Diff:
---
gcc/config/rs6000/altivec.h | 16 +++++++------
gcc/config/rs6000/rs6000-builtin-new.def | 26 ++++++++++----------
gcc/config/rs6000/rs6000-overload.def | 28 ++++++++++++++--------
gcc/testsuite/gcc.target/powerpc/vec-gnb-2.c | 2 +-
.../gcc.target/powerpc/vsu/vec-all-nez-7.c | 2 +-
.../gcc.target/powerpc/vsu/vec-any-eqz-7.c | 2 +-
.../gcc.target/powerpc/vsu/vec-cmpnez-7.c | 2 +-
.../gcc.target/powerpc/vsu/vec-cntlz-lsbb-2.c | 2 +-
.../gcc.target/powerpc/vsu/vec-cnttz-lsbb-2.c | 2 +-
.../gcc.target/powerpc/vsu/vec-xst-len-12.c | 2 +-
10 files changed, 47 insertions(+), 37 deletions(-)
diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h
index c68e854f30f..3d6f259fa1e 100644
--- a/gcc/config/rs6000/altivec.h
+++ b/gcc/config/rs6000/altivec.h
@@ -58,18 +58,20 @@
#include "rs6000-vecdefines.h"
/* Deprecated interfaces. */
-#define vec_vsld vec_sld
-#define vec_vsrad vec_srad
-#define vec_vsrd vec_srd
+#ifdef _ARCH_PWR8
+#define vec_vsld vec_sl
+#define vec_vsrd vec_sr
+#define vec_vsrad vec_sra
+#endif
#ifdef _ARCH_PWR9
#define __builtin_vec_vadub __builtin_vec_vadu
#define __builtin_vec_vaduh __builtin_vec_vadu
#define __builtin_vec_vaduw __builtin_vec_vadu
-#define __builtin_vec_vprtybw __builtin_vec_vprtyb
-#define __builtin_vec_vprtybd __builtin_vec_vprtyb
-#define __builtin_vec_vprtybq __builtin_vec_vprtyb
-#define vec_vrlnm vec_rlnm
+#define vec_vprtybw vec_vprtyb
+#define vec_vprtybd vec_vprtyb
+#define vec_vprtybq vec_vprtyb
+#define vec_vrlnm __builtin_vec_rlnm
#endif
/* Synonyms. */
diff --git a/gcc/config/rs6000/rs6000-builtin-new.def b/gcc/config/rs6000/rs6000-builtin-new.def
index 84654e872e0..24fd7ed182d 100644
--- a/gcc/config/rs6000/rs6000-builtin-new.def
+++ b/gcc/config/rs6000/rs6000-builtin-new.def
@@ -1647,37 +1647,37 @@
fpmath vf __builtin_vsx_xvaddsp (vf, vf);
XVADDSP addv4sf3 {}
- const vbll __builtin_vsx_xvcmpeqdp (vd, vd);
+ const vd __builtin_vsx_xvcmpeqdp (vd, vd);
XVCMPEQDP vector_eqv2df {}
const signed int __builtin_vsx_xvcmpeqdp_p (signed int, vd, vd);
XVCMPEQDP_P vector_eq_v2df_p {pred}
- const vbi __builtin_vsx_xvcmpeqsp (vf, vf);
+ const vf __builtin_vsx_xvcmpeqsp (vf, vf);
XVCMPEQSP vector_eqv4sf {}
const signed int __builtin_vsx_xvcmpeqsp_p (signed int, vf, vf);
XVCMPEQSP_P vector_eq_v4sf_p {pred}
- const vbll __builtin_vsx_xvcmpgedp (vd, vd);
+ const vd __builtin_vsx_xvcmpgedp (vd, vd);
XVCMPGEDP vector_gev2df {}
const signed int __builtin_vsx_xvcmpgedp_p (signed int, vd, vd);
XVCMPGEDP_P vector_ge_v2df_p {pred}
- const vbi __builtin_vsx_xvcmpgesp (vf, vf);
+ const vf __builtin_vsx_xvcmpgesp (vf, vf);
XVCMPGESP vector_gev4sf {}
const signed int __builtin_vsx_xvcmpgesp_p (signed int, vf, vf);
XVCMPGESP_P vector_ge_v4sf_p {pred}
- const vbll __builtin_vsx_xvcmpgtdp (vd, vd);
+ const vd __builtin_vsx_xvcmpgtdp (vd, vd);
XVCMPGTDP vector_gtv2df {}
const signed int __builtin_vsx_xvcmpgtdp_p (signed int, vd, vd);
XVCMPGTDP_P vector_gt_v2df_p {pred}
- const vbi __builtin_vsx_xvcmpgtsp (vf, vf);
+ const vf __builtin_vsx_xvcmpgtsp (vf, vf);
XVCMPGTSP vector_gtv4sf {}
const signed int __builtin_vsx_xvcmpgtsp_p (signed int, vf, vf);
@@ -1927,25 +1927,25 @@
const vsi __builtin_vsx_xxmrglw_4si (vsi, vsi);
XXMRGLW_4SI vsx_xxmrglw_v4si {}
- const vsc __builtin_vsx_xxpermdi_16qi (vsc, vsc, const int<1>);
+ const vsc __builtin_vsx_xxpermdi_16qi (vsc, vsc, const int<2>);
XXPERMDI_16QI vsx_xxpermdi_v16qi {}
- const vsq __builtin_vsx_xxpermdi_1ti (vsq, vsq, const int<1>);
+ const vsq __builtin_vsx_xxpermdi_1ti (vsq, vsq, const int<2>);
XXPERMDI_1TI vsx_xxpermdi_v1ti {}
- const vd __builtin_vsx_xxpermdi_2df (vd, vd, const int<1>);
+ const vd __builtin_vsx_xxpermdi_2df (vd, vd, const int<2>);
XXPERMDI_2DF vsx_xxpermdi_v2df {}
- const vsll __builtin_vsx_xxpermdi_2di (vsll, vsll, const int<1>);
+ const vsll __builtin_vsx_xxpermdi_2di (vsll, vsll, const int<2>);
XXPERMDI_2DI vsx_xxpermdi_v2di {}
- const vf __builtin_vsx_xxpermdi_4sf (vf, vf, const int<1>);
+ const vf __builtin_vsx_xxpermdi_4sf (vf, vf, const int<2>);
XXPERMDI_4SF vsx_xxpermdi_v4sf {}
- const vsi __builtin_vsx_xxpermdi_4si (vsi, vsi, const int<1>);
+ const vsi __builtin_vsx_xxpermdi_4si (vsi, vsi, const int<2>);
XXPERMDI_4SI vsx_xxpermdi_v4si {}
- const vss __builtin_vsx_xxpermdi_8hi (vss, vss, const int<1>);
+ const vss __builtin_vsx_xxpermdi_8hi (vss, vss, const int<2>);
XXPERMDI_8HI vsx_xxpermdi_v8hi {}
const vsc __builtin_vsx_xxsel_16qi (vsc, vsc, vsc);
diff --git a/gcc/config/rs6000/rs6000-overload.def b/gcc/config/rs6000/rs6000-overload.def
index a2651e59c9f..90d17ee90e1 100644
--- a/gcc/config/rs6000/rs6000-overload.def
+++ b/gcc/config/rs6000/rs6000-overload.def
@@ -992,7 +992,7 @@
signed int __builtin_vec_vcmpne_p (signed int, vbll, vsll);
VCMPNED_P VCMPNED_P_SB
-[VEC_CMPNEZ, vec_cmpnez, __builtin_vec_cmpnez, _ARCH_PWR9]
+[VEC_CMPNEZ, vec_cmpnez, __builtin_vec_vcmpnez, _ARCH_PWR9]
vbc __builtin_vec_cmpnez (vsc, vsc);
CMPNEZB CMPNEZB_S
vbc __builtin_vec_cmpnez (vuc, vuc);
@@ -1654,19 +1654,19 @@
MTVSRBM
[VEC_GENHM, vec_genhm, __builtin_vec_mtvsrhm, _ARCH_PWR10]
- vuc __builtin_vec_mtvsrhm (unsigned long long);
+ vus __builtin_vec_mtvsrhm (unsigned long long);
MTVSRHM
[VEC_GENWM, vec_genwm, __builtin_vec_mtvsrwm, _ARCH_PWR10]
- vuc __builtin_vec_mtvsrwm (unsigned long long);
+ vui __builtin_vec_mtvsrwm (unsigned long long);
MTVSRWM
[VEC_GENDM, vec_gendm, __builtin_vec_mtvsrdm, _ARCH_PWR10]
- vuc __builtin_vec_mtvsrdm (unsigned long long);
+ vull __builtin_vec_mtvsrdm (unsigned long long);
MTVSRDM
[VEC_GENQM, vec_genqm, __builtin_vec_mtvsrqm, _ARCH_PWR10]
- vuc __builtin_vec_mtvsrqm (unsigned long long);
+ vuq __builtin_vec_mtvsrqm (unsigned long long);
MTVSRQM
[VEC_GENPCVM, vec_genpcvm, __builtin_vec_xxgenpcvm, _ARCH_PWR10]
@@ -3462,7 +3462,7 @@
vf __builtin_vec_xxspltiw (float);
VXXSPLTIW_V4SF
-[VEC_SPLATID, vec_splatid, __builtin_vec_xxspltid, ARCH_PWR10]
+[VEC_SPLATID, vec_splatid, __builtin_vec_xxspltid, _ARCH_PWR10]
vd __builtin_vec_xxspltid (float);
VXXSPLTIDP
@@ -4417,6 +4417,8 @@
LXVW4X_V16QI LXVW4X_VUC
vuc __builtin_vec_vsx_ld (signed long long, const unsigned char *);
LXVW4X_V16QI LXVW4X_UC
+ vbc __builtin_vec_vsx_ld (signed long long, const vbc *);
+ LXVW4X_V16QI LXVW4X_VBC
vss __builtin_vec_vsx_ld (signed long long, const vss *);
LXVW4X_V8HI LXVW4X_VSS
vss __builtin_vec_vsx_ld (signed long long, const signed short *);
@@ -4425,6 +4427,8 @@
LXVW4X_V8HI LXVW4X_VUS
vus __builtin_vec_vsx_ld (signed long long, const unsigned short *);
LXVW4X_V8HI LXVW4X_US
+ vbs __builtin_vec_vsx_ld (signed long long, const vbs *);
+ LXVW4X_V8HI LXVW4X_VBS
vp __builtin_vec_vsx_ld (signed long long, const vp *);
LXVW4X_V8HI LXVW4X_P
vsi __builtin_vec_vsx_ld (signed long long, const vsi *);
@@ -4435,6 +4439,8 @@
LXVW4X_V4SI LXVW4X_VUI
vui __builtin_vec_vsx_ld (signed long long, const unsigned int *);
LXVW4X_V4SI LXVW4X_UI
+ vbi __builtin_vec_vsx_ld (signed long long, const vbi *);
+ LXVW4X_V4SI LXVW4X_VBI
vsll __builtin_vec_vsx_ld (signed long long, const vsll *);
LXVD2X_V2DI LXVD2X_VSLL
vsll __builtin_vec_vsx_ld (signed long long, const signed long long *);
@@ -4443,6 +4449,8 @@
LXVD2X_V2DI LXVD2X_VULL
vull __builtin_vec_vsx_ld (signed long long, const unsigned long long *);
LXVD2X_V2DI LXVD2X_ULL
+ vbll __builtin_vec_vsx_ld (signed long long, const vbll *);
+ LXVD2X_V2DI LXVD2X_VBLL
vsq __builtin_vec_vsx_ld (signed long long, const vsq *);
LXVD2X_V1TI LXVD2X_VSQ
vsq __builtin_vec_vsx_ld (signed long long, const signed __int128 *);
@@ -4519,13 +4527,13 @@
SE_LXVRDX
[VEC_XL_ZEXT, vec_xl_zext, __builtin_vec_xl_zext, _ARCH_PWR10]
- vsq __builtin_vec_xl_zext (signed long long, const signed char *);
+ vuq __builtin_vec_xl_zext (signed long long, const unsigned char *);
ZE_LXVRBX
- vsq __builtin_vec_xl_zext (signed long long, const signed short *);
+ vuq __builtin_vec_xl_zext (signed long long, const unsigned short *);
ZE_LXVRHX
- vsq __builtin_vec_xl_zext (signed long long, const signed int *);
+ vuq __builtin_vec_xl_zext (signed long long, const unsigned int *);
ZE_LXVRWX
- vsq __builtin_vec_xl_zext (signed long long, const signed long long *);
+ vuq __builtin_vec_xl_zext (signed long long, const unsigned long long *);
ZE_LXVRDX
[VEC_XOR, vec_xor, __builtin_vec_xor]
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-gnb-2.c b/gcc/testsuite/gcc.target/powerpc/vec-gnb-2.c
index 895bb953b37..4e59cbffa17 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-gnb-2.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-gnb-2.c
@@ -20,7 +20,7 @@ do_vec_gnb (vector unsigned __int128 source, int stride)
case 5:
return vec_gnb (source, 1); /* { dg-error "between 2 and 7" } */
case 6:
- return vec_gnb (source, stride); /* { dg-error "unsigned literal" } */
+ return vec_gnb (source, stride); /* { dg-error "literal" } */
case 7:
return vec_gnb (source, 7);
diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-7.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-7.c
index f53c6dca0a9..d1ef054b488 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-7.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-7.c
@@ -12,5 +12,5 @@ test_all_not_equal_and_not_zero (vector unsigned short *arg1_p,
vector unsigned short arg_2 = *arg2_p;
return __builtin_vec_vcmpnez_p (__CR6_LT, arg_1, arg_2);
- /* { dg-error "'__builtin_altivec_vcmpnezh_p' requires the '-mcpu=power9' option" "" { target *-*-* } .-1 } */
+ /* { dg-error "'__builtin_altivec_vcmpnezh_p' requires the '-mpower9-vector' option" "" { target *-*-* } .-1 } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-7.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-7.c
index 757acd93110..b5cdea5fb3e 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-7.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-7.c
@@ -11,5 +11,5 @@ test_any_equal (vector unsigned int *arg1_p, vector unsigned int *arg2_p)
vector unsigned int arg_2 = *arg2_p;
return __builtin_vec_vcmpnez_p (__CR6_LT_REV, arg_1, arg_2);
- /* { dg-error "'__builtin_altivec_vcmpnezw_p' requires the '-mcpu=power9' option" "" { target *-*-* } .-1 } */
+ /* { dg-error "'__builtin_altivec_vcmpnezw_p' requires the '-mpower9-vector' option" "" { target *-*-* } .-1 } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-7.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-7.c
index 811b32f1c32..320421e6028 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-7.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-7.c
@@ -10,5 +10,5 @@ fetch_data (vector unsigned int *arg1_p, vector unsigned int *arg2_p)
vector unsigned int arg_1 = *arg1_p;
vector unsigned int arg_2 = *arg2_p;
- return __builtin_vec_vcmpnez (arg_1, arg_2); /* { dg-error "'__builtin_altivec_vcmpnezw' requires the '-mcpu=power9' option" } */
+ return __builtin_vec_vcmpnez (arg_1, arg_2); /* { dg-error "'__builtin_altivec_vcmpnezw' requires the '-mpower9-vector' option" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-2.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-2.c
index 6ee066d1eff..251285536c2 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-2.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-2.c
@@ -9,5 +9,5 @@ count_leading_zero_byte_bits (vector unsigned char *arg1_p)
{
vector unsigned char arg_1 = *arg1_p;
- return __builtin_vec_vclzlsbb (arg_1); /* { dg-error "'__builtin_altivec_vclzlsbb_v16qi' requires the '-mcpu=power9' option" } */
+ return __builtin_vec_vclzlsbb (arg_1); /* { dg-error "'__builtin_altivec_vclzlsbb_v16qi' requires the '-mpower9-vector' option" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-2.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-2.c
index ecd0add70d0..83ca92daced 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-2.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-2.c
@@ -9,5 +9,5 @@ count_trailing_zero_byte_bits (vector unsigned char *arg1_p)
{
vector unsigned char arg_1 = *arg1_p;
- return __builtin_vec_vctzlsbb (arg_1); /* { dg-error "'__builtin_altivec_vctzlsbb_v16qi' requires the '-mcpu=power9' option" } */
+ return __builtin_vec_vctzlsbb (arg_1); /* { dg-error "'__builtin_altivec_vctzlsbb_v16qi' requires the '-mpower9-vector' option" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-12.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-12.c
index 3a51132a5a2..f30d49cb4cc 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-12.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-12.c
@@ -13,5 +13,5 @@ store_data (vector double *datap, double *address, size_t length)
{
vector double data = *datap;
- __builtin_vec_stxvl (data, address, length); /* { dg-error "'__builtin_vec_stxvl' is not supported in this compiler configuration" } */
+ __builtin_vec_stxvl (data, address, length); /* { dg-error "'__builtin_altivec_stxvl' requires the" } */
}
^ permalink raw reply [flat|nested] 29+ messages in thread
* [gcc(refs/users/wschmidt/heads/builtins4)] rs6000: More bug fixes
@ 2021-01-28 23:21 William Schmidt
0 siblings, 0 replies; 29+ messages in thread
From: William Schmidt @ 2021-01-28 23:21 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:fa6a1a08419013e7c541ecd3102480e6c49f2a4e
commit fa6a1a08419013e7c541ecd3102480e6c49f2a4e
Author: Bill Schmidt <wschmidt@linux.ibm.com>
Date: Thu Jan 28 17:21:38 2021 -0600
rs6000: More bug fixes
2021-01-28 Bill Schmidt <wschmidt@linux.ibm.com>
gcc/
* config/rs6000/altivec.h: Add deprecated interfaces.
* config/rs6000/rs6000-builtin-new.def (__builtin_altivec_vgnb):
Fix prototype.
* config/rs6000/rs6000-overload.def: Miscellaneous fixes.
gcc/testsuite/
* gcc.target/powerpc/p9-vparity.c: Revert earlier changes.
Diff:
---
gcc/config/rs6000/altivec.h | 22 ++++++++++++------
gcc/config/rs6000/rs6000-builtin-new.def | 2 +-
gcc/config/rs6000/rs6000-overload.def | 24 ++++++++++++++++++--
gcc/testsuite/gcc.target/powerpc/p9-vparity.c | 32 +++++++++++++--------------
4 files changed, 54 insertions(+), 26 deletions(-)
diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h
index 312e5657623..c68e854f30f 100644
--- a/gcc/config/rs6000/altivec.h
+++ b/gcc/config/rs6000/altivec.h
@@ -57,6 +57,21 @@
#include "rs6000-vecdefines.h"
+/* Deprecated interfaces. */
+#define vec_vsld vec_sld
+#define vec_vsrad vec_srad
+#define vec_vsrd vec_srd
+
+#ifdef _ARCH_PWR9
+#define __builtin_vec_vadub __builtin_vec_vadu
+#define __builtin_vec_vaduh __builtin_vec_vadu
+#define __builtin_vec_vaduw __builtin_vec_vadu
+#define __builtin_vec_vprtybw __builtin_vec_vprtyb
+#define __builtin_vec_vprtybd __builtin_vec_vprtyb
+#define __builtin_vec_vprtybq __builtin_vec_vprtyb
+#define vec_vrlnm vec_rlnm
+#endif
+
/* Synonyms. */
/* Functions that are resolved by the backend to one of the
typed builtins. */
@@ -264,11 +279,4 @@ __altivec_scalar_pred(vec_any_nle,
to #define vec_step to __builtin_vec_step. */
#define vec_step(x) __builtin_vec_step (* (__typeof__ (x) *) 0)
-/* Deprecated interfaces. */
-#ifdef _ARCH_PWR9
-#define __builtin_vec_vadub __builtin_vec_vadu
-#define __builtin_vec_vaduh __builtin_vec_vadu
-#define __builtin_vec_vaduw __builtin_vec_vadu
-#endif
-
#endif /* _ALTIVEC_H */
diff --git a/gcc/config/rs6000/rs6000-builtin-new.def b/gcc/config/rs6000/rs6000-builtin-new.def
index 417fd2a35dd..84654e872e0 100644
--- a/gcc/config/rs6000/rs6000-builtin-new.def
+++ b/gcc/config/rs6000/rs6000-builtin-new.def
@@ -3183,7 +3183,7 @@
const signed int __builtin_altivec_vextractmw (vui);
VEXTRACTMW vec_extract_v4si {}
- const unsigned long long __builtin_altivec_vgnb (vuq, const int <2,7>);
+ const unsigned long long __builtin_altivec_vgnb (vull, const int <2,7>);
VGNB vgnb {}
const vuc __builtin_altivec_vinsgubvlx (unsigned int, vuc, unsigned int);
diff --git a/gcc/config/rs6000/rs6000-overload.def b/gcc/config/rs6000/rs6000-overload.def
index 344c78b6a83..a2651e59c9f 100644
--- a/gcc/config/rs6000/rs6000-overload.def
+++ b/gcc/config/rs6000/rs6000-overload.def
@@ -3071,7 +3071,7 @@
vull __builtin_vec_rl (vull, vull);
VRLD VRLD_VULL
-[VEC_RLMI, vec_rlmi, __builtin_vec_rlmi]
+[VEC_RLMI, vec_rlmi, __builtin_vec_rlmi, _ARCH_PWR9]
vui __builtin_vec_rlmi (vui, vui, vui);
VRLWMI
vull __builtin_vec_rlmi (vull, vull, vull);
@@ -3079,7 +3079,7 @@
; We SKIP vec_rlnm so that altivec.h can define it as the three-operand
; form we expose to the users.
-[VEC_RLNM, SKIP, __builtin_vec_rlnm]
+[VEC_RLNM, SKIP, __builtin_vec_rlnm, _ARCH_PWR9]
vui __builtin_vec_rlnm (vui, vui);
VRLWNM
vull __builtin_vec_rlnm (vull, vull);
@@ -4320,6 +4320,26 @@
vd __builtin_vec_insert_exp (vull, vull);
VIEDP VIEDP_VULL
+; It is truly unfortunate that vec_vprtyb has an incompatible set of
+; interfaces with vec_parity_lsbb. So we can't even deprecate this.
+[VEC_VPRTYB, vec_vprtyb, __builtin_vec_vprtyb, _ARCH_PWR9]
+ vsi __builtin_vec_vprtyb (vsi);
+ VPRTYBW VPRTYB_VSI
+ vui __builtin_vec_vprtyb (vui);
+ VPRTYBW VPRTYB_VUI
+ vsll __builtin_vec_vprtyb (vsll);
+ VPRTYBD VPRTYB_VSLL
+ vull __builtin_vec_vprtyb (vull);
+ VPRTYBD VPRTYB_VULL
+ vsq __builtin_vec_vprtyb (vsq);
+ VPRTYBQ VPRTYB_VSQ
+ vuq __builtin_vec_vprtyb (vuq);
+ VPRTYBQ VPRTYB_VUQ
+ signed __int128 __builtin_vec_vprtyb (signed __int128);
+ VPRTYBQ VPRTYB_SQ
+ unsigned __int128 __builtin_vec_vprtyb (unsigned __int128);
+ VPRTYBQ VPRTYB_UQ
+
[VEC_VSCEEQ, scalar_cmp_exp_eq, __builtin_vec_scalar_cmp_exp_eq, _ARCH_PWR9]
signed int __builtin_vec_scalar_cmp_exp_eq (double, double);
VSCEDPEQ
diff --git a/gcc/testsuite/gcc.target/powerpc/p9-vparity.c b/gcc/testsuite/gcc.target/powerpc/p9-vparity.c
index 8897a5b6b7f..f4aba1567cd 100644
--- a/gcc/testsuite/gcc.target/powerpc/p9-vparity.c
+++ b/gcc/testsuite/gcc.target/powerpc/p9-vparity.c
@@ -9,97 +9,97 @@
vector int
parity_v4si_1s (vector int a)
{
- return vec_parity_lsbb (a);
+ return vec_vprtyb (a);
}
vector int
parity_v4si_2s (vector int a)
{
- return vec_parity_lsbb (a);
+ return vec_vprtybw (a);
}
vector unsigned int
parity_v4si_1u (vector unsigned int a)
{
- return vec_parity_lsbb (a);
+ return vec_vprtyb (a);
}
vector unsigned int
parity_v4si_2u (vector unsigned int a)
{
- return vec_parity_lsbb (a);
+ return vec_vprtybw (a);
}
vector long long
parity_v2di_1s (vector long long a)
{
- return vec_parity_lsbb (a);
+ return vec_vprtyb (a);
}
vector long long
parity_v2di_2s (vector long long a)
{
- return vec_parity_lsbb (a);
+ return vec_vprtybd (a);
}
vector unsigned long long
parity_v2di_1u (vector unsigned long long a)
{
- return vec_parity_lsbb (a);
+ return vec_vprtyb (a);
}
vector unsigned long long
parity_v2di_2u (vector unsigned long long a)
{
- return vec_parity_lsbb (a);
+ return vec_vprtybd (a);
}
vector __int128_t
parity_v1ti_1s (vector __int128_t a)
{
- return vec_parity_lsbb (a);
+ return vec_vprtyb (a);
}
vector __int128_t
parity_v1ti_2s (vector __int128_t a)
{
- return vec_parity_lsbb (a);
+ return vec_vprtybq (a);
}
__int128_t
parity_ti_3s (__int128_t a)
{
- return vec_parity_lsbb (a);
+ return vec_vprtyb (a);
}
__int128_t
parity_ti_4s (__int128_t a)
{
- return vec_parity_lsbb (a);
+ return vec_vprtybq (a);
}
vector __uint128_t
parity_v1ti_1u (vector __uint128_t a)
{
- return vec_parity_lsbb (a);
+ return vec_vprtyb (a);
}
vector __uint128_t
parity_v1ti_2u (vector __uint128_t a)
{
- return vec_parity_lsbb (a);
+ return vec_vprtybq (a);
}
__uint128_t
parity_ti_3u (__uint128_t a)
{
- return vec_parity_lsbb (a);
+ return vec_vprtyb (a);
}
__uint128_t
parity_ti_4u (__uint128_t a)
{
- return vec_parity_lsbb (a);
+ return vec_vprtybq (a);
}
/* { dg-final { scan-assembler "vprtybd" } } */
^ permalink raw reply [flat|nested] 29+ messages in thread
* [gcc(refs/users/wschmidt/heads/builtins4)] rs6000: More bug fixes
@ 2021-01-27 23:01 William Schmidt
0 siblings, 0 replies; 29+ messages in thread
From: William Schmidt @ 2021-01-27 23:01 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:013fb6e9e7d3c14e2e91523f1c7e07a5f392f6ad
commit 013fb6e9e7d3c14e2e91523f1c7e07a5f392f6ad
Author: Bill Schmidt <wschmidt@linux.ibm.com>
Date: Wed Jan 27 17:00:50 2021 -0600
rs6000: More bug fixes
2021-01-27 Bill Schmidt <wschmidt@linux.ibm.com>
gcc/
* config/rs6000/altivec.h (__builtin_vec_vaduh): Fix.
(__builtin_vec_vaduw): Fix.
* config/rs6000/rs6000-builtin-new.def: Miscellaneous fixes.
* config/rs6000/rs6000-overload.def: Miscellaneous fixes.
gcc/testsuite/
* gcc.target/powerpc/vadsdub-2.c: Remove deprecated interface.
* gcc.target/powerpc/vadsduh-2.c: Likewise.
* gcc.target/powerpc/vadsduw-2.c: Likewise.
Diff:
---
gcc/config/rs6000/altivec.h | 4 +--
gcc/config/rs6000/rs6000-builtin-new.def | 14 +++++-----
gcc/config/rs6000/rs6000-overload.def | 38 ++++++++++++++--------------
gcc/testsuite/gcc.target/powerpc/vadsdub-2.c | 2 +-
gcc/testsuite/gcc.target/powerpc/vadsduh-2.c | 2 +-
gcc/testsuite/gcc.target/powerpc/vadsduw-2.c | 2 +-
6 files changed, 31 insertions(+), 31 deletions(-)
diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h
index 5a4c366e0f1..312e5657623 100644
--- a/gcc/config/rs6000/altivec.h
+++ b/gcc/config/rs6000/altivec.h
@@ -267,8 +267,8 @@ __altivec_scalar_pred(vec_any_nle,
/* Deprecated interfaces. */
#ifdef _ARCH_PWR9
#define __builtin_vec_vadub __builtin_vec_vadu
-#define __builtin_vec_vaduh __builtin_vec_vaduh
-#define __builtin_vec_vaduw __builtin_vec_vaduw
+#define __builtin_vec_vaduh __builtin_vec_vadu
+#define __builtin_vec_vaduw __builtin_vec_vadu
#endif
#endif /* _ALTIVEC_H */
diff --git a/gcc/config/rs6000/rs6000-builtin-new.def b/gcc/config/rs6000/rs6000-builtin-new.def
index 061470d8198..417fd2a35dd 100644
--- a/gcc/config/rs6000/rs6000-builtin-new.def
+++ b/gcc/config/rs6000/rs6000-builtin-new.def
@@ -203,7 +203,7 @@
const __ibm128 __builtin_pack_ibm128 (double, double);
PACK_IF packif {}
- void __builtin_set_fpscr_rn (const int[0,7]);
+ void __builtin_set_fpscr_rn (const int[0,3]);
SET_FPSCR_RN rs6000_set_fpscr_rn {}
const double __builtin_unpack_ibm128 (__ibm128, const int<1>);
@@ -3186,22 +3186,22 @@
const unsigned long long __builtin_altivec_vgnb (vuq, const int <2,7>);
VGNB vgnb {}
- const vuc __builtin_altivec_vinsgubvlx (unsigned char, vuc, unsigned int);
+ const vuc __builtin_altivec_vinsgubvlx (unsigned int, vuc, unsigned int);
VINSERTGPRBL vinsertgl_v16qi {}
- const vuc __builtin_altivec_vinsgubvrx (unsigned char, vuc, unsigned int);
+ const vuc __builtin_altivec_vinsgubvrx (unsigned int, vuc, unsigned int);
VINSERTGPRBR vinsertgr_v16qi {}
- const vull __builtin_altivec_vinsgudvlx (unsigned long long, vull, unsigned int);
+ const vull __builtin_altivec_vinsgudvlx (unsigned int, vull, unsigned int);
VINSERTGPRDL vinsertgl_v2di {}
- const vull __builtin_altivec_vinsgudvrx (unsigned long long, vull, unsigned int);
+ const vull __builtin_altivec_vinsgudvrx (unsigned int, vull, unsigned int);
VINSERTGPRDR vinsertgr_v2di {}
- const vus __builtin_altivec_vinsguhvlx (unsigned short, vus, unsigned int);
+ const vus __builtin_altivec_vinsguhvlx (unsigned int, vus, unsigned int);
VINSERTGPRHL vinsertgl_v8hi {}
- const vus __builtin_altivec_vinsguhvrx (unsigned short, vus, unsigned int);
+ const vus __builtin_altivec_vinsguhvrx (unsigned int, vus, unsigned int);
VINSERTGPRHR vinsertgr_v8hi {}
const vui __builtin_altivec_vinsguwvlx (unsigned int, vui, unsigned int);
diff --git a/gcc/config/rs6000/rs6000-overload.def b/gcc/config/rs6000/rs6000-overload.def
index f9bf995de28..344c78b6a83 100644
--- a/gcc/config/rs6000/rs6000-overload.def
+++ b/gcc/config/rs6000/rs6000-overload.def
@@ -555,7 +555,7 @@
vuc __builtin_vec_clrl (vuc, unsigned int);
VCLRLB VCLRLB_U
-[VEC_CLRR, vec_clrr, __builtin_vec_clrr, ARCH_PWR10]
+[VEC_CLRR, vec_clrr, __builtin_vec_clrr, _ARCH_PWR10]
vsc __builtin_vec_clrr (vsc, unsigned int);
VCLRRB VCLRRB_S
vuc __builtin_vec_clrr (vuc, unsigned int);
@@ -1054,7 +1054,7 @@
[VEC_CNTTZM, vec_cnttzm, __builtin_vec_vctzdm, _ARCH_PWR10]
vull __builtin_vec_vctzdm (vull, vull);
- CNTTZDM
+ VCTZDM
[VEC_CNTLZ_LSBB, vec_cntlz_lsbb, __builtin_vec_vclzlsbb, _ARCH_PWR9]
signed int __builtin_vec_vclzlsbb (vsc);
@@ -1680,7 +1680,7 @@
XXGENPCVM_V2DI
[VEC_GNB, vec_gnb, __builtin_vec_gnb, _ARCH_PWR10]
- vull __builtin_vec_gnb (vuq, unsigned char);
+ unsigned long long __builtin_vec_gnb (vuq, const int);
VGNB
; There are no actual builtins for vec_insert. There is special handling for
@@ -2856,25 +2856,25 @@
[VEC_PERMX, vec_permx, __builtin_vec_xxpermx, _ARCH_PWR10]
vsc __builtin_vec_xxpermx (vsc, vsc, vuc, const int);
- XXPERMX_V16QI
+ XXPERMX_UV2DI XXPERMX_VSC
vuc __builtin_vec_xxpermx (vuc, vuc, vuc, const int);
- XXPERMX_UV16QI
+ XXPERMX_UV2DI XXPERMX_VUC
vss __builtin_vec_xxpermx (vss, vss, vuc, const int);
- XXPERMX_V8HI
+ XXPERMX_UV2DI XXPERMX_VSS
vus __builtin_vec_xxpermx (vus, vus, vuc, const int);
- XXPERMX_UV8HI
+ XXPERMX_UV2DI XXPERMX_VUS
vsi __builtin_vec_xxpermx (vsi, vsi, vuc, const int);
- XXPERMX_V4SI
+ XXPERMX_UV2DI XXPERMX_VSI
vui __builtin_vec_xxpermx (vui, vui, vuc, const int);
- XXPERMX_UV4SI
+ XXPERMX_UV2DI XXPERMX_VUI
vsll __builtin_vec_xxpermx (vsll, vsll, vuc, const int);
- XXPERMX_V2DI
+ XXPERMX_UV2DI XXPERMX_VSLL
vull __builtin_vec_xxpermx (vull, vull, vuc, const int);
- XXPERMX_UV2DI
+ XXPERMX_UV2DI XXPERMX_VULL
vf __builtin_vec_xxpermx (vf, vf, vuc, const int);
- XXPERMX_V4SF
+ XXPERMX_UV2DI XXPERMX_VF
vd __builtin_vec_xxpermx (vd, vd, vuc, const int);
- XXPERMX_V2DF
+ XXPERMX_UV2DI XXPERMX_VD
[VEC_PERMXOR, vec_permxor, __builtin_vec_vpermxor]
vsc __builtin_vec_vpermxor (vsc, vsc, vsc);
@@ -2917,17 +2917,17 @@
VPOPCNTUD
[VEC_PARITY_LSBB, vec_parity_lsbb, __builtin_vec_vparity_lsbb, _ARCH_PWR9]
- vsi __builtin_vec_vparity_lsbb (vsi);
+ vui __builtin_vec_vparity_lsbb (vsi);
VPRTYBW VPRTYBW_S
- vsi __builtin_vec_vparity_lsbb (vui);
+ vui __builtin_vec_vparity_lsbb (vui);
VPRTYBW VPRTYBW_U
- vsll __builtin_vec_vparity_lsbb (vsll);
+ vull __builtin_vec_vparity_lsbb (vsll);
VPRTYBD VPRTYBD_S
- vsll __builtin_vec_vparity_lsbb (vull);
+ vull __builtin_vec_vparity_lsbb (vull);
VPRTYBD VPRTYBD_U
- vsq __builtin_vec_vparity_lsbb (vsq);
+ vuq __builtin_vec_vparity_lsbb (vsq);
VPRTYBQ VPRTYBQ_S
- vsq __builtin_vec_vparity_lsbb (vuq);
+ vuq __builtin_vec_vparity_lsbb (vuq);
VPRTYBQ VPRTYBQ_U
; There are no actual builtins for vec_promote. There is special handling for
diff --git a/gcc/testsuite/gcc.target/powerpc/vadsdub-2.c b/gcc/testsuite/gcc.target/powerpc/vadsdub-2.c
index c3d1bc84ade..53e2d895d46 100644
--- a/gcc/testsuite/gcc.target/powerpc/vadsdub-2.c
+++ b/gcc/testsuite/gcc.target/powerpc/vadsdub-2.c
@@ -15,7 +15,7 @@ doAbsoluteDifferenceUnsigned (__vector unsigned char *p,
source_1 = *p;
source_2 = *q;
- uc_result = vec_absdb (source_1, source_2);
+ uc_result = vec_absd (source_1, source_2);
return uc_result;
}
diff --git a/gcc/testsuite/gcc.target/powerpc/vadsduh-2.c b/gcc/testsuite/gcc.target/powerpc/vadsduh-2.c
index 7f17694cc09..6e28e62c043 100644
--- a/gcc/testsuite/gcc.target/powerpc/vadsduh-2.c
+++ b/gcc/testsuite/gcc.target/powerpc/vadsduh-2.c
@@ -14,7 +14,7 @@ doAbsoluteDifferenceUnsignedMacro (__vector unsigned short *p,
source_1 = *p;
source_2 = *q;
- result = vec_absdh (source_1, source_2);
+ result = vec_absd (source_1, source_2);
return result;
}
diff --git a/gcc/testsuite/gcc.target/powerpc/vadsduw-2.c b/gcc/testsuite/gcc.target/powerpc/vadsduw-2.c
index a330f526c51..0a22ccd9067 100644
--- a/gcc/testsuite/gcc.target/powerpc/vadsduw-2.c
+++ b/gcc/testsuite/gcc.target/powerpc/vadsduw-2.c
@@ -14,7 +14,7 @@ doAbsoluteDifferenceUnsignedMacro (__vector unsigned int *p,
source_1 = *p;
source_2 = *q;
- result = vec_absdw (source_1, source_2);
+ result = vec_absd (source_1, source_2);
return result;
}
^ permalink raw reply [flat|nested] 29+ messages in thread
* [gcc(refs/users/wschmidt/heads/builtins4)] rs6000: More bug fixes
@ 2021-01-27 16:07 William Schmidt
0 siblings, 0 replies; 29+ messages in thread
From: William Schmidt @ 2021-01-27 16:07 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:5865fad98276e06e5ac02354240e065befbf1242
commit 5865fad98276e06e5ac02354240e065befbf1242
Author: Bill Schmidt <wschmidt@linux.ibm.com>
Date: Wed Jan 27 10:06:53 2021 -0600
rs6000: More bug fixes
2021-01-27 Bill Schmidt <wschmidt@linux.ibm.com>
gcc/
* config/rs6000/altivec.h: Add some deprecated interfaces.
* config/rs6000/rs6000-builtin-new.def: Miscellaneous fixes.
* config/rs6000/rs6000-c.c
(altivec_resolve_new_overloaded_builtin): Add missing break
statements.
* config/rs6000/rs6000-overload.def: Miscellaneous fixes.
* config/rs6000/rs6000.c
(rs6000_new_builtin_md_vectorized_function): Use
rs6000_gen_builtins.
gcc/testsuite/
* gcc.target/powerpc/p8vector-builtin-2.c: Adjust.
* gcc.target/powerpc/p8vector-builtin-3.c: Adjust.
* gcc.target/powerpc/p8vector-builtin-4.c: Adjust.
* gcc.target/powerpc/p8vector-builtin-8.c: Remove deprecated
builtins.
* gcc.target/powerpc/p8vector-int128-2.c: Likewise.
* gcc.target/powerpc/p8vector-vbpermq.c: Likewise.
* gcc.target/powerpc/p9-vparity.c: Likewise.
* gcc.target/powerpc/pr79544.c: Likewise.
* gcc.target/powerpc/pr80315-1.c: Adjust.
* gcc.target/powerpc/pr80315-2.c: Adjust.
* gcc.target/powerpc/pr80315-3.c: Adjust.
* gcc.target/powerpc/pr80315-4.c: Adjust.
* gcc.target/powerpc/pr88100.c: Adjust.
* gcc.target/powerpc/pragma_misc9.c: Adjust.
* gcc.target/powerpc/pragma_power9.c: Undefine
_RS6000_VECDEFINES_H before including altivec.h.
* gcc.target/powerpc/swaps-p8-46.c: Remove deprecated builtins.
* gcc.target/powerpc/test_fpscr_drn_builtin_error.c: Adjust.
* gcc.target/powerpc/test_fpscr_rn_builtin_error.c: Adjust.
Diff:
---
gcc/config/rs6000/altivec.h | 7 ++++
gcc/config/rs6000/rs6000-builtin-new.def | 10 +++---
gcc/config/rs6000/rs6000-c.c | 9 +++--
gcc/config/rs6000/rs6000-overload.def | 39 +++++++++++-----------
gcc/config/rs6000/rs6000.c | 12 +++----
.../gcc.target/powerpc/p8vector-builtin-2.c | 16 ++++-----
.../gcc.target/powerpc/p8vector-builtin-3.c | 8 ++---
.../gcc.target/powerpc/p8vector-builtin-4.c | 18 +++++-----
.../gcc.target/powerpc/p8vector-builtin-8.c | 4 +--
.../gcc.target/powerpc/p8vector-int128-1.c | 16 ++++-----
.../gcc.target/powerpc/p8vector-int128-2.c | 4 +--
.../gcc.target/powerpc/p8vector-vbpermq.c | 4 +--
gcc/testsuite/gcc.target/powerpc/p9-vparity.c | 32 +++++++++---------
gcc/testsuite/gcc.target/powerpc/pr79544.c | 8 +----
gcc/testsuite/gcc.target/powerpc/pr80315-1.c | 2 +-
gcc/testsuite/gcc.target/powerpc/pr80315-2.c | 2 +-
gcc/testsuite/gcc.target/powerpc/pr80315-3.c | 2 +-
gcc/testsuite/gcc.target/powerpc/pr80315-4.c | 2 +-
gcc/testsuite/gcc.target/powerpc/pr88100.c | 12 +++----
gcc/testsuite/gcc.target/powerpc/pragma_misc9.c | 2 +-
gcc/testsuite/gcc.target/powerpc/pragma_power9.c | 1 +
gcc/testsuite/gcc.target/powerpc/swaps-p8-46.c | 5 +--
.../powerpc/test_fpscr_drn_builtin_error.c | 4 +--
.../powerpc/test_fpscr_rn_builtin_error.c | 12 +++----
24 files changed, 117 insertions(+), 114 deletions(-)
diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h
index 8904d2c545d..5a4c366e0f1 100644
--- a/gcc/config/rs6000/altivec.h
+++ b/gcc/config/rs6000/altivec.h
@@ -264,4 +264,11 @@ __altivec_scalar_pred(vec_any_nle,
to #define vec_step to __builtin_vec_step. */
#define vec_step(x) __builtin_vec_step (* (__typeof__ (x) *) 0)
+/* Deprecated interfaces. */
+#ifdef _ARCH_PWR9
+#define __builtin_vec_vadub __builtin_vec_vadu
+#define __builtin_vec_vaduh __builtin_vec_vaduh
+#define __builtin_vec_vaduw __builtin_vec_vaduw
+#endif
+
#endif /* _ALTIVEC_H */
diff --git a/gcc/config/rs6000/rs6000-builtin-new.def b/gcc/config/rs6000/rs6000-builtin-new.def
index 449dcd5e257..061470d8198 100644
--- a/gcc/config/rs6000/rs6000-builtin-new.def
+++ b/gcc/config/rs6000/rs6000-builtin-new.def
@@ -203,7 +203,7 @@
const __ibm128 __builtin_pack_ibm128 (double, double);
PACK_IF packif {}
- void __builtin_set_fpscr_rn (signed long long);
+ void __builtin_set_fpscr_rn (const int[0,7]);
SET_FPSCR_RN rs6000_set_fpscr_rn {}
const double __builtin_unpack_ibm128 (__ibm128, const int<1>);
@@ -1698,7 +1698,7 @@
const vull __builtin_vsx_xvcvdpuxds (vd);
XVCVDPUXDS vsx_fixuns_truncv2dfv2di2 {}
- const vull __builtin_vsx_xvcvdpuxds_scale (vd, const int);
+ const vsll __builtin_vsx_xvcvdpuxds_scale (vd, const int);
XVCVDPUXDS_SCALE vsx_xvcvdpuxds_scale {}
; Redundant with __builtin_vsx_xvcvdpuxds
@@ -2946,7 +2946,7 @@
const _Decimal128 __builtin_pack_dec128 (unsigned long long, unsigned long long);
PACK_TD packtd {}
- void __builtin_set_fpscr_drn (signed long long);
+ void __builtin_set_fpscr_drn (const int[0,7]);
SET_FPSCR_DRN rs6000_set_fpscr_drn {}
const unsigned long long __builtin_unpack_dec128 (_Decimal128, const int<1>);
@@ -3348,13 +3348,13 @@
const vuc __builtin_vsx_xxblend_v16qi (vuc, vuc, vuc);
VXXBLEND_V16QI xxblend_v16qi {}
- const vd __builtin_vsx_xxblend_v2df (vd, vd, vull);
+ const vd __builtin_vsx_xxblend_v2df (vd, vd, vd);
VXXBLEND_V2DF xxblend_v2df {}
const vull __builtin_vsx_xxblend_v2di (vull, vull, vull);
VXXBLEND_V2DI xxblend_v2di {}
- const vf __builtin_vsx_xxblend_v4sf (vf, vf, vui);
+ const vf __builtin_vsx_xxblend_v4sf (vf, vf, vf);
VXXBLEND_V4SF xxblend_v4sf {}
const vui __builtin_vsx_xxblend_v4si (vui, vui, vui);
diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c
index 11099d21006..64924df97f9 100644
--- a/gcc/config/rs6000/rs6000-c.c
+++ b/gcc/config/rs6000/rs6000-c.c
@@ -2245,10 +2245,9 @@ altivec_resolve_new_overloaded_builtin (location_t loc, tree fndecl,
params);
}
/* For {un}signed __int128s use the vaddeuqm/vsubeuqm instruction
- directly. This is done by the normal processing. */
+ directly. */
case E_TImode:
- {
- }
+ break;
/* Types other than {un}signed int and {un}signed __int128
are errors. */
@@ -2345,8 +2344,8 @@ altivec_resolve_new_overloaded_builtin (location_t loc, tree fndecl,
/* For {un}signed __int128s use the vaddecuq/vsubbecuq
instructions. This occurs through normal processing. */
case E_TImode:
- {
- }
+ break;
+
/* Types other than {un}signed int and {un}signed __int128
are errors. */
default:
diff --git a/gcc/config/rs6000/rs6000-overload.def b/gcc/config/rs6000/rs6000-overload.def
index f6e43b88e07..f9bf995de28 100644
--- a/gcc/config/rs6000/rs6000-overload.def
+++ b/gcc/config/rs6000/rs6000-overload.def
@@ -433,7 +433,7 @@
vui __builtin_vec_andc (vui, vui);
VANDC_V4SI_UNS VANDC_VUI
vbll __builtin_vec_andc (vbll, vbll);
- VANDC_V4SI_UNS VANDC_VBLL
+ VANDC_V2DI_UNS VANDC_VBLL
vsll __builtin_vec_andc (vsll, vsll);
VANDC_V2DI
vull __builtin_vec_andc (vull, vull);
@@ -526,7 +526,9 @@
vull __builtin_vec_vbperm_api (vuq, vuc);
VBPERMD VBPERMD_VUQ
vuc __builtin_vec_vbperm_api (vuc, vuc);
- VBPERMQ2
+ VBPERMQ2 VBPERMQ2_U
+ vsc __builtin_vec_vbperm_api (vsc, vsc);
+ VBPERMQ2 VBPERMQ2_S
; #### XVRSPIP{TARGET_VSX};VRFIP
[VEC_CEIL, vec_ceil, __builtin_vec_ceil]
@@ -2915,17 +2917,17 @@
VPOPCNTUD
[VEC_PARITY_LSBB, vec_parity_lsbb, __builtin_vec_vparity_lsbb, _ARCH_PWR9]
- vui __builtin_vec_vparity_lsbb (vsi);
+ vsi __builtin_vec_vparity_lsbb (vsi);
VPRTYBW VPRTYBW_S
- vui __builtin_vec_vparity_lsbb (vui);
+ vsi __builtin_vec_vparity_lsbb (vui);
VPRTYBW VPRTYBW_U
- vull __builtin_vec_vparity_lsbb (vsll);
+ vsll __builtin_vec_vparity_lsbb (vsll);
VPRTYBD VPRTYBD_S
- vull __builtin_vec_vparity_lsbb (vull);
+ vsll __builtin_vec_vparity_lsbb (vull);
VPRTYBD VPRTYBD_U
- vuq __builtin_vec_vparity_lsbb (vsq);
+ vsq __builtin_vec_vparity_lsbb (vsq);
VPRTYBQ VPRTYBQ_S
- vuq __builtin_vec_vparity_lsbb (vuq);
+ vsq __builtin_vec_vparity_lsbb (vuq);
VPRTYBQ VPRTYBQ_U
; There are no actual builtins for vec_promote. There is special handling for
@@ -3276,17 +3278,17 @@
vuc __builtin_vec_sldw (vuc, vuc, const int);
XXSLDWI_16QI XXSLDWI_VUC
vss __builtin_vec_sldw (vss, vss, const int);
- XXSLDWI_16QI XXSLDWI_VSS
+ XXSLDWI_8HI XXSLDWI_VSS
vus __builtin_vec_sldw (vus, vus, const int);
- XXSLDWI_16QI XXSLDWI_VUS
+ XXSLDWI_8HI XXSLDWI_VUS
vsi __builtin_vec_sldw (vsi, vsi, const int);
- XXSLDWI_16QI XXSLDWI_VSI
+ XXSLDWI_4SI XXSLDWI_VSI
vui __builtin_vec_sldw (vui, vui, const int);
- XXSLDWI_16QI XXSLDWI_VUI
+ XXSLDWI_4SI XXSLDWI_VUI
vsll __builtin_vec_sldw (vsll, vsll, const int);
- XXSLDWI_16QI XXSLDWI_VSLL
+ XXSLDWI_2DI XXSLDWI_VSLL
vull __builtin_vec_sldw (vull, vull, const int);
- XXSLDWI_16QI XXSLDWI_VULL
+ XXSLDWI_2DI XXSLDWI_VULL
[VEC_SLL, vec_sll, __builtin_vec_sll]
vsc __builtin_vec_sll (vsc, vuc);
@@ -4119,11 +4121,8 @@
VSUBCUQ VSUBCUQ_VUQ
; TODO: Note that the entry for VEC_SUBE currently gets ignored in
-; altivec_resolve_overloaded_builtin. There are also forms for
-; vsi and vui arguments, but rather than building a define_expand
-; for the instruction sequence generated for those, we do some RTL
-; hackery. Revisit whether we can remove that. For now, keep this
-; much of the entry here to generate the #define, at least.
+; altivec_resolve_overloaded_builtin. Revisit whether we can remove
+; that. We still need to register the legal builtin forms here.
[VEC_SUBE, vec_sube, __builtin_vec_sube]
vsq __builtin_vec_sube (vsq, vsq, vsq);
VSUBEUQM VSUBEUQM_VSQ
@@ -4406,6 +4405,8 @@
LXVW4X_V8HI LXVW4X_VUS
vus __builtin_vec_vsx_ld (signed long long, const unsigned short *);
LXVW4X_V8HI LXVW4X_US
+ vp __builtin_vec_vsx_ld (signed long long, const vp *);
+ LXVW4X_V8HI LXVW4X_P
vsi __builtin_vec_vsx_ld (signed long long, const vsi *);
LXVW4X_V4SI LXVW4X_VSI
vsi __builtin_vec_vsx_ld (signed long long, const signed int *);
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 8b7b7820f42..e48cf0ca702 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -5570,29 +5570,29 @@ rs6000_new_builtin_md_vectorized_function (tree fndecl, tree type_out,
in_mode = TYPE_MODE (TREE_TYPE (type_in));
in_n = TYPE_VECTOR_SUBPARTS (type_in);
- enum rs6000_builtins fn
- = (enum rs6000_builtins) DECL_MD_FUNCTION_CODE (fndecl);
+ enum rs6000_gen_builtins fn
+ = (enum rs6000_gen_builtins) DECL_MD_FUNCTION_CODE (fndecl);
switch (fn)
{
- case RS6000_BUILTIN_RSQRTF:
+ case RS6000_BIF_RSQRTF:
if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
&& out_mode == SFmode && out_n == 4
&& in_mode == SFmode && in_n == 4)
return rs6000_builtin_decls_x[RS6000_BIF_VRSQRTFP];
break;
- case RS6000_BUILTIN_RSQRT:
+ case RS6000_BIF_RSQRT:
if (VECTOR_UNIT_VSX_P (V2DFmode)
&& out_mode == DFmode && out_n == 2
&& in_mode == DFmode && in_n == 2)
return rs6000_builtin_decls_x[RS6000_BIF_RSQRT_2DF];
break;
- case RS6000_BUILTIN_RECIPF:
+ case RS6000_BIF_RECIPF:
if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
&& out_mode == SFmode && out_n == 4
&& in_mode == SFmode && in_n == 4)
return rs6000_builtin_decls_x[RS6000_BIF_VRECIPFP];
break;
- case RS6000_BUILTIN_RECIP:
+ case RS6000_BIF_RECIP:
if (VECTOR_UNIT_VSX_P (V2DFmode)
&& out_mode == DFmode && out_n == 2
&& in_mode == DFmode && in_n == 2)
diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c
index 0259e364aa6..a1f4e4e9a4e 100644
--- a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c
+++ b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c
@@ -214,17 +214,17 @@ v_bshort vbshort_ne (v_bshort a, v_bshort b)
}
-/* { dg-final { scan-assembler-times "vaddudm" 5 } } */
-/* { dg-final { scan-assembler-times "vsubudm" 6 } } */
-/* { dg-final { scan-assembler-times "vmaxsd" 4 } } */
-/* { dg-final { scan-assembler-times "vminsd" 3 } } */
-/* { dg-final { scan-assembler-times "vmaxud" 2 } } */
-/* { dg-final { scan-assembler-times "vminud" 2 } } */
+/* { dg-final { scan-assembler-times "vaddudm" 3 } } */
+/* { dg-final { scan-assembler-times "vsubudm" 4 } } */
+/* { dg-final { scan-assembler-times "vmaxsd" 3 } } */
+/* { dg-final { scan-assembler-times "vminsd" 2 } } */
+/* { dg-final { scan-assembler-times "vmaxud" 1 } } */
+/* { dg-final { scan-assembler-times "vminud" 1 } } */
/* { dg-final { scan-assembler-times "vcmpequd" 6 } } */
/* { dg-final { scan-assembler-times "vcmpgtsd" 1 } } */
/* { dg-final { scan-assembler-times "vcmpgtud" 1 } } */
/* { dg-final { scan-assembler-times "vrld" 3 } } */
-/* { dg-final { scan-assembler-times "vsld" 5 } } */
-/* { dg-final { scan-assembler-times "vsrad" 3 } } */
+/* { dg-final { scan-assembler-times "vsld" 3 } } */
+/* { dg-final { scan-assembler-times "vsrad" 2 } } */
/* { dg-final { scan-assembler-times "vcmpequb" 3 } } */
/* { dg-final { scan-assembler-times "vcmpequw" 6 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-3.c b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-3.c
index ae6a3a8437b..0b038edfafe 100644
--- a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-3.c
@@ -77,8 +77,8 @@ vll_sign vll_unpack_lo_2 (vi_sign a)
return vec_unpackl (a);
}
-/* { dg-final { scan-assembler-times "vpkudum" 4 } } */
-/* { dg-final { scan-assembler-times "vpkuwum" 3 } } */
-/* { dg-final { scan-assembler-times "vpkuhum" 3 } } */
+/* { dg-final { scan-assembler-times "vpkudum" 3 } } */
+/* { dg-final { scan-assembler-times "vpkuwum" 2 } } */
+/* { dg-final { scan-assembler-times "vpkuhum" 2 } } */
/* { dg-final { scan-assembler-times "vupklsw" 3 } } */
-/* { dg-final { scan-assembler-times "vupkhsw" 3 } } */
+/* { dg-final { scan-assembler-times "vupkhsw" 1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-4.c b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-4.c
index 2d2d141948f..e814c648843 100644
--- a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-4.c
+++ b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-4.c
@@ -156,14 +156,14 @@ vc_uns vc_gbb_3 (vc_uns a)
return vec_gb (a);
}
-/* { dg-final { scan-assembler-times "vclzd" 5 } } */
-/* { dg-final { scan-assembler-times "vclzw" 5 } } */
-/* { dg-final { scan-assembler-times "vclzh" 5 } } */
-/* { dg-final { scan-assembler-times "vclzb" 5 } } */
-
-/* { dg-final { scan-assembler-times "vpopcntd" 5 } } */
-/* { dg-final { scan-assembler-times "vpopcntw" 5 } } */
-/* { dg-final { scan-assembler-times "vpopcnth" 5 } } */
-/* { dg-final { scan-assembler-times "vpopcntb" 5 } } */
+/* { dg-final { scan-assembler-times "vclzd" 3 } } */
+/* { dg-final { scan-assembler-times "vclzw" 3 } } */
+/* { dg-final { scan-assembler-times "vclzh" 3 } } */
+/* { dg-final { scan-assembler-times "vclzb" 3 } } */
+
+/* { dg-final { scan-assembler-times "vpopcntd" 3 } } */
+/* { dg-final { scan-assembler-times "vpopcntw" 3 } } */
+/* { dg-final { scan-assembler-times "vpopcnth" 3 } } */
+/* { dg-final { scan-assembler-times "vpopcntb" 3 } } */
/* { dg-final { scan-assembler-times "vgbbd" 3 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-8.c b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-8.c
index 0cfbe68c3a4..b5c81ab1ace 100644
--- a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-8.c
+++ b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-8.c
@@ -112,7 +112,6 @@ void foo (vector signed char *vscr,
*vsir++ = vec_sum4s (vsca, vsib);
*vsir++ = vec_sum4s (vssa, vsib);
*vuir++ = vec_sum4s (vuca, vuib);
-
}
/* { dg-final { scan-assembler-times "vaddcuq" 2 } } */
@@ -125,7 +124,8 @@ void foo (vector signed char *vscr,
/* { dg-final { scan-assembler-times "vsubecuq" 2 } } */
/* { dg-final { scan-assembler-times "vsubcuw" 4 } } */
/* { dg-final { scan-assembler-times "vsubuwm" 4 } } */
-/* { dg-final { scan-assembler-times "vbpermq" 2 } } */
+/* { dg-final { scan-assembler-times "vbpermq" 1 } } */
+/* { dg-final { scan-assembler-times "vbpermd" 1 } } */
/* { dg-final { scan-assembler-times "xxleqv" 4 } } */
/* { dg-final { scan-assembler-times "vgbbd" 1 } } */
/* { dg-final { scan-assembler-times "xxlnand" 4 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-int128-1.c b/gcc/testsuite/gcc.target/powerpc/p8vector-int128-1.c
index 28b148c692c..8a7484b7144 100644
--- a/gcc/testsuite/gcc.target/powerpc/p8vector-int128-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/p8vector-int128-1.c
@@ -13,49 +13,49 @@
TYPE
do_addcuq (TYPE p, TYPE q)
{
- return __builtin_vec_vaddcuq (p, q);
+ return vec_addc (p, q);
}
TYPE
do_adduqm (TYPE p, TYPE q)
{
- return __builtin_vec_add (p, q);
+ return vec_add (p, q);
}
TYPE
do_addeuqm (TYPE p, TYPE q, TYPE r)
{
- return __builtin_vec_vaddeuqm (p, q, r);
+ return vec_adde (p, q, r);
}
TYPE
do_addecuq (TYPE p, TYPE q, TYPE r)
{
- return __builtin_vec_vaddecuq (p, q, r);
+ return vec_addec (p, q, r);
}
TYPE
do_subeuqm (TYPE p, TYPE q, TYPE r)
{
- return __builtin_vec_vsubeuqm (p, q, r);
+ return vec_sube (p, q, r);
}
TYPE
do_subecuq (TYPE p, TYPE q, TYPE r)
{
- return __builtin_vec_vsubecuq (p, q, r);
+ return vec_subec (p, q, r);
}
TYPE
do_subcuq (TYPE p, TYPE q)
{
- return __builtin_vec_vsubcuq (p, q);
+ return vec_subc (p, q);
}
TYPE
do_subuqm (TYPE p, TYPE q)
{
- return __builtin_vec_vsubuqm (p, q);
+ return vec_sub (p, q);
}
TYPE
diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-int128-2.c b/gcc/testsuite/gcc.target/powerpc/p8vector-int128-2.c
index 72358d616b1..cdeebb36342 100644
--- a/gcc/testsuite/gcc.target/powerpc/p8vector-int128-2.c
+++ b/gcc/testsuite/gcc.target/powerpc/p8vector-int128-2.c
@@ -132,7 +132,7 @@ main (void)
v_reg_in1 = (V_TYPE) { s_reg_in1 };
v_reg_in2 = (V_TYPE) { s_reg_in2 };
- v_reg_res = vec_vadduqm (v_reg_in1, v_reg_in2);
+ v_reg_res = vec_add (v_reg_in1, v_reg_in2);
reg_errors += compare (s_reg_res, v_reg_res, "", "reg, res");
s_mem_in1 = s_reg_in1;
@@ -144,7 +144,7 @@ main (void)
mem_errors += compare (s_mem_in2, (V_TYPE) { s_mem_in2 }, "", "mem, in2");
s_mem_res = s_mem_in1 + s_mem_in2;
- v_mem_res = vec_vadduqm (v_mem_in1, v_mem_in2);
+ v_mem_res = vec_add (v_mem_in1, v_mem_in2);
mem_errors += compare (s_mem_res, v_mem_res, "", "mem, res");
nl = "\n";
diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-vbpermq.c b/gcc/testsuite/gcc.target/powerpc/p8vector-vbpermq.c
index c2ab68ba761..e5601b13b3a 100644
--- a/gcc/testsuite/gcc.target/powerpc/p8vector-vbpermq.c
+++ b/gcc/testsuite/gcc.target/powerpc/p8vector-vbpermq.c
@@ -17,11 +17,11 @@
long foos (vector signed char a, vector signed char b)
{
- return vec_extract (vec_vbpermq (a, b), OFFSET);
+ return vec_extract (vec_bperm (a, b), OFFSET);
}
long foou (vector unsigned char a, vector unsigned char b)
{
- return vec_extract (vec_vbpermq (a, b), OFFSET);
+ return vec_extract (vec_bperm (a, b), OFFSET);
}
diff --git a/gcc/testsuite/gcc.target/powerpc/p9-vparity.c b/gcc/testsuite/gcc.target/powerpc/p9-vparity.c
index f4aba1567cd..8897a5b6b7f 100644
--- a/gcc/testsuite/gcc.target/powerpc/p9-vparity.c
+++ b/gcc/testsuite/gcc.target/powerpc/p9-vparity.c
@@ -9,97 +9,97 @@
vector int
parity_v4si_1s (vector int a)
{
- return vec_vprtyb (a);
+ return vec_parity_lsbb (a);
}
vector int
parity_v4si_2s (vector int a)
{
- return vec_vprtybw (a);
+ return vec_parity_lsbb (a);
}
vector unsigned int
parity_v4si_1u (vector unsigned int a)
{
- return vec_vprtyb (a);
+ return vec_parity_lsbb (a);
}
vector unsigned int
parity_v4si_2u (vector unsigned int a)
{
- return vec_vprtybw (a);
+ return vec_parity_lsbb (a);
}
vector long long
parity_v2di_1s (vector long long a)
{
- return vec_vprtyb (a);
+ return vec_parity_lsbb (a);
}
vector long long
parity_v2di_2s (vector long long a)
{
- return vec_vprtybd (a);
+ return vec_parity_lsbb (a);
}
vector unsigned long long
parity_v2di_1u (vector unsigned long long a)
{
- return vec_vprtyb (a);
+ return vec_parity_lsbb (a);
}
vector unsigned long long
parity_v2di_2u (vector unsigned long long a)
{
- return vec_vprtybd (a);
+ return vec_parity_lsbb (a);
}
vector __int128_t
parity_v1ti_1s (vector __int128_t a)
{
- return vec_vprtyb (a);
+ return vec_parity_lsbb (a);
}
vector __int128_t
parity_v1ti_2s (vector __int128_t a)
{
- return vec_vprtybq (a);
+ return vec_parity_lsbb (a);
}
__int128_t
parity_ti_3s (__int128_t a)
{
- return vec_vprtyb (a);
+ return vec_parity_lsbb (a);
}
__int128_t
parity_ti_4s (__int128_t a)
{
- return vec_vprtybq (a);
+ return vec_parity_lsbb (a);
}
vector __uint128_t
parity_v1ti_1u (vector __uint128_t a)
{
- return vec_vprtyb (a);
+ return vec_parity_lsbb (a);
}
vector __uint128_t
parity_v1ti_2u (vector __uint128_t a)
{
- return vec_vprtybq (a);
+ return vec_parity_lsbb (a);
}
__uint128_t
parity_ti_3u (__uint128_t a)
{
- return vec_vprtyb (a);
+ return vec_parity_lsbb (a);
}
__uint128_t
parity_ti_4u (__uint128_t a)
{
- return vec_vprtybq (a);
+ return vec_parity_lsbb (a);
}
/* { dg-final { scan-assembler "vprtybd" } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/pr79544.c b/gcc/testsuite/gcc.target/powerpc/pr79544.c
index 3f782489bbd..ecdbbcc67bd 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr79544.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr79544.c
@@ -10,11 +10,5 @@ test_sra (vector unsigned long long x, vector unsigned long long y)
return vec_sra (x, y);
}
-vector unsigned long long
-test_vsrad (vector unsigned long long x, vector unsigned long long y)
-{
- return vec_vsrad (x, y);
-}
-
-/* { dg-final { scan-assembler-times {\mvsrad\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mvsrad\M} 1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/pr80315-1.c b/gcc/testsuite/gcc.target/powerpc/pr80315-1.c
index e2db0ff4b5f..f37f1f169a2 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr80315-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr80315-1.c
@@ -10,6 +10,6 @@ main()
int mask;
/* Argument 2 must be 0 or 1. Argument 3 must be in range 0..15. */
- res = __builtin_crypto_vshasigmaw (test, 1, 0xff); /* { dg-error {argument 3 must be in the range \[0, 15\]} } */
+ res = __builtin_crypto_vshasigmaw (test, 1, 0xff); /* { dg-error {argument 3 must be a 4-bit unsigned literal} } */
return 0;
}
diff --git a/gcc/testsuite/gcc.target/powerpc/pr80315-2.c b/gcc/testsuite/gcc.target/powerpc/pr80315-2.c
index 144b705c012..0819a0511b7 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr80315-2.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr80315-2.c
@@ -10,6 +10,6 @@ main ()
int mask;
/* Argument 2 must be 0 or 1. Argument 3 must be in range 0..15. */
- res = __builtin_crypto_vshasigmad (test, 1, 0xff); /* { dg-error {argument 3 must be in the range \[0, 15\]} } */
+ res = __builtin_crypto_vshasigmad (test, 1, 0xff); /* { dg-error {argument 3 must be a 4-bit unsigned literal} } */
return 0;
}
diff --git a/gcc/testsuite/gcc.target/powerpc/pr80315-3.c b/gcc/testsuite/gcc.target/powerpc/pr80315-3.c
index 99a3e24eadd..cc2e46cf5cb 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr80315-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr80315-3.c
@@ -12,6 +12,6 @@ main ()
int mask;
/* Argument 2 must be 0 or 1. Argument 3 must be in range 0..15. */
- res = vec_shasigma_be (test, 1, 0xff); /* { dg-error {argument 3 must be in the range \[0, 15\]} } */
+ res = vec_shasigma_be (test, 1, 0xff); /* { dg-error {argument 3 must be a 4-bit unsigned literal} } */
return res;
}
diff --git a/gcc/testsuite/gcc.target/powerpc/pr80315-4.c b/gcc/testsuite/gcc.target/powerpc/pr80315-4.c
index 7f5f6f75029..ac12910741b 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr80315-4.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr80315-4.c
@@ -12,6 +12,6 @@ main ()
int mask;
/* Argument 2 must be 0 or 1. Argument 3 must be in range 0..15. */
- res = vec_shasigma_be (test, 1, 0xff); /* { dg-error {argument 3 must be in the range \[0, 15\]} } */
+ res = vec_shasigma_be (test, 1, 0xff); /* { dg-error {argument 3 must be a 4-bit unsigned literal} } */
return res;
}
diff --git a/gcc/testsuite/gcc.target/powerpc/pr88100.c b/gcc/testsuite/gcc.target/powerpc/pr88100.c
index 4452145ce95..764c897a497 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr88100.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr88100.c
@@ -10,35 +10,35 @@
vector unsigned char
splatu1 (void)
{
- return vec_splat_u8(0x100);/* { dg-error "argument 1 must be a 5-bit signed literal" } */
+ return vec_splat_u8(0x100);/* { dg-error "argument 1 must be a literal between -16 and 15, inclusive" } */
}
vector unsigned short
splatu2 (void)
{
- return vec_splat_u16(0x10000);/* { dg-error "argument 1 must be a 5-bit signed literal" } */
+ return vec_splat_u16(0x10000);/* { dg-error "argument 1 must be a literal between -16 and 15, inclusive" } */
}
vector unsigned int
splatu3 (void)
{
- return vec_splat_u32(0x10000000);/* { dg-error "argument 1 must be a 5-bit signed literal" } */
+ return vec_splat_u32(0x10000000);/* { dg-error "argument 1 must be a literal between -16 and 15, inclusive" } */
}
vector signed char
splats1 (void)
{
- return vec_splat_s8(0x100);/* { dg-error "argument 1 must be a 5-bit signed literal" } */
+ return vec_splat_s8(0x100);/* { dg-error "argument 1 must be a literal between -16 and 15, inclusive" } */
}
vector signed short
splats2 (void)
{
- return vec_splat_s16(0x10000);/* { dg-error "argument 1 must be a 5-bit signed literal" } */
+ return vec_splat_s16(0x10000);/* { dg-error "argument 1 must be a literal between -16 and 15, inclusive" } */
}
vector signed int
splats3 (void)
{
- return vec_splat_s32(0x10000000);/* { dg-error "argument 1 must be a 5-bit signed literal" } */
+ return vec_splat_s32(0x10000000);/* { dg-error "argument 1 must be a literal between -16 and 15, inclusive" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/pragma_misc9.c b/gcc/testsuite/gcc.target/powerpc/pragma_misc9.c
index e03099bd084..61274463653 100644
--- a/gcc/testsuite/gcc.target/powerpc/pragma_misc9.c
+++ b/gcc/testsuite/gcc.target/powerpc/pragma_misc9.c
@@ -20,7 +20,7 @@ vector bool int
test2 (vector signed int a, vector signed int b)
{
return vec_cmpnez (a, b);
- /* { dg-error "'__builtin_altivec_vcmpnezw' requires the '-mcpu=power9' option" "" { target *-*-* } .-1 } */
+ /* { dg-error "'__builtin_altivec_vcmpnezw' requires the '-mpower9-vector' option" "" { target *-*-* } .-1 } */
}
#pragma GCC target ("cpu=power7")
diff --git a/gcc/testsuite/gcc.target/powerpc/pragma_power9.c b/gcc/testsuite/gcc.target/powerpc/pragma_power9.c
index e33aad1aaf7..5327c8c8cc8 100644
--- a/gcc/testsuite/gcc.target/powerpc/pragma_power9.c
+++ b/gcc/testsuite/gcc.target/powerpc/pragma_power9.c
@@ -50,6 +50,7 @@ test3b (vec_t a, vec_t b)
#pragma GCC target ("cpu=power9,power9-vector")
#undef _ALTIVEC_H
+#undef _RS6000_VECDEFINES_H
#include <altivec.h>
#ifdef _ARCH_PWR9
vector bool int
diff --git a/gcc/testsuite/gcc.target/powerpc/swaps-p8-46.c b/gcc/testsuite/gcc.target/powerpc/swaps-p8-46.c
index 4738d5e0139..3911ac9e713 100644
--- a/gcc/testsuite/gcc.target/powerpc/swaps-p8-46.c
+++ b/gcc/testsuite/gcc.target/powerpc/swaps-p8-46.c
@@ -2,6 +2,7 @@
/* { dg-require-effective-target powerpc_p8vector_ok } */
/* { dg-options "-mdejagnu-cpu=power8 -O2 " } */
+#include <altivec.h>
typedef __attribute__ ((__aligned__ (8))) unsigned long long __m64;
typedef float __m128 __attribute__ ((__vector_size__ (16), __may_alias__));
@@ -17,8 +18,8 @@ _mm_movemask_ps (__m128 *__A)
};
result = (__vector __m64)
- __builtin_vec_vbpermq ((__vector unsigned char) (*__A),
- (__vector unsigned char) perm_mask);
+ vec_bperm ((__vector unsigned char) (*__A),
+ (__vector unsigned char) perm_mask);
return result[1];
}
diff --git a/gcc/testsuite/gcc.target/powerpc/test_fpscr_drn_builtin_error.c b/gcc/testsuite/gcc.target/powerpc/test_fpscr_drn_builtin_error.c
index 028ab0b6d66..4f9d9e08e8a 100644
--- a/gcc/testsuite/gcc.target/powerpc/test_fpscr_drn_builtin_error.c
+++ b/gcc/testsuite/gcc.target/powerpc/test_fpscr_drn_builtin_error.c
@@ -9,8 +9,8 @@ int main ()
__builtin_set_fpscr_drn() also support a variable as an argument but
can't test variable value at compile time. */
- __builtin_set_fpscr_drn(-1); /* { dg-error "Argument must be a value between 0 and 7" } */
- __builtin_set_fpscr_drn(8); /* { dg-error "Argument must be a value between 0 and 7" } */
+ __builtin_set_fpscr_drn(-1); /* { dg-error "argument 1 must be a variable or a literal between 0 and 7, inclusive" } */
+ __builtin_set_fpscr_drn(8); /* { dg-error "argument 1 must be a variable or a literal between 0 and 7, inclusive" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/test_fpscr_rn_builtin_error.c b/gcc/testsuite/gcc.target/powerpc/test_fpscr_rn_builtin_error.c
index aea65091b0c..10391b71008 100644
--- a/gcc/testsuite/gcc.target/powerpc/test_fpscr_rn_builtin_error.c
+++ b/gcc/testsuite/gcc.target/powerpc/test_fpscr_rn_builtin_error.c
@@ -8,13 +8,13 @@ int main ()
int arguments. The builtins __builtin_set_fpscr_rn() also supports a
variable as an argument but can't test variable value at compile time. */
- __builtin_mtfsb0(-1); /* { dg-error "Argument must be a constant between 0 and 31" } */
- __builtin_mtfsb0(32); /* { dg-error "Argument must be a constant between 0 and 31" } */
+ __builtin_mtfsb0(-1); /* { dg-error "argument 1 must be a 5-bit unsigned literal" } */
+ __builtin_mtfsb0(32); /* { dg-error "argument 1 must be a 5-bit unsigned literal" } */
- __builtin_mtfsb1(-1); /* { dg-error "Argument must be a constant between 0 and 31" } */
- __builtin_mtfsb1(32); /* { dg-error "Argument must be a constant between 0 and 31" } */
+ __builtin_mtfsb1(-1); /* { dg-error "argument 1 must be a 5-bit unsigned literal" } */
+ __builtin_mtfsb1(32); /* { dg-error "argument 1 must be a 5-bit unsigned literal" } */
- __builtin_set_fpscr_rn(-1); /* { dg-error "Argument must be a value between 0 and 3" } */
- __builtin_set_fpscr_rn(4); /* { dg-error "Argument must be a value between 0 and 3" } */
+ __builtin_set_fpscr_rn(-1); /* { dg-error "argument 1 must be a variable or a literal between 0 and 3, inclusive" } */
+ __builtin_set_fpscr_rn(4); /* { dg-error "argument 1 must be a variable or a literal between 0 and 3, inclusive" } */
}
^ permalink raw reply [flat|nested] 29+ messages in thread
* [gcc(refs/users/wschmidt/heads/builtins4)] rs6000: More bug fixes
@ 2021-01-14 23:07 William Schmidt
0 siblings, 0 replies; 29+ messages in thread
From: William Schmidt @ 2021-01-14 23:07 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:37e08634788ae74488be734f9cce3a87e9be96bc
commit 37e08634788ae74488be734f9cce3a87e9be96bc
Author: Bill Schmidt <wschmidt@linux.ibm.com>
Date: Thu Jan 14 17:06:55 2021 -0600
rs6000: More bug fixes
2021-01-14 Bill Schmidt <wschmidt@linux.ibm.com>
gcc/
* config/rs6000/rs6000-builtin-new.def: Assorted fixes.
* config/rs6000/rs6000-overload.def: Assorted fixes.
gcc/testsuite/
* gcc.target/powerpc/altivec-7.c: Adjust.
* gcc.target/powerpc/cmpb-2.c: Adjust.
* gcc.target/powerpc/cmpb32-2.c: Adjust.
* gcc.target/powerpc/fold-vec-mule-misc.c: Adjust.
* gcc.target/powerpc/fold-vec-splat-floatdouble.c: Adjust.
* gcc.target/powerpc/fold-vec-splat-longlong.c: Adjust.
* gcc.target/powerpc/fold-vec-splat-misc-invalid.c: Adjust.
* gcc.target/powerpc/p8vector-builtin-2.c: Adjust.
* gcc.target/powerpc/p8vector-builtin-3.c: Adjust.
* gcc.target/powerpc/p8vector-builtin-4.c: Adjust.
* gcc.target/powerpc/p8vector-builtin-7.c: Adjust.
Diff:
---
gcc/config/rs6000/altivec.h | 2 +
gcc/config/rs6000/rs6000-builtin-new.def | 24 ++--
gcc/config/rs6000/rs6000-overload.def | 11 +-
gcc/testsuite/gcc.target/powerpc/altivec-7.c | 2 +-
gcc/testsuite/gcc.target/powerpc/cmpb-2.c | 2 +-
gcc/testsuite/gcc.target/powerpc/cmpb32-2.c | 2 +-
.../gcc.target/powerpc/fold-vec-mule-misc.c | 8 +-
.../powerpc/fold-vec-splat-floatdouble.c | 4 +-
.../gcc.target/powerpc/fold-vec-splat-longlong.c | 10 +-
.../powerpc/fold-vec-splat-misc-invalid.c | 8 +-
.../gcc.target/powerpc/p8vector-builtin-2.c | 55 ---------
.../gcc.target/powerpc/p8vector-builtin-3.c | 27 +----
.../gcc.target/powerpc/p8vector-builtin-4.c | 124 ++++-----------------
.../gcc.target/powerpc/p8vector-builtin-7.c | 8 +-
14 files changed, 61 insertions(+), 226 deletions(-)
diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h
index 0eae8a6404a..8904d2c545d 100644
--- a/gcc/config/rs6000/altivec.h
+++ b/gcc/config/rs6000/altivec.h
@@ -66,6 +66,8 @@
/* VSX additions */
#define vec_vsx_ld __builtin_vec_vsx_ld
#define vec_vsx_st __builtin_vec_vsx_st
+#define __builtin_vec_xl __builtin_vec_vsx_ld
+#define __builtin_vec_xst __builtin_vec_vsx_st
#define __builtin_bcdadd_ofl __builtin_vec_bcdadd_ov
#define __builtin_bcdsub_ofl __builtin_vec_bcdsub_ov
diff --git a/gcc/config/rs6000/rs6000-builtin-new.def b/gcc/config/rs6000/rs6000-builtin-new.def
index 9c4470bf400..449dcd5e257 100644
--- a/gcc/config/rs6000/rs6000-builtin-new.def
+++ b/gcc/config/rs6000/rs6000-builtin-new.def
@@ -805,13 +805,13 @@
const vus __builtin_altivec_vpkswus (vsi, vsi);
VPKSWUS altivec_vpkswus {}
- const vuc __builtin_altivec_vpkuhum (vus, vus);
+ const vsc __builtin_altivec_vpkuhum (vss, vss);
VPKUHUM altivec_vpkuhum {}
const vuc __builtin_altivec_vpkuhus (vus, vus);
VPKUHUS altivec_vpkuhus {}
- const vus __builtin_altivec_vpkuwum (vui, vui);
+ const vss __builtin_altivec_vpkuwum (vsi, vsi);
VPKUWUM altivec_vpkuwum {}
const vus __builtin_altivec_vpkuwus (vui, vui);
@@ -1219,7 +1219,7 @@
const vsll __builtin_altivec_vreve_v2di (vsll);
VREVE_V2DI altivec_vrevev2di2 {}
- const vd __builtin_altivec_vsel_2df (vd, vd, vull);
+ const vd __builtin_altivec_vsel_2df (vd, vd, vd);
VSEL_2DF vector_select_v2df {}
const vsll __builtin_altivec_vsel_2di (vsll, vsll, vull);
@@ -2263,7 +2263,7 @@
const vui __builtin_altivec_vpksdus (vsll, vsll);
VPKSDUS altivec_vpksdus {}
- const vui __builtin_altivec_vpkudum (vull, vull);
+ const vsi __builtin_altivec_vpkudum (vsll, vsll);
VPKUDUM altivec_vpkudum {}
const vui __builtin_altivec_vpkudus (vull, vull);
@@ -2285,13 +2285,13 @@
; const vull __builtin_altivec_vpmsumw (vui, vui);
; VPMSUMW crypto_vpmsumw {}
- const vuc __builtin_altivec_vpopcntb (vsc);
+ const vsc __builtin_altivec_vpopcntb (vsc);
VPOPCNTB popcountv16qi2 {}
- const vull __builtin_altivec_vpopcntd (vsll);
+ const vsll __builtin_altivec_vpopcntd (vsll);
VPOPCNTD popcountv2di2 {}
- const vus __builtin_altivec_vpopcnth (vss);
+ const vss __builtin_altivec_vpopcnth (vss);
VPOPCNTH popcountv8hi2 {}
const vuc __builtin_altivec_vpopcntub (vuc);
@@ -2306,16 +2306,16 @@
const vui __builtin_altivec_vpopcntuw (vui);
VPOPCNTUW popcountv4si2 {}
- const vui __builtin_altivec_vpopcntw (vsi);
+ const vsi __builtin_altivec_vpopcntw (vsi);
VPOPCNTW popcountv4si2 {}
- const vsll __builtin_altivec_vrld (vsll, vull);
+ const vsll __builtin_altivec_vrld (vsll, vsll);
VRLD vrotlv2di3 {}
- const vsll __builtin_altivec_vsld (vsll, vull);
+ const vsll __builtin_altivec_vsld (vsll, vsll);
VSLD vashlv2di3 {}
- const vsll __builtin_altivec_vsrad (vsll, vull);
+ const vsll __builtin_altivec_vsrad (vsll, vsll);
VSRAD vashrv2di3 {}
const vsll __builtin_altivec_vsrd (vsll, vull);
@@ -2330,7 +2330,7 @@
const vuq __builtin_altivec_vsubeuqm (vuq, vuq, vuq);
VSUBEUQM altivec_vsubeuqm {}
- const vull __builtin_altivec_vsubudm (vull, vull);
+ const vsll __builtin_altivec_vsubudm (vsll, vsll);
VSUBUDM subv2di3 {}
const vuq __builtin_altivec_vsubuqm (vuq, vuq);
diff --git a/gcc/config/rs6000/rs6000-overload.def b/gcc/config/rs6000/rs6000-overload.def
index e80e163f8ec..f6e43b88e07 100644
--- a/gcc/config/rs6000/rs6000-overload.def
+++ b/gcc/config/rs6000/rs6000-overload.def
@@ -3830,7 +3830,7 @@
void __builtin_vec_stl (vd, signed long long, double *);
STVXL_V2DF STVXL_D
-[VEC_STRIL, vec_stril, __builtin_vec_stril, ARCH_PWR10]
+[VEC_STRIL, vec_stril, __builtin_vec_stril, _ARCH_PWR10]
vuc __builtin_vec_stril (vuc);
VSTRIBL VSTRIBL_U
vsc __builtin_vec_stril (vsc);
@@ -3860,7 +3860,7 @@
vss __builtin_vec_strir (vss);
VSTRIHR VSTRIHR_S
-[VEC_STRIR_P, vec_strir_p, __builtin_vec_strir_p, ARCH_PWR10]
+[VEC_STRIR_P, vec_strir_p, __builtin_vec_strir_p, _ARCH_PWR10]
signed int __builtin_vec_strir_p (vuc);
VSTRIBR_P VSTRIBR_PU
signed int __builtin_vec_strir_p (vsc);
@@ -4131,11 +4131,8 @@
VSUBEUQM VSUBEUQM_VUQ
; TODO: Note that the entry for VEC_SUBEC currently gets ignored in
-; altivec_resolve_overloaded_builtin. There are also forms for
-; vsi and vui arguments, but rather than building a define_expand
-; for the instruction sequence generated for those, we do some RTL
-; hackery. Revisit whether we can remove that. For now, keep this
-; much of the entry here to generate the #define, at least.
+; altivec_resolve_overloaded_builtin. Revisit whether we can remove
+; that. We still need to register the legal builtin forms here.
[VEC_SUBEC, vec_subec, __builtin_vec_subec]
vsq __builtin_vec_subec (vsq, vsq, vsq);
VSUBECUQ VSUBECUQ_VSQ
diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-7.c b/gcc/testsuite/gcc.target/powerpc/altivec-7.c
index 46bf7148b20..52f5ecc8d59 100644
--- a/gcc/testsuite/gcc.target/powerpc/altivec-7.c
+++ b/gcc/testsuite/gcc.target/powerpc/altivec-7.c
@@ -84,7 +84,7 @@ int main ()
/* { dg-final { scan-assembler-times {\mlvx\M} 39 { target { ! powerpc_vsx } } } } */
/* { dg-final { scan-assembler-times {\mlxv} 0 { target { ! powerpc_vsx } } } } */
/* { dg-final { scan-assembler-times {\mlvx\M} 0 { target powerpc_vsx } } } */
-/* { dg-final { scan-assembler-times {\mlxv} 42 { target powerpc_vsx } } } */
+/* { dg-final { scan-assembler-times {\mlxv} 39 { target powerpc_vsx } } } */
/* { dg-final { scan-assembler-times "lvewx" 1 } } */
/* { dg-final { scan-assembler-times "lvxl" 1 } } */
/* { dg-final { scan-assembler-times "vupklsh" 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/cmpb-2.c b/gcc/testsuite/gcc.target/powerpc/cmpb-2.c
index 113ab6a5f99..02b84d0731d 100644
--- a/gcc/testsuite/gcc.target/powerpc/cmpb-2.c
+++ b/gcc/testsuite/gcc.target/powerpc/cmpb-2.c
@@ -8,7 +8,7 @@ void abort ();
unsigned long long int
do_compare (unsigned long long int a, unsigned long long int b)
{
- return __builtin_cmpb (a, b); /* { dg-warning "implicit declaration of function '__builtin_cmpb'" } */
+ return __builtin_cmpb (a, b); /* { dg-error "'__builtin_p6_cmpb' requires the '-mcpu=power6' option" } */
}
void
diff --git a/gcc/testsuite/gcc.target/powerpc/cmpb32-2.c b/gcc/testsuite/gcc.target/powerpc/cmpb32-2.c
index 37b54745e0e..d4264ab6e7d 100644
--- a/gcc/testsuite/gcc.target/powerpc/cmpb32-2.c
+++ b/gcc/testsuite/gcc.target/powerpc/cmpb32-2.c
@@ -7,7 +7,7 @@ void abort ();
unsigned int
do_compare (unsigned int a, unsigned int b)
{
- return __builtin_cmpb (a, b); /* { dg-warning "implicit declaration of function '__builtin_cmpb'" } */
+ return __builtin_cmpb (a, b); /* { dg-error "'__builtin_p6_cmpb_32' requires the '-mcpu=power6' option" } */
}
void
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-mule-misc.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-mule-misc.c
index 7daf30215b8..19a5d044c4d 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-mule-misc.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-mule-misc.c
@@ -11,7 +11,7 @@ test_eub_char ()
{
volatile vector unsigned char v0 = {1, 0, 0, 0, 0, 0, 0, 0};
volatile vector unsigned char v1 = {0xff, 0, 0, 0, 0, 0, 0, 0};
- vector unsigned short res = vec_vmuleub (v0, v1);
+ vector unsigned short res = vec_mule (v0, v1);
if (res[0] != (unsigned short)v0[0] * (unsigned short)v1[0])
__builtin_abort ();
}
@@ -21,7 +21,7 @@ test_oub_char ()
{
volatile vector unsigned char v0 = {0, 1, 0, 0, 0, 0, 0, 0};
volatile vector unsigned char v1 = {0, 0xff, 0, 0, 0, 0, 0, 0};
- vector unsigned short res = vec_vmuloub (v0, v1);
+ vector unsigned short res = vec_mulo (v0, v1);
if (res[0] != (unsigned short)v0[1] * (unsigned short)v1[1])
__builtin_abort ();
}
@@ -31,7 +31,7 @@ test_euh_short ()
{
volatile vector unsigned short v0 = {1, 0, 0, 0};
volatile vector unsigned short v1 = {0xff, 0, 0, 0};
- vector unsigned int res = vec_vmuleuh (v0, v1);
+ vector unsigned int res = vec_mule (v0, v1);
if (res[0] != (unsigned int)v0[0] * (unsigned int)v1[0])
__builtin_abort ();
}
@@ -41,7 +41,7 @@ test_ouh_short ()
{
volatile vector unsigned short v0 = {0, 1, 0, 0};
volatile vector unsigned short v1 = {0, 0xff, 0, 0};
- vector unsigned int res = vec_vmulouh (v0, v1);
+ vector unsigned int res = vec_mulo (v0, v1);
if (res[0] != (unsigned int)v0[1] * (unsigned int)v1[1])
__builtin_abort ();
}
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-floatdouble.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-floatdouble.c
index ab396967c3d..3f22ba31862 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-floatdouble.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-floatdouble.c
@@ -18,7 +18,7 @@ vector float test_fc ()
vector double testd_00 (vector double x) { return vec_splat (x, 0b00000); }
vector double testd_01 (vector double x) { return vec_splat (x, 0b00001); }
vector double test_dc ()
-{ const vector double y = { 3.0, 5.0 }; return vec_splat (y, 0b00010); }
+{ const vector double y = { 3.0, 5.0 }; return vec_splat (y, 0b00001); }
/* If the source vector is a known constant, we will generate a load. */
/* { dg-final { scan-assembler-times {\mlvx\M|\mlxvd2x\M|\mlxv\M} 2 } } */
@@ -27,5 +27,5 @@ vector double test_dc ()
/* { dg-final { scan-assembler-times "vspltw|xxspltw" 3 } } */
/* For double types, we will generate xxpermdi instructions. */
-/* { dg-final { scan-assembler-times "xxpermdi" 3 } } */
+/* { dg-final { scan-assembler-times "xxpermdi" 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-longlong.c
index 4fa06c85ecc..9376f702a7a 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-longlong.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-longlong.c
@@ -9,23 +9,19 @@
vector bool long long testb_00 (vector bool long long x) { return vec_splat (x, 0b00000); }
vector bool long long testb_01 (vector bool long long x) { return vec_splat (x, 0b00001); }
-vector bool long long testb_02 (vector bool long long x) { return vec_splat (x, 0b00010); }
vector signed long long tests_00 (vector signed long long x) { return vec_splat (x, 0b00000); }
vector signed long long tests_01 (vector signed long long x) { return vec_splat (x, 0b00001); }
-vector signed long long tests_02 (vector signed long long x) { return vec_splat (x, 0b00010); }
vector unsigned long long testu_00 (vector unsigned long long x) { return vec_splat (x, 0b00000); }
vector unsigned long long testu_01 (vector unsigned long long x) { return vec_splat (x, 0b00001); }
-vector unsigned long long testu_02 (vector unsigned long long x) { return vec_splat (x, 0b00010); }
/* Similar test as above, but the source vector is a known constant. */
-vector bool long long test_bll () { const vector bool long long y = {12, 23}; return vec_splat (y, 0b00010); }
-vector signed long long test_sll () { const vector signed long long y = {34, 45}; return vec_splat (y, 0b00010); }
-vector unsigned long long test_ull () { const vector unsigned long long y = {56, 67}; return vec_splat (y, 0b00010); }
+vector bool long long test_bll () { const vector bool long long y = {12, 23}; return vec_splat (y, 0b00001); }
+vector signed long long test_sll () { const vector signed long long y = {34, 45}; return vec_splat (y, 0b00001); }
/* Assorted load instructions for the initialization with known constants. */
-/* { dg-final { scan-assembler-times {\mlvx\M|\mlxvd2x\M|\mlxv\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mlvx\M|\mlxvd2x\M|\mlxv\M|\mxxspltib\M} 2 } } */
/* xxpermdi for vec_splat of long long vectors.
At the time of this writing, the number of xxpermdi instructions
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-misc-invalid.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-misc-invalid.c
index 20f5b05561e..263a1723d31 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-misc-invalid.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-misc-invalid.c
@@ -10,24 +10,24 @@
vector signed short
testss_1 (unsigned int ui)
{
- return vec_splat_s16 (ui);/* { dg-error "argument 1 must be a 5-bit signed literal" } */
+ return vec_splat_s16 (ui);/* { dg-error "argument 1 must be a literal between -16 and 15, inclusive" } */
}
vector unsigned short
testss_2 (signed int si)
{
- return vec_splat_u16 (si);/* { dg-error "argument 1 must be a 5-bit signed literal" } */
+ return vec_splat_u16 (si);/* { dg-error "argument 1 must be a literal between -16 and 15, inclusive" } */
}
vector signed char
testsc_1 (unsigned int ui)
{
- return vec_splat_s8 (ui); /* { dg-error "argument 1 must be a 5-bit signed literal" } */
+ return vec_splat_s8 (ui); /* { dg-error "argument 1 must be a literal between -16 and 15, inclusive" } */
}
vector unsigned char
testsc_2 (signed int si)
{
- return vec_splat_u8 (si);/* { dg-error "argument 1 must be a 5-bit signed literal" } */
+ return vec_splat_u8 (si);/* { dg-error "argument 1 must be a literal between -16 and 15, inclusive" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c
index 102e1d1f813..0259e364aa6 100644
--- a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c
+++ b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c
@@ -27,11 +27,6 @@ v_sign sign_add_2 (v_sign a, v_sign b)
return vec_add (a, b);
}
-v_sign sign_add_3 (v_sign a, v_sign b)
-{
- return vec_vaddudm (a, b);
-}
-
v_sign sign_sub_1 (v_sign a, v_sign b)
{
return __builtin_altivec_vsubudm (a, b);
@@ -43,11 +38,6 @@ v_sign sign_sub_2 (v_sign a, v_sign b)
}
-v_sign sign_sub_3 (v_sign a, v_sign b)
-{
- return vec_vsubudm (a, b);
-}
-
v_sign sign_min_1 (v_sign a, v_sign b)
{
return __builtin_altivec_vminsd (a, b);
@@ -58,11 +48,6 @@ v_sign sign_min_2 (v_sign a, v_sign b)
return vec_min (a, b);
}
-v_sign sign_min_3 (v_sign a, v_sign b)
-{
- return vec_vminsd (a, b);
-}
-
v_sign sign_max_1 (v_sign a, v_sign b)
{
return __builtin_altivec_vmaxsd (a, b);
@@ -73,11 +58,6 @@ v_sign sign_max_2 (v_sign a, v_sign b)
return vec_max (a, b);
}
-v_sign sign_max_3 (v_sign a, v_sign b)
-{
- return vec_vmaxsd (a, b);
-}
-
v_sign sign_abs (v_sign a)
{
return vec_abs (a); /* xor, vsubudm, vmaxsd. */
@@ -98,41 +78,21 @@ v_uns uns_add_2 (v_uns a, v_uns b)
return vec_add (a, b);
}
-v_uns uns_add_3 (v_uns a, v_uns b)
-{
- return vec_vaddudm (a, b);
-}
-
v_uns uns_sub_2 (v_uns a, v_uns b)
{
return vec_sub (a, b);
}
-v_uns uns_sub_3 (v_uns a, v_uns b)
-{
- return vec_vsubudm (a, b);
-}
-
v_uns uns_min_2 (v_uns a, v_uns b)
{
return vec_min (a, b);
}
-v_uns uns_min_3 (v_uns a, v_uns b)
-{
- return vec_vminud (a, b);
-}
-
v_uns uns_max_2 (v_uns a, v_uns b)
{
return vec_max (a, b);
}
-v_uns uns_max_3 (v_uns a, v_uns b)
-{
- return vec_vmaxud (a, b);
-}
-
v_bool uns_eq (v_uns a, v_uns b)
{
return vec_cmpeq (a, b);
@@ -168,21 +128,11 @@ v_sign sign_sl_2 (v_sign a, v_uns b)
return vec_sl (a, b);
}
-v_sign sign_sl_3 (v_sign a, v_uns b)
-{
- return vec_vsld (a, b);
-}
-
v_uns uns_sl_2 (v_uns a, v_uns b)
{
return vec_sl (a, b);
}
-v_uns uns_sl_3 (v_uns a, v_uns b)
-{
- return vec_vsld (a, b);
-}
-
v_sign sign_sra_1 (v_sign a, v_sign b)
{
return __builtin_altivec_vsrad (a, b);
@@ -193,11 +143,6 @@ v_sign sign_sra_2 (v_sign a, v_uns b)
return vec_sra (a, b);
}
-v_sign sign_sra_3 (v_sign a, v_uns b)
-{
- return vec_vsrad (a, b);
-}
-
v_bchar vbchar_eq (v_bchar a, v_bchar b)
{
return vec_cmpeq (a, b);
diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-3.c b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-3.c
index 33304fe6132..ae6a3a8437b 100644
--- a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-3.c
@@ -37,11 +37,6 @@ vi_uns vi_pack_3 (vll_uns a, vll_uns b)
return vec_pack (a, b);
}
-vi_sign vi_pack_4 (vll_sign a, vll_sign b)
-{
- return vec_vpkudum (a, b);
-}
-
vs_sign vs_pack_1 (vi_sign a, vi_sign b)
{
return __builtin_altivec_vpkuwum (a, b);
@@ -52,11 +47,6 @@ vs_sign vs_pack_2 (vi_sign a, vi_sign b)
return vec_pack (a, b);
}
-vs_sign vs_pack_3 (vi_sign a, vi_sign b)
-{
- return vec_vpkuwum (a, b);
-}
-
vc_sign vc_pack_1 (vs_sign a, vs_sign b)
{
return __builtin_altivec_vpkuhum (a, b);
@@ -67,11 +57,6 @@ vc_sign vc_pack_2 (vs_sign a, vs_sign b)
return vec_pack (a, b);
}
-vc_sign vc_pack_3 (vs_sign a, vs_sign b)
-{
- return vec_vpkuhum (a, b);
-}
-
vll_sign vll_unpack_hi_1 (vi_sign a)
{
return __builtin_altivec_vupkhsw (a);
@@ -84,12 +69,7 @@ vll_sign vll_unpack_hi_2 (vi_sign a)
vll_sign vll_unpack_hi_3 (vi_sign a)
{
- return __builtin_vec_vupkhsw (a);
-}
-
-vll_sign vll_unpack_lo_1 (vi_sign a)
-{
- return vec_vupklsw (a);
+ return __builtin_altivec_vupkhsw (a);
}
vll_sign vll_unpack_lo_2 (vi_sign a)
@@ -97,11 +77,6 @@ vll_sign vll_unpack_lo_2 (vi_sign a)
return vec_unpackl (a);
}
-vll_sign vll_unpack_lo_3 (vi_sign a)
-{
- return vec_vupklsw (a);
-}
-
/* { dg-final { scan-assembler-times "vpkudum" 4 } } */
/* { dg-final { scan-assembler-times "vpkuwum" 3 } } */
/* { dg-final { scan-assembler-times "vpkuhum" 3 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-4.c b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-4.c
index 8329e2bae5a..2d2d141948f 100644
--- a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-4.c
+++ b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-4.c
@@ -28,22 +28,12 @@ vll_sign vll_clz_1 (vll_sign a)
vll_sign vll_clz_2 (vll_sign a)
{
- return vec_vclz (a);
-}
-
-vll_sign vll_clz_3 (vll_sign a)
-{
- return vec_vclzd (a);
+ return vec_cntlz (a);
}
vll_uns vll_clz_4 (vll_uns a)
{
- return vec_vclz (a);
-}
-
-vll_uns vll_clz_5 (vll_uns a)
-{
- return vec_vclzd (a);
+ return vec_cntlz (a);
}
vi_sign vi_clz_1 (vi_sign a)
@@ -53,22 +43,12 @@ vi_sign vi_clz_1 (vi_sign a)
vi_sign vi_clz_2 (vi_sign a)
{
- return vec_vclz (a);
-}
-
-vi_sign vi_clz_3 (vi_sign a)
-{
- return vec_vclzw (a);
+ return vec_cntlz (a);
}
vi_uns vi_clz_4 (vi_uns a)
{
- return vec_vclz (a);
-}
-
-vi_uns vi_clz_5 (vi_uns a)
-{
- return vec_vclzw (a);
+ return vec_cntlz (a);
}
vs_sign vs_clz_1 (vs_sign a)
@@ -78,22 +58,12 @@ vs_sign vs_clz_1 (vs_sign a)
vs_sign vs_clz_2 (vs_sign a)
{
- return vec_vclz (a);
-}
-
-vs_sign vs_clz_3 (vs_sign a)
-{
- return vec_vclzh (a);
+ return vec_cntlz (a);
}
vs_uns vs_clz_4 (vs_uns a)
{
- return vec_vclz (a);
-}
-
-vs_uns vs_clz_5 (vs_uns a)
-{
- return vec_vclzh (a);
+ return vec_cntlz (a);
}
vc_sign vc_clz_1 (vc_sign a)
@@ -103,22 +73,12 @@ vc_sign vc_clz_1 (vc_sign a)
vc_sign vc_clz_2 (vc_sign a)
{
- return vec_vclz (a);
-}
-
-vc_sign vc_clz_3 (vc_sign a)
-{
- return vec_vclzb (a);
+ return vec_cntlz (a);
}
vc_uns vc_clz_4 (vc_uns a)
{
- return vec_vclz (a);
-}
-
-vc_uns vc_clz_5 (vc_uns a)
-{
- return vec_vclzb (a);
+ return vec_cntlz (a);
}
vll_sign vll_popcnt_1 (vll_sign a)
@@ -126,24 +86,14 @@ vll_sign vll_popcnt_1 (vll_sign a)
return __builtin_altivec_vpopcntd (a);
}
-vll_sign vll_popcnt_2 (vll_sign a)
+vll_uns vll_popcnt_2 (vll_sign a)
{
- return vec_vpopcnt (a);
-}
-
-vll_sign vll_popcnt_3 (vll_sign a)
-{
- return vec_vpopcntd (a);
+ return vec_popcnt (a);
}
vll_uns vll_popcnt_4 (vll_uns a)
{
- return vec_vpopcnt (a);
-}
-
-vll_uns vll_popcnt_5 (vll_uns a)
-{
- return vec_vpopcntd (a);
+ return vec_popcnt (a);
}
vi_sign vi_popcnt_1 (vi_sign a)
@@ -151,24 +101,14 @@ vi_sign vi_popcnt_1 (vi_sign a)
return __builtin_altivec_vpopcntw (a);
}
-vi_sign vi_popcnt_2 (vi_sign a)
+vi_uns vi_popcnt_2 (vi_sign a)
{
- return vec_vpopcnt (a);
-}
-
-vi_sign vi_popcnt_3 (vi_sign a)
-{
- return vec_vpopcntw (a);
+ return vec_popcnt (a);
}
vi_uns vi_popcnt_4 (vi_uns a)
{
- return vec_vpopcnt (a);
-}
-
-vi_uns vi_popcnt_5 (vi_uns a)
-{
- return vec_vpopcntw (a);
+ return vec_popcnt (a);
}
vs_sign vs_popcnt_1 (vs_sign a)
@@ -176,24 +116,14 @@ vs_sign vs_popcnt_1 (vs_sign a)
return __builtin_altivec_vpopcnth (a);
}
-vs_sign vs_popcnt_2 (vs_sign a)
+vs_uns vs_popcnt_2 (vs_sign a)
{
- return vec_vpopcnt (a);
-}
-
-vs_sign vs_popcnt_3 (vs_sign a)
-{
- return vec_vpopcnth (a);
+ return vec_popcnt (a);
}
vs_uns vs_popcnt_4 (vs_uns a)
{
- return vec_vpopcnt (a);
-}
-
-vs_uns vs_popcnt_5 (vs_uns a)
-{
- return vec_vpopcnth (a);
+ return vec_popcnt (a);
}
vc_sign vc_popcnt_1 (vc_sign a)
@@ -201,24 +131,14 @@ vc_sign vc_popcnt_1 (vc_sign a)
return __builtin_altivec_vpopcntb (a);
}
-vc_sign vc_popcnt_2 (vc_sign a)
+vc_uns vc_popcnt_2 (vc_sign a)
{
- return vec_vpopcnt (a);
-}
-
-vc_sign vc_popcnt_3 (vc_sign a)
-{
- return vec_vpopcntb (a);
+ return vec_popcnt (a);
}
vc_uns vc_popcnt_4 (vc_uns a)
{
- return vec_vpopcnt (a);
-}
-
-vc_uns vc_popcnt_5 (vc_uns a)
-{
- return vec_vpopcntb (a);
+ return vec_popcnt (a);
}
vc_uns vc_gbb_1 (vc_uns a)
@@ -228,12 +148,12 @@ vc_uns vc_gbb_1 (vc_uns a)
vc_sign vc_gbb_2 (vc_sign a)
{
- return vec_vgbbd (a);
+ return vec_gb (a);
}
vc_uns vc_gbb_3 (vc_uns a)
{
- return vec_vgbbd (a);
+ return vec_gb (a);
}
/* { dg-final { scan-assembler-times "vclzd" 5 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-7.c b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-7.c
index fcfac7c50b1..f3035000fe7 100644
--- a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-7.c
+++ b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-7.c
@@ -10,22 +10,22 @@ typedef vector unsigned int v_uns;
v_sign even_sign (v_sign a, v_sign b)
{
- return vec_vmrgew (a, b);
+ return vec_mergee (a, b);
}
v_uns even_uns (v_uns a, v_uns b)
{
- return vec_vmrgew (a, b);
+ return vec_mergee (a, b);
}
v_sign odd_sign (v_sign a, v_sign b)
{
- return vec_vmrgow (a, b);
+ return vec_mergeo (a, b);
}
v_uns odd_uns (v_uns a, v_uns b)
{
- return vec_vmrgow (a, b);
+ return vec_mergeo (a, b);
}
/* { dg-final { scan-assembler-times "vmrgew" 2 } } */
^ permalink raw reply [flat|nested] 29+ messages in thread
* [gcc(refs/users/wschmidt/heads/builtins4)] rs6000: More bug fixes
@ 2021-01-13 21:47 William Schmidt
0 siblings, 0 replies; 29+ messages in thread
From: William Schmidt @ 2021-01-13 21:47 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:20bd4638aba09d1077f585a00e42d4cfb312fb38
commit 20bd4638aba09d1077f585a00e42d4cfb312fb38
Author: Bill Schmidt <wschmidt@linux.ibm.com>
Date: Wed Jan 13 15:47:32 2021 -0600
rs6000: More bug fixes
2021-01-13 Bill Schmidt <wschmidt@linux.ibm.com>
gcc/
* config/rs6000/rs6000-builtin-new.def: Assorted fixes.
* config/rs6000/rs6000-c.c
(altivec_resolve_new_overloaded_builtin): Fix thinko.
* config/rs6000/rs6000-call.c (rs6000_invalid_new_builtin): Handle
ENB_P10_64.
(rs6000_new_builtin_is_supported_p): Likewise.
(rs6000_expand_new_builtin): Likewise.
(rs6000_init_builtins): Likewise.
* config/rs6000/rs6000-gen-builtins.c (write_defines_file):
Define _ARCH_PPC64_PWR9 when appropriate.
* config/rs6000/rs6000-overload.def: Assorted fixes.
gcc/testsuite/
* gcc.target/powerpc/altivec-7.c: Remove vec_lvx call and adjust
counts.
* gcc.target/powerpc/ctz-4.c: Don't use deprecated builtins.
Diff:
---
gcc/config/rs6000/rs6000-builtin-new.def | 26 ++++-----
gcc/config/rs6000/rs6000-c.c | 2 +-
gcc/config/rs6000/rs6000-call.c | 14 +++++
gcc/config/rs6000/rs6000-gen-builtins.c | 3 +
gcc/config/rs6000/rs6000-overload.def | 84 ++++++++++++----------------
gcc/testsuite/gcc.target/powerpc/altivec-7.c | 5 +-
gcc/testsuite/gcc.target/powerpc/ctz-4.c | 64 +++------------------
7 files changed, 76 insertions(+), 122 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-builtin-new.def b/gcc/config/rs6000/rs6000-builtin-new.def
index 68d1a7d361a..9c4470bf400 100644
--- a/gcc/config/rs6000/rs6000-builtin-new.def
+++ b/gcc/config/rs6000/rs6000-builtin-new.def
@@ -1087,28 +1087,28 @@
; Cell builtins.
[cell]
- pure vuc __builtin_altivec_lvlx (signed long long, const void *);
+ pure vsc __builtin_altivec_lvlx (signed long long, const void *);
LVLX altivec_lvlx {ldvec}
- pure vuc __builtin_altivec_lvlxl (signed long long, const void *);
+ pure vsc __builtin_altivec_lvlxl (signed long long, const void *);
LVLXL altivec_lvlxl {ldvec}
- pure vuc __builtin_altivec_lvrx (signed long long, const void *);
+ pure vsc __builtin_altivec_lvrx (signed long long, const void *);
LVRX altivec_lvrx {ldvec}
- pure vuc __builtin_altivec_lvrxl (signed long long, const void *);
+ pure vsc __builtin_altivec_lvrxl (signed long long, const void *);
LVRXL altivec_lvrxl {ldvec}
- void __builtin_altivec_stvlx (vuc, signed long long, void *);
+ void __builtin_altivec_stvlx (vsc, signed long long, void *);
STVLX altivec_stvlx {stvec}
- void __builtin_altivec_stvlxl (vuc, signed long long, void *);
+ void __builtin_altivec_stvlxl (vsc, signed long long, void *);
STVLXL altivec_stvlxl {stvec}
- void __builtin_altivec_stvrx (vuc, signed long long, void *);
+ void __builtin_altivec_stvrx (vsc, signed long long, void *);
STVRX altivec_stvrx {stvec}
- void __builtin_altivec_stvrxl (vuc, signed long long, void *);
+ void __builtin_altivec_stvrxl (vsc, signed long long, void *);
STVRXL altivec_stvrxl {stvec}
@@ -2681,10 +2681,10 @@
const vuc __builtin_altivec_vsrv (vuc, vuc);
VSRV vsrv {}
- const signed int __builtin_scalar_byte_in_range (unsigned char, unsigned int);
+ const signed int __builtin_scalar_byte_in_range (unsigned int, unsigned int);
CMPRB cmprb {}
- const signed int __builtin_scalar_byte_in_either_range (unsigned char, unsigned int);
+ const signed int __builtin_scalar_byte_in_either_range (unsigned int, unsigned int);
CMPRB2 cmprb2 {}
const vull __builtin_vsx_extract4b (vuc, const int[0,12]);
@@ -2825,7 +2825,7 @@
void __builtin_altivec_stxvl (vuc, void *, long long);
STXVL stxvl {}
- const signed int __builtin_scalar_byte_in_set (unsigned char, unsigned long long);
+ const signed int __builtin_scalar_byte_in_set (unsigned int, unsigned long long);
CMPEQB cmpeqb {}
pure vuc __builtin_vsx_lxvl (const void *, unsigned long long);
@@ -2904,10 +2904,10 @@
; Decimal floating-point builtins.
[dfp]
- const _Decimal64 __builtin_ddedpd (const int<0,2>, _Decimal64);
+ const _Decimal64 __builtin_ddedpd (const int<2>, _Decimal64);
DDEDPD dfp_ddedpd_dd {}
- const _Decimal128 __builtin_ddedpdq (const int<0,2>, _Decimal128);
+ const _Decimal128 __builtin_ddedpdq (const int<2>, _Decimal128);
DDEDPDQ dfp_ddedpd_td {}
const _Decimal64 __builtin_denbcd (const int<1>, _Decimal64);
diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c
index 4e535e535ac..11099d21006 100644
--- a/gcc/config/rs6000/rs6000-c.c
+++ b/gcc/config/rs6000/rs6000-c.c
@@ -2826,7 +2826,7 @@ altivec_resolve_new_overloaded_builtin (location_t loc, tree fndecl,
gcc_assert (instance != NULL);
tree fntype = rs6000_builtin_info_x[instance->bifid].fntype;
tree parmtype0 = TREE_VALUE (TYPE_ARG_TYPES (fntype));
- tree parmtype1 = TREE_VALUE (TREE_CHAIN (parmtype0));
+ tree parmtype1 = TREE_VALUE (TREE_CHAIN (TYPE_ARG_TYPES (fntype)));
if (rs6000_new_builtin_type_compatible (types[0], parmtype0)
&& rs6000_new_builtin_type_compatible (types[1], parmtype1))
diff --git a/gcc/config/rs6000/rs6000-call.c b/gcc/config/rs6000/rs6000-call.c
index fde516ab7cb..45ebdbe3f13 100644
--- a/gcc/config/rs6000/rs6000-call.c
+++ b/gcc/config/rs6000/rs6000-call.c
@@ -11771,6 +11771,10 @@ rs6000_invalid_new_builtin (enum rs6000_gen_builtins fncode)
case ENB_P10:
error ("%qs requires the %qs option", name, "-mcpu=power10");
break;
+ case ENB_P10_64:
+ error ("%qs requires the %qs option and either the %qs or %qs option",
+ name, "-mcpu=power10", "-m64", "-mpowerpc64");
+ break;
case ENB_MMA:
error ("%qs requires the %qs option", name, "-mmma");
break;
@@ -14045,6 +14049,10 @@ rs6000_new_builtin_is_supported_p (enum rs6000_gen_builtins fncode)
if (!TARGET_POWER10)
return false;
break;
+ case ENB_P10_64:
+ if (!TARGET_POWER10 || !TARGET_POWERPC64)
+ return false;
+ break;
case ENB_MMA:
if (!TARGET_MMA)
return false;
@@ -15304,6 +15312,10 @@ rs6000_expand_new_builtin (tree exp, rtx target,
if (!TARGET_POWER10)
return const0_rtx;
break;
+ case ENB_P10_64:
+ if (!TARGET_POWER10 || !TARGET_POWERPC64)
+ return const0_rtx;
+ break;
case ENB_MMA:
if (!TARGET_MMA)
return const0_rtx;
@@ -15953,6 +15965,8 @@ rs6000_init_builtins (void)
continue;
if (e == ENB_P10 && !TARGET_POWER10)
continue;
+ if (e == ENB_P10_64 && (!TARGET_POWER10 || !TARGET_POWERPC64))
+ continue;
if (e == ENB_MMA && !TARGET_MMA)
continue;
tree fntype = rs6000_builtin_info_x[i].fntype;
diff --git a/gcc/config/rs6000/rs6000-gen-builtins.c b/gcc/config/rs6000/rs6000-gen-builtins.c
index 8f129f47d8c..b75b29303dd 100644
--- a/gcc/config/rs6000/rs6000-gen-builtins.c
+++ b/gcc/config/rs6000/rs6000-gen-builtins.c
@@ -2768,6 +2768,9 @@ write_defines_file ()
{
fprintf (defines_file, "#ifndef _RS6000_VECDEFINES_H\n");
fprintf (defines_file, "#define _RS6000_VECDEFINES_H 1\n\n");
+ fprintf (defines_file, "#if defined(_ARCH_PPC64) && defined (_ARCH_PWR9)\n");
+ fprintf (defines_file, " #define _ARCH_PPC64_PWR9 1\n");
+ fprintf (defines_file, "#endif\n\n");
for (int i = 0; i < num_ovld_stanzas; i++)
if (strcmp (ovld_stanzas[i].extern_name, "SKIP"))
{
diff --git a/gcc/config/rs6000/rs6000-overload.def b/gcc/config/rs6000/rs6000-overload.def
index ec884b63388..e80e163f8ec 100644
--- a/gcc/config/rs6000/rs6000-overload.def
+++ b/gcc/config/rs6000/rs6000-overload.def
@@ -730,7 +730,7 @@
VCMPEQUD_P VCMPEQUD_P_SB
[VEC_CMPEQB, SKIP, __builtin_byte_in_set]
- signed int __builtin_byte_in_set (unsigned char, unsigned long long);
+ signed int __builtin_byte_in_set (unsigned int, unsigned long long);
CMPEQB
; #### XVCMPGESP{TARGET_VSX};VCMPGEFP
@@ -738,19 +738,19 @@
vbc __builtin_vec_cmpge (vsc, vsc);
CMPGE_16QI CMPGE_16QI_VSC
vbc __builtin_vec_cmpge (vuc, vuc);
- CMPGE_16QI CMPGE_16QI_VUC
+ CMPGE_U16QI CMPGE_16QI_VUC
vbs __builtin_vec_cmpge (vss, vss);
CMPGE_8HI CMPGE_8HI_VSS
vbs __builtin_vec_cmpge (vus, vus);
- CMPGE_8HI CMPGE_8HI_VUS
+ CMPGE_U8HI CMPGE_8HI_VUS
vbi __builtin_vec_cmpge (vsi, vsi);
CMPGE_4SI CMPGE_4SI_VSI
vbi __builtin_vec_cmpge (vui, vui);
- CMPGE_4SI CMPGE_4SI_VUI
+ CMPGE_U4SI CMPGE_4SI_VUI
vbll __builtin_vec_cmpge (vsll, vsll);
CMPGE_2DI CMPGE_2DI_VSLL
vbll __builtin_vec_cmpge (vull, vull);
- CMPGE_2DI CMPGE_2DI_VULL
+ CMPGE_U2DI CMPGE_2DI_VULL
vbi __builtin_vec_cmpge (vf, vf);
VCMPGEFP
vbll __builtin_vec_cmpge (vd, vd);
@@ -1021,11 +1021,11 @@
VCMPNEZW_P VCMPNEZW_VUI_P
[VEC_CMPRB, SKIP, __builtin_byte_in_range]
- signed int __builtin_byte_in_range (unsigned char, unsigned int);
+ signed int __builtin_byte_in_range (unsigned int, unsigned int);
CMPRB
[VEC_CMPRB2, SKIP, __builtin_byte_in_either_range]
- signed int __builtin_byte_in_range (unsigned char, unsigned int);
+ signed int __builtin_byte_in_range (unsigned int, unsigned int);
CMPRB2
[VEC_CNTLZ, vec_cntlz, __builtin_vec_vclz, _ARCH_PWR8]
@@ -4640,6 +4640,10 @@
STXVD2X_V2DI STXVD2X_ULL
void __builtin_vec_vsx_st (vbll, signed long long, vbll *);
STXVD2X_V2DI STXVD2X_VBLL
+ void __builtin_vec_vsx_st (vsq, signed long long, signed __int128 *);
+ STXVD2X_V1TI STXVD2X_SQ
+ void __builtin_vec_vsx_st (vuq, signed long long, unsigned __int128 *);
+ STXVD2X_V1TI STXVD2X_UQ
void __builtin_vec_vsx_st (vf, signed long long, vf *);
STXVW4X_V4SF STXVW4X_VF
void __builtin_vec_vsx_st (vf, signed long long, float *);
@@ -4651,67 +4655,49 @@
[VEC_XST_BE, vec_xst_be, __builtin_vec_xst_be, __VSX__]
void __builtin_vec_xst_be (vsc, signed long long, vsc *);
- STXVW4X_V16QI STXVW4X_VSC_BE
+ ST_ELEMREV_V16QI ST_ELEMREV_VSC
void __builtin_vec_xst_be (vsc, signed long long, signed char *);
- STXVW4X_V16QI STXVW4X_SC_BE
+ ST_ELEMREV_V16QI ST_ELEMREV_SC_
void __builtin_vec_xst_be (vuc, signed long long, vuc *);
- STXVW4X_V16QI STXVW4X_VUC_BE
+ ST_ELEMREV_V16QI ST_ELEMREV_VUC
void __builtin_vec_xst_be (vuc, signed long long, unsigned char *);
- STXVW4X_V16QI STXVW4X_UC_BE
- void __builtin_vec_xst_be (vbc, signed long long, vbc *);
- STXVW4X_V16QI STXVW4X_VBC_BE
- void __builtin_vec_xst_be (vbc, signed long long, signed char *);
- STXVW4X_V16QI STXVW4X_VBC_S_BE
- void __builtin_vec_xst_be (vbc, signed long long, unsigned char *);
- STXVW4X_V16QI STXVW4X_VBC_U_BE
+ ST_ELEMREV_V16QI ST_ELEMREV_UC
void __builtin_vec_xst_be (vss, signed long long, vss *);
- STXVW4X_V8HI STXVW4X_VSS_BE
+ ST_ELEMREV_V8HI ST_ELEMREV_VSS
void __builtin_vec_xst_be (vss, signed long long, signed short *);
- STXVW4X_V8HI STXVW4X_SS_BE
+ ST_ELEMREV_V8HI ST_ELEMREV_SS
void __builtin_vec_xst_be (vus, signed long long, vus *);
- STXVW4X_V8HI STXVW4X_VUS_BE
+ ST_ELEMREV_V8HI ST_ELEMREV_VUS
void __builtin_vec_xst_be (vus, signed long long, unsigned short *);
- STXVW4X_V8HI STXVW4X_US_BE
- void __builtin_vec_xst_be (vbs, signed long long, vbs *);
- STXVW4X_V8HI STXVW4X_VBS_BE
- void __builtin_vec_xst_be (vbs, signed long long, signed short *);
- STXVW4X_V8HI STXVW4X_VBS_S_BE
- void __builtin_vec_xst_be (vbs, signed long long, unsigned short *);
- STXVW4X_V8HI STXVW4X_VBS_U_BE
- void __builtin_vec_xst_be (vp, signed long long, vp *);
- STXVW4X_V8HI STXVW4X_VP_BE
+ ST_ELEMREV_V8HI ST_ELEMREV_US
void __builtin_vec_xst_be (vsi, signed long long, vsi *);
- STXVW4X_V4SI STXVW4X_VSI_BE
+ ST_ELEMREV_V4SI ST_ELEMREV_VSI
void __builtin_vec_xst_be (vsi, signed long long, signed int *);
- STXVW4X_V4SI STXVW4X_SI_BE
+ ST_ELEMREV_V4SI ST_ELEMREV_SI
void __builtin_vec_xst_be (vui, signed long long, vui *);
- STXVW4X_V4SI STXVW4X_VUI_BE
+ ST_ELEMREV_V4SI ST_ELEMREV_VUI
void __builtin_vec_xst_be (vui, signed long long, unsigned int *);
- STXVW4X_V4SI STXVW4X_UI_BE
- void __builtin_vec_xst_be (vbi, signed long long, vbi *);
- STXVW4X_V4SI STXVW4X_VBI_BE
- void __builtin_vec_xst_be (vbi, signed long long, signed int *);
- STXVW4X_V4SI STXVW4X_VBI_S_BE
- void __builtin_vec_xst_be (vbi, signed long long, unsigned int *);
- STXVW4X_V4SI STXVW4X_VBI_U_BE
+ ST_ELEMREV_V4SI ST_ELEMREV_UI
void __builtin_vec_xst_be (vsll, signed long long, vsll *);
- STXVD2X_V2DI STXVD2X_VSLL_BE
+ ST_ELEMREV_V2DI ST_ELEMREV_VSLL
void __builtin_vec_xst_be (vsll, signed long long, signed long long *);
- STXVD2X_V2DI STXVD2X_SLL_BE
+ ST_ELEMREV_V2DI ST_ELEMREV_SLL
void __builtin_vec_xst_be (vull, signed long long, vull *);
- STXVD2X_V2DI STXVD2X_VULL_BE
+ ST_ELEMREV_V2DI ST_ELEMREV_VULL
void __builtin_vec_xst_be (vull, signed long long, unsigned long long *);
- STXVD2X_V2DI STXVD2X_ULL_BE
- void __builtin_vec_xst_be (vbll, signed long long, vbll *);
- STXVD2X_V2DI STXVD2X_VBLL_BE
+ ST_ELEMREV_V2DI ST_ELEMREV_ULL
+ void __builtin_vec_xst_be (vsq, signed long long, signed __int128 *);
+ ST_ELEMREV_V1TI ST_ELEMREV_SQ
+ void __builtin_vec_xst_be (vuq, signed long long, unsigned __int128 *);
+ ST_ELEMREV_V1TI ST_ELEMREV_UQ
void __builtin_vec_xst_be (vf, signed long long, vf *);
- STXVW4X_V4SF STXVW4X_VF_BE
+ ST_ELEMREV_V4SF ST_ELEMREV_VF
void __builtin_vec_xst_be (vf, signed long long, float *);
- STXVW4X_V4SF STXVW4X_F_BE
+ ST_ELEMREV_V4SF ST_ELEMREV_F
void __builtin_vec_xst_be (vd, signed long long, vd *);
- STXVD2X_V2DF STXVD2X_VD_BE
+ ST_ELEMREV_V2DF ST_ELEMREV_VD
void __builtin_vec_xst_be (vd, signed long long, double *);
- STXVD2X_V2DF STXVD2X_D_BE
+ ST_ELEMREV_V2DF ST_ELEMREV_D
[VEC_XST_LEN_R, vec_xst_len_r, __builtin_vec_xst_len_r, _ARCH_PPC64_PWR9]
void __builtin_vsx_xst_len_r (vuc, unsigned char *, unsigned long long);
diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-7.c b/gcc/testsuite/gcc.target/powerpc/altivec-7.c
index 0cef426fcd9..46bf7148b20 100644
--- a/gcc/testsuite/gcc.target/powerpc/altivec-7.c
+++ b/gcc/testsuite/gcc.target/powerpc/altivec-7.c
@@ -41,7 +41,6 @@ int main ()
*vecushort++ = vec_xor((vector bool short)vecshort[0], vecushort[1]);
*vecushort++ = vec_xor(vecushort[0], (vector bool short)vecshort[1]);
*vecuint++ = vec_ld(var_int[0], uintp[1]);
- *vecuint++ = vec_lvx(var_int[0], uintp[1]);
*vecuint++ = vec_msum(vecuchar[0], vecuchar[1], vecuint[2]);
*vecuchar++ = vec_xor(vecuchar[0], (vector unsigned char)vecchar[1]);
@@ -79,10 +78,10 @@ int main ()
vec_ld lvx
*/
-/* { dg-final { scan-assembler-times "vpkpx" 2 } } */
+/* { dg-final { scan-assembler-times "vpkpx" 1 } } */
/* { dg-final { scan-assembler-times "vmulesb" 1 } } */
/* { dg-final { scan-assembler-times "vmulosb" 1 } } */
-/* { dg-final { scan-assembler-times {\mlvx\M} 42 { target { ! powerpc_vsx } } } } */
+/* { dg-final { scan-assembler-times {\mlvx\M} 39 { target { ! powerpc_vsx } } } } */
/* { dg-final { scan-assembler-times {\mlxv} 0 { target { ! powerpc_vsx } } } } */
/* { dg-final { scan-assembler-times {\mlvx\M} 0 { target powerpc_vsx } } } */
/* { dg-final { scan-assembler-times {\mlxv} 42 { target powerpc_vsx } } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/ctz-4.c b/gcc/testsuite/gcc.target/powerpc/ctz-4.c
index 74d305a8fbc..8e5f7699a63 100644
--- a/gcc/testsuite/gcc.target/powerpc/ctz-4.c
+++ b/gcc/testsuite/gcc.target/powerpc/ctz-4.c
@@ -8,97 +8,49 @@
vector signed char
count_trailing_zeros_v16qi_1s (vector signed char a)
{
- return vec_vctz (a);
-}
-
-vector signed char
-count_trailing_zeros_v16qi_2s (vector signed char a)
-{
- return vec_vctzb (a);
+ return vec_cnttz (a);
}
vector unsigned char
count_trailing_zeros_v16qi_1u (vector unsigned char a)
{
- return vec_vctz (a);
-}
-
-vector unsigned char
-count_trailing_zeros_v16qi_2u (vector unsigned char a)
-{
- return vec_vctzb (a);
+ return vec_cnttz (a);
}
vector short
count_trailing_zeros_v8hi_1s (vector short a)
{
- return vec_vctz (a);
-}
-
-vector short
-count_trailing_zeros_v8hi_2s (vector short a)
-{
- return vec_vctzh (a);
+ return vec_cnttz (a);
}
vector unsigned short
count_trailing_zeros_v8hi_1u (vector unsigned short a)
{
- return vec_vctz (a);
-}
-
-vector unsigned short
-count_trailing_zeros_v8hi_2u (vector unsigned short a)
-{
- return vec_vctzh (a);
+ return vec_cnttz (a);
}
vector int
count_trailing_zeros_v4si_1s (vector int a)
{
- return vec_vctz (a);
-}
-
-vector int
-count_trailing_zeros_v4si_2s (vector int a)
-{
- return vec_vctzw (a);
+ return vec_cnttz (a);
}
vector unsigned int
count_trailing_zeros_v4si_1u (vector unsigned int a)
{
- return vec_vctz (a);
-}
-
-vector unsigned int
-count_trailing_zeros_v4si_2u (vector unsigned int a)
-{
- return vec_vctzw (a);
+ return vec_cnttz (a);
}
vector long long
count_trailing_zeros_v2di_1s (vector long long a)
{
- return vec_vctz (a);
-}
-
-vector long long
-count_trailing_zeros_v2di_2s (vector long long a)
-{
- return vec_vctzd (a);
+ return vec_cnttz (a);
}
vector unsigned long long
count_trailing_zeros_v2di_1u (vector unsigned long long a)
{
- return vec_vctz (a);
-}
-
-vector unsigned long long
-count_trailing_zeros_v2di_2u (vector unsigned long long a)
-{
- return vec_vctzd (a);
+ return vec_cnttz (a);
}
/* { dg-final { scan-assembler "vctzb" } } */
^ permalink raw reply [flat|nested] 29+ messages in thread
* [gcc(refs/users/wschmidt/heads/builtins4)] rs6000: More bug fixes
@ 2021-01-13 14:58 William Schmidt
0 siblings, 0 replies; 29+ messages in thread
From: William Schmidt @ 2021-01-13 14:58 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:c960c4d15be4a8bb91185c562eb97d23d08d34e2
commit c960c4d15be4a8bb91185c562eb97d23d08d34e2
Author: Bill Schmidt <wschmidt@linux.ibm.com>
Date: Wed Jan 13 08:58:23 2021 -0600
rs6000: More bug fixes
2021-01-13 Bill Schmidt <wschmidt@linux.ibm.com>
gcc/
* config/rs6000/rs6000-builtin-new.def: Assorted fixes.
* config/rs6000/rs6000-c.c
(altivec_resolve_new_overloaded_builtin): Remove incorrect
gcc_assert.
* config/rs6000/rs6000-call.c (rs6000_init_builtins): Fix
initialization of ptr_intTI_type_node and ptr_uintTI_type_node.
* config/rs6000/rs6000-gen-builtins.c (typeinfo): Remove isopaque.
(match_type): Remove vop handling.
(construct_fntype_id): Remove isopaque handling.
(parse_ovld_entry): Commentary update.
* config/rs6000/rs6000-overload.def: Assorted fixes.
gcc/testsuite/
* gcc.dg/vmx/ops.c: Remove deprecated calls.
* gcc.target/powerpc/altivec-7.c: Likewise.
* gcc.target/powerpc/bfp/scalar-test-neg-2.c: Adjust.
* gcc.target/powerpc/bfp/scalar-test-neg-3.c: Adjust.
* gcc.target/powerpc/bfp/scalar-test-neg-5.c: Adjust.
* gcc.target/powerpc/builtins-3-p9-runnable.c: Adjust.
Diff:
---
gcc/config/rs6000/rs6000-builtin-new.def | 173 ++++++++++-----------
gcc/config/rs6000/rs6000-c.c | 1 -
gcc/config/rs6000/rs6000-call.c | 5 +-
gcc/config/rs6000/rs6000-gen-builtins.c | 49 ++----
gcc/config/rs6000/rs6000-overload.def | 47 +++---
gcc/testsuite/gcc.dg/vmx/ops.c | 86 ----------
gcc/testsuite/gcc.target/powerpc/altivec-7.c | 29 ++--
.../gcc.target/powerpc/bfp/scalar-test-neg-2.c | 2 +-
.../gcc.target/powerpc/bfp/scalar-test-neg-3.c | 2 +-
.../gcc.target/powerpc/bfp/scalar-test-neg-5.c | 2 +-
.../gcc.target/powerpc/builtins-3-p9-runnable.c | 8 +-
11 files changed, 139 insertions(+), 265 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-builtin-new.def b/gcc/config/rs6000/rs6000-builtin-new.def
index 6fa121bb38d..68d1a7d361a 100644
--- a/gcc/config/rs6000/rs6000-builtin-new.def
+++ b/gcc/config/rs6000/rs6000-builtin-new.def
@@ -81,7 +81,6 @@
; vp vector pixel
; vf vector float
; vd vector double
-; vop opaque vector (matches all vectors)
;
; For simplicity, We don't support "short int" and "long long int".
; We don't currently support a <basetype> of "bool", "long double",
@@ -127,30 +126,20 @@
;
; It is important to note that each entry's <bif-name> must be
; unique. The code generated from this file will call def_builtin
-; for each entry, and this can only happen once per name. This
-; means that in some cases we currently retain some tricks from
-; the old builtin support to aid with overloading. This
-; unfortunately seems to be necessary for backward compatibility.
+; for each entry, and this can only happen once per name.
;
-; The two tricks at our disposal are the void pointer and the "vop"
-; vector type. We use void pointers anywhere that pointer types
-; are accepted (primarily for vector load/store built-ins). In
-; practice this means that we accept pointers to anything, not
-; just to the types that we intend. We use the "vop" vector type
-; anytime that a built-in must accept vector types that have
-; different modes. This is an opaque type that will match any
-; vector type, which may mean matching vector types that we don't
-; intend.
+; The type signature for the builtin must match the modes of the RTL
+; pattern <bif-pattern>. When a builtin is used only as a basis for
+; overloading, you can use an arbitrary type for each mode (for example,
+; for V8HImode, you could use vp, vss, vus, or vbs). The overloading
+; machinery takes care of adding appropriate casts between vectors to
+; satisfy impedance matching. The overloaded prototypes are the ones
+; that must match what users expect. Thus you will often have a small
+; number of entries in this file that correspond to a much greater
+; number of entries in rs6000-overload.def.
;
-; We can improve on "vop" when a vector argument or return type is
-; limited to one mode. For example, "vsll" and "vull" both map to
-; V2DImode. In this case, we can arbitrarily pick one of the
-; acceptable types to use in the prototype. The signature used by
-; def_builtin is based on modes, not types, so this works well.
-; Only use "vop" when there is no alternative. When there is a
-; choice, best practice is to use the signed type ("vsll" in the
-; example above) unless the choices are unsigned and bool, in
-; which case the unsigned type should be used.
+; However, builtins in this file that are expected to be directly called
+; by users must have one version for each expected type combination.
;
; Eventually we want to automatically generate built-in documentation
; from the entries in this file. Documenting of built-ins with more
@@ -354,12 +343,24 @@
vuc __builtin_altivec_mask_for_load (const void *);
MASK_FOR_LOAD altivec_lvsr_direct {ldstmask}
- vus __builtin_altivec_mfvscr ();
+ vss __builtin_altivec_mfvscr ();
MFVSCR altivec_mfvscr {}
- void __builtin_altivec_mtvscr (vop);
+ void __builtin_altivec_mtvscr (vsi);
MTVSCR altivec_mtvscr {}
+ const vsll __builtin_altivec_vmulesw (vsi, vsi);
+ VMULESW vec_widen_smult_even_v4si {}
+
+ const vull __builtin_altivec_vmuleuw (vui, vui);
+ VMULEUW vec_widen_umult_even_v4si {}
+
+ const vsll __builtin_altivec_vmulosw (vsi, vsi);
+ VMULOSW vec_widen_smult_odd_v4si {}
+
+ const vull __builtin_altivec_vmulouw (vui, vui);
+ VMULOUW vec_widen_umult_odd_v4si {}
+
const vsc __builtin_altivec_nabs_v16qi (vsc);
NABS_V16QI nabsv16qi2 {}
@@ -441,7 +442,7 @@
const vus __builtin_altivec_vadduhs (vus, vus);
VADDUHS altivec_vadduhs {}
- const vui __builtin_altivec_vadduwm (vui, vui);
+ const vsi __builtin_altivec_vadduwm (vsi, vsi);
VADDUWM addv4si3 {}
const vui __builtin_altivec_vadduws (vui, vui);
@@ -528,19 +529,19 @@
const vsc __builtin_altivec_vcmpequb (vuc, vuc);
VCMPEQUB vector_eqv16qi {}
- const int __builtin_altivec_vcmpequb_p (int, vuc, vuc);
+ const int __builtin_altivec_vcmpequb_p (int, vsc, vsc);
VCMPEQUB_P vector_eq_v16qi_p {pred}
const vss __builtin_altivec_vcmpequh (vus, vus);
VCMPEQUH vector_eqv8hi {}
- const int __builtin_altivec_vcmpequh_p (int, vus, vus);
+ const int __builtin_altivec_vcmpequh_p (int, vss, vss);
VCMPEQUH_P vector_eq_v8hi_p {pred}
const vsi __builtin_altivec_vcmpequw (vui, vui);
VCMPEQUW vector_eqv4si {}
- const int __builtin_altivec_vcmpequw_p (int, vui, vui);
+ const int __builtin_altivec_vcmpequw_p (int, vsi, vsi);
VCMPEQUW_P vector_eq_v4si_p {pred}
const vf __builtin_altivec_vcmpgefp (vf, vf);
@@ -576,19 +577,19 @@
const vsc __builtin_altivec_vcmpgtub (vuc, vuc);
VCMPGTUB vector_gtuv16qi {}
- const int __builtin_altivec_vcmpgtub_p (int, vuc, vuc);
+ const int __builtin_altivec_vcmpgtub_p (int, vsc, vsc);
VCMPGTUB_P vector_gtu_v16qi_p {pred}
const vss __builtin_altivec_vcmpgtuh (vus, vus);
VCMPGTUH vector_gtuv8hi {}
- const int __builtin_altivec_vcmpgtuh_p (int, vus, vus);
+ const int __builtin_altivec_vcmpgtuh_p (int, vss, vss);
VCMPGTUH_P vector_gtu_v8hi_p {pred}
const vsi __builtin_altivec_vcmpgtuw (vui, vui);
VCMPGTUW vector_gtuv4si {}
- const int __builtin_altivec_vcmpgtuw_p (int, vui, vui);
+ const int __builtin_altivec_vcmpgtuw_p (int, vsi, vsi);
VCMPGTUW_P vector_gtu_v4si_p {pred}
const vsi __builtin_altivec_vctsxs (vf, const int<5>);
@@ -873,7 +874,7 @@
const vuq __builtin_altivec_vsel_1ti_uns (vuq, vuq, vuq);
VSEL_1TI_UNS vector_select_v1ti_uns {}
- const vf __builtin_altivec_vsel_4sf (vf, vf, vui);
+ const vf __builtin_altivec_vsel_4sf (vf, vf, vf);
VSEL_4SF vector_select_v4sf {}
const vsi __builtin_altivec_vsel_4si (vsi, vsi, vui);
@@ -888,7 +889,7 @@
const vus __builtin_altivec_vsel_8hi_uns (vus, vus, vus);
VSEL_8HI_UNS vector_select_v8hi_uns {}
- const vop __builtin_altivec_vsl (vop, vuc);
+ const vsi __builtin_altivec_vsl (vsi, vsi);
VSL altivec_vsl {}
const vsc __builtin_altivec_vslb (vsc, vuc);
@@ -909,7 +910,7 @@
const vss __builtin_altivec_vslh (vss, vus);
VSLH vashlv8hi3 {}
- const vop __builtin_altivec_vslo (vop, vuc);
+ const vsi __builtin_altivec_vslo (vsi, vsi);
VSLO altivec_vslo {}
const vsi __builtin_altivec_vslw (vsi, vui);
@@ -933,7 +934,7 @@
const vsi __builtin_altivec_vspltw (vsi, const int<2>);
VSPLTW altivec_vspltw {}
- const vop __builtin_altivec_vsr (vop, vop);
+ const vsi __builtin_altivec_vsr (vsi, vsi);
VSR altivec_vsr {}
const vsc __builtin_altivec_vsrab (vsc, vuc);
@@ -951,7 +952,7 @@
const vss __builtin_altivec_vsrh (vss, vus);
VSRH vlshrv8hi3 {}
- const vop __builtin_altivec_vsro (vop, vop);
+ const vsi __builtin_altivec_vsro (vsi, vsi);
VSRO altivec_vsro {}
const vsi __builtin_altivec_vsrw (vsi, vui);
@@ -1086,28 +1087,28 @@
; Cell builtins.
[cell]
- pure vop __builtin_altivec_lvlx (signed long long, const void *);
+ pure vuc __builtin_altivec_lvlx (signed long long, const void *);
LVLX altivec_lvlx {ldvec}
- pure vop __builtin_altivec_lvlxl (signed long long, const void *);
+ pure vuc __builtin_altivec_lvlxl (signed long long, const void *);
LVLXL altivec_lvlxl {ldvec}
- pure vop __builtin_altivec_lvrx (signed long long, const void *);
+ pure vuc __builtin_altivec_lvrx (signed long long, const void *);
LVRX altivec_lvrx {ldvec}
- pure vop __builtin_altivec_lvrxl (signed long long, const void *);
+ pure vuc __builtin_altivec_lvrxl (signed long long, const void *);
LVRXL altivec_lvrxl {ldvec}
- void __builtin_altivec_stvlx (vop, signed long long, void *);
+ void __builtin_altivec_stvlx (vuc, signed long long, void *);
STVLX altivec_stvlx {stvec}
- void __builtin_altivec_stvlxl (vop, signed long long, void *);
+ void __builtin_altivec_stvlxl (vuc, signed long long, void *);
STVLXL altivec_stvlxl {stvec}
- void __builtin_altivec_stvrx (vop, signed long long, void *);
+ void __builtin_altivec_stvrx (vuc, signed long long, void *);
STVRX altivec_stvrx {stvec}
- void __builtin_altivec_stvrxl (vop, signed long long, void *);
+ void __builtin_altivec_stvrxl (vuc, signed long long, void *);
STVRXL altivec_stvrxl {stvec}
@@ -1167,6 +1168,24 @@
const vull __builtin_altivec_vandc_v2di_uns (vull, vull);
VANDC_V2DI_UNS andcv2di3 {}
+ const vbll __builtin_altivec_vcmpequd (vull, vull);
+ VCMPEQUD vector_eqv2di {}
+
+ const int __builtin_altivec_vcmpequd_p (int, vsll, vsll);
+ VCMPEQUD_P vector_eq_v2di_p {pred}
+
+ const vsll __builtin_altivec_vcmpgtsd (vsll, vsll);
+ VCMPGTSD vector_gtv2di {}
+
+ const int __builtin_altivec_vcmpgtsd_p (int, vsll, vsll);
+ VCMPGTSD_P vector_gt_v2di_p {pred}
+
+ const vsll __builtin_altivec_vcmpgtud (vull, vull);
+ VCMPGTUD vector_gtuv2di {}
+
+ const int __builtin_altivec_vcmpgtud_p (int, vull, vull);
+ VCMPGTUD_P vector_gtu_v2di_p {pred}
+
const vd __builtin_altivec_vnor_v2df (vd, vd);
VNOR_V2DF norv2df3 {}
@@ -1717,11 +1736,11 @@
XVCVSXWDP vsx_xvcvsxwdp {}
; Need to pick one or the other here!! ####
-; Second one is used in the overload table (old and new) for VEC_FLOAT.
-; const vf __builtin_vsx_xvcvsxwsp (vsi);
-; XVCVSXWSP vsx_floatv4siv4sf2 {}
+; The first is needed to make vec_float work correctly.
const vf __builtin_vsx_xvcvsxwsp (vsi);
- XVCVSXWSP_V4SF vsx_xvcvsxwdp {}
+ XVCVSXWSP vsx_floatv4siv4sf2 {}
+; const vf __builtin_vsx_xvcvsxwsp (vsi);
+; XVCVSXWSP_V4SF vsx_xvcvsxwdp {}
const vd __builtin_vsx_xvcvuxddp (vull);
XVCVUXDDP vsx_floatunsv2div2df2 {}
@@ -1740,11 +1759,11 @@
XVCVUXWDP vsx_xvcvuxwdp {}
; Need to pick one or the other here!! ####
-; Second one is used in the overload table (old and new) for VEC_FLOAT.
-; const vf __builtin_vsx_xvcvuxwsp (vui);
-; XVCVUXWSP vsx_floatunsv4siv4sf2 {}
+; The first is needed to make vec_float work correctly.
const vf __builtin_vsx_xvcvuxwsp (vui);
- XVCVUXWSP_V4SF vsx_xvcvuxwsp {}
+ XVCVUXWSP vsx_floatunsv4siv4sf2 {}
+; const vf __builtin_vsx_xvcvuxwsp (vui);
+; XVCVUXWSP_V4SF vsx_xvcvuxwsp {}
fpmath vd __builtin_vsx_xvdivdp (vd, vd);
XVDIVDP divv2df3 {}
@@ -2199,24 +2218,6 @@
const vuc __builtin_altivec_vbpermq2 (vuc, vuc);
VBPERMQ2 altivec_vbpermq2 {}
- const vbll __builtin_altivec_vcmpequd (vull, vull);
- VCMPEQUD vector_eqv2di {}
-
- const int __builtin_altivec_vcmpequd_p (int, vsll, vsll);
- VCMPEQUD_P vector_eq_v2di_p {pred}
-
- const vsll __builtin_altivec_vcmpgtsd (vsll, vsll);
- VCMPGTSD vector_gtv2di {}
-
- const int __builtin_altivec_vcmpgtsd_p (int, vsll, vsll);
- VCMPGTSD_P vector_gt_v2di_p {pred}
-
- const vsll __builtin_altivec_vcmpgtud (vull, vull);
- VCMPGTUD vector_gtuv2di {}
-
- const int __builtin_altivec_vcmpgtud_p (int, vull, vull);
- VCMPGTUD_P vector_gtu_v2di_p {pred}
-
const vsll __builtin_altivec_vmaxsd (vsll, vsll);
VMAXSD smaxv2di3 {}
@@ -2253,18 +2254,6 @@
const vsi __builtin_altivec_vmrgow_v4si (vsi, vsi);
VMRGOW_V4SI p8_vmrgow_v4si {}
- const vsll __builtin_altivec_vmulesw (vsi, vsi);
- VMULESW vec_widen_smult_even_v4si {}
-
- const vull __builtin_altivec_vmuleuw (vui, vui);
- VMULEUW vec_widen_umult_even_v4si {}
-
- const vsll __builtin_altivec_vmulosw (vsi, vsi);
- VMULOSW vec_widen_smult_odd_v4si {}
-
- const vull __builtin_altivec_vmulouw (vui, vui);
- VMULOUW vec_widen_umult_odd_v4si {}
-
const vsc __builtin_altivec_vpermxor (vsc, vsc, vsc);
VPERMXOR altivec_vpermxor {}
@@ -2296,13 +2285,13 @@
; const vull __builtin_altivec_vpmsumw (vui, vui);
; VPMSUMW crypto_vpmsumw {}
- const vsc __builtin_altivec_vpopcntb (vsc);
+ const vuc __builtin_altivec_vpopcntb (vsc);
VPOPCNTB popcountv16qi2 {}
- const vsll __builtin_altivec_vpopcntd (vsll);
+ const vull __builtin_altivec_vpopcntd (vsll);
VPOPCNTD popcountv2di2 {}
- const vss __builtin_altivec_vpopcnth (vss);
+ const vus __builtin_altivec_vpopcnth (vss);
VPOPCNTH popcountv8hi2 {}
const vuc __builtin_altivec_vpopcntub (vuc);
@@ -2317,7 +2306,7 @@
const vui __builtin_altivec_vpopcntuw (vui);
VPOPCNTUW popcountv4si2 {}
- const vsi __builtin_altivec_vpopcntw (vsi);
+ const vui __builtin_altivec_vpopcntw (vsi);
VPOPCNTW popcountv4si2 {}
const vsll __builtin_altivec_vrld (vsll, vull);
@@ -2716,10 +2705,10 @@
const vuc __builtin_vsx_insert4b (vsi, vuc, const int[0,12]);
INSERT4B insert4b {}
- const vd __builtin_vsx_insert_exp_dp (vop, vull);
+ const vd __builtin_vsx_insert_exp_dp (vd, vd);
VIEDP xviexpdp {}
- const vf __builtin_vsx_insert_exp_sp (vop, vui);
+ const vf __builtin_vsx_insert_exp_sp (vf, vf);
VIESP xviexpsp {}
const signed int __builtin_vsx_scalar_cmp_exp_dp_eq (double, double);
@@ -2833,13 +2822,13 @@
void __builtin_altivec_xst_len_r (vsc, void *, long long);
XST_LEN_R xst_len_r {}
- void __builtin_altivec_stxvl (vop, void *, long long);
+ void __builtin_altivec_stxvl (vuc, void *, long long);
STXVL stxvl {}
const signed int __builtin_scalar_byte_in_set (unsigned char, unsigned long long);
CMPEQB cmpeqb {}
- pure vop __builtin_vsx_lxvl (const void *, unsigned long long);
+ pure vuc __builtin_vsx_lxvl (const void *, unsigned long long);
LXVL lxvl {}
const unsigned int __builtin_vsx_scalar_extract_exp (double);
@@ -3374,7 +3363,7 @@
const vus __builtin_vsx_xxblend_v8hi (vus, vus, vus);
VXXBLEND_V8HI xxblend_v8hi {}
- const vop __builtin_vsx_xxeval (vop, vop, vop, const int <8>);
+ const vull __builtin_vsx_xxeval (vull, vull, vull, const int <8>);
XXEVAL xxeval {}
const vuc __builtin_vsx_xxgenpcvm_v16qi (vuc, const int <2>);
diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c
index 1de614ba2b3..4e535e535ac 100644
--- a/gcc/config/rs6000/rs6000-c.c
+++ b/gcc/config/rs6000/rs6000-c.c
@@ -2947,7 +2947,6 @@ altivec_resolve_new_overloaded_builtin (location_t loc, tree fndecl,
break;
}
}
- gcc_assert (unsupported_builtin);
}
if (unsupported_builtin)
diff --git a/gcc/config/rs6000/rs6000-call.c b/gcc/config/rs6000/rs6000-call.c
index c96410b411b..fde516ab7cb 100644
--- a/gcc/config/rs6000/rs6000-call.c
+++ b/gcc/config/rs6000/rs6000-call.c
@@ -15624,6 +15624,7 @@ rs6000_init_builtins (void)
= build_pointer_type (build_qualified_type (unsigned_V4SI_type_node,
TYPE_QUAL_CONST));
+ /* #### Should just always be long long??? */
unsigned_V2DI_type_node = rs6000_vector_type (TARGET_POWERPC64
? "__vector unsigned long"
: "__vector unsigned long long",
@@ -15711,10 +15712,10 @@ rs6000_init_builtins (void)
= build_pointer_type (build_qualified_type (uintDI_type_internal_node,
TYPE_QUAL_CONST));
ptr_intTI_type_node
- = build_pointer_type (build_qualified_type (intDI_type_internal_node,
+ = build_pointer_type (build_qualified_type (intTI_type_internal_node,
TYPE_QUAL_CONST));
ptr_uintTI_type_node
- = build_pointer_type (build_qualified_type (uintDI_type_internal_node,
+ = build_pointer_type (build_qualified_type (uintTI_type_internal_node,
TYPE_QUAL_CONST));
ptr_long_integer_type_node
= build_pointer_type
diff --git a/gcc/config/rs6000/rs6000-gen-builtins.c b/gcc/config/rs6000/rs6000-gen-builtins.c
index 6405b0f7a56..8f129f47d8c 100644
--- a/gcc/config/rs6000/rs6000-gen-builtins.c
+++ b/gcc/config/rs6000/rs6000-gen-builtins.c
@@ -317,7 +317,6 @@ struct typeinfo {
char isbool;
char ispixel;
char ispointer;
- char isopaque;
basetype base;
restriction restr;
int val1;
@@ -474,7 +473,6 @@ static typemap type_map[TYPE_MAP_SIZE] =
{ "if", "ibm128_float" },
{ "ld", "long_double" },
{ "lg", "long_integer" },
- { "opaque", "opaque_V4SI" },
{ "pbv16qi", "ptr_bool_V16QI" },
{ "pbv2di", "ptr_bool_V2DI" },
{ "pbv4si", "ptr_bool_V4SI" },
@@ -972,7 +970,6 @@ match_type (typeinfo *typedata, int voidok)
vd vector double
v256 __vector_pair
v512 __vector_quad
- vop opaque vector (matches all vectors)
For simplicity, We don't support "short int" and "long long int".
We don't support a <basetype> of "bool", "long double", or "_Float16",
@@ -1156,11 +1153,6 @@ match_type (typeinfo *typedata, int voidok)
handle_pointer (typedata);
return 1;
}
- else if (!strcmp (token, "vop"))
- {
- typedata->isopaque = 1;
- return 1;
- }
else if (!strcmp (token, "signed"))
typedata->issigned = 1;
else if (!strcmp (token, "unsigned"))
@@ -1549,20 +1541,12 @@ construct_fntype_id (prototype *protoptr)
buf[bufi++] = 'v';
else
{
- if (protoptr->rettype.isopaque)
- {
- memcpy (&buf[bufi], "opaque", 6);
- bufi += 6;
- }
+ if (protoptr->rettype.isunsigned)
+ buf[bufi++] = 'u';
+ if (protoptr->rettype.isvector)
+ complete_vector_type (&protoptr->rettype, buf, &bufi);
else
- {
- if (protoptr->rettype.isunsigned)
- buf[bufi++] = 'u';
- if (protoptr->rettype.isvector)
- complete_vector_type (&protoptr->rettype, buf, &bufi);
- else
- complete_base_type (&protoptr->rettype, buf, &bufi);
- }
+ complete_base_type (&protoptr->rettype, buf, &bufi);
}
memcpy (&buf[bufi], "_ftype", 6);
@@ -1608,21 +1592,13 @@ construct_fntype_id (prototype *protoptr)
else
buf[bufi++] = 'p';
}
- if (argptr->info.isopaque)
- {
- assert (!argptr->info.ispointer);
- memcpy (&buf[bufi], "opaque", 6);
- bufi += 6;
- }
+
+ if (argptr->info.isunsigned)
+ buf[bufi++] = 'u';
+ if (argptr->info.isvector)
+ complete_vector_type (&argptr->info, buf, &bufi);
else
- {
- if (argptr->info.isunsigned)
- buf[bufi++] = 'u';
- if (argptr->info.isvector)
- complete_vector_type (&argptr->info, buf, &bufi);
- else
- complete_base_type (&argptr->info, buf, &bufi);
- }
+ complete_base_type (&argptr->info, buf, &bufi);
}
assert (!argptr);
}
@@ -1965,8 +1941,7 @@ parse_ovld_entry ()
/* Check for an optional overload id. Usually we use the builtin
function id for that purpose, but sometimes we need multiple
- overload entries for the same builtin id when we use opaque
- vector parameter and return types, and it needs to be unique. */
+ overload entries for the same builtin id, and it needs to be unique. */
consume_whitespace ();
if (linebuf[pos] != '\n')
{
diff --git a/gcc/config/rs6000/rs6000-overload.def b/gcc/config/rs6000/rs6000-overload.def
index 66f5836c444..ec884b63388 100644
--- a/gcc/config/rs6000/rs6000-overload.def
+++ b/gcc/config/rs6000/rs6000-overload.def
@@ -257,7 +257,7 @@
VADDUWM VADDUWM_VSI_VBI
vui __builtin_vec_add (vbi, vui);
VADDUWM VADDUWM_VBI_VUI
- vui __builtin_vec_add (vbi, vui);
+ vui __builtin_vec_add (vui, vbi);
VADDUWM VADDUWM_VUI_VBI
vsll __builtin_vec_add (vbll, vsll);
VADDUDM VADDUDM_VBLL_VSLL
@@ -382,7 +382,7 @@
VAND_V16QI_UNS VAND_VBC_VUC
vss __builtin_vec_and (vss, vbs);
VAND_V8HI VAND_VSS_VBS
- vss __builtin_vec_and (vss, vbs);
+ vss __builtin_vec_and (vbs, vss);
VAND_V8HI VAND_VBS_VSS
vus __builtin_vec_and (vus, vbs);
VAND_V8HI_UNS VAND_VUS_VBS
@@ -1606,9 +1606,9 @@
[VEC_FLOAT, vec_float, __builtin_vec_float]
vf __builtin_vec_float (vsi);
- XVCVSXWSP_V4SF
+ XVCVSXWSP
vf __builtin_vec_float (vui);
- XVCVUXWSP_V4SF
+ XVCVUXWSP
[VEC_FLOAT2, vec_float2, __builtin_vec_float2]
vf __builtin_vec_float2 (vsll, vsll);
@@ -1634,9 +1634,10 @@
vf __builtin_vec_floato (vd);
FLOATO_V2DF
+; #### XVRSPIM{TARGET_VSX}; VRFIM
[VEC_FLOOR, vec_floor, __builtin_vec_floor]
vf __builtin_vec_floor (vf);
- XVRSPIM
+ VRFIM
vd __builtin_vec_floor (vd);
XVRDPIM
@@ -2118,7 +2119,7 @@
VMLADDUHM VMLADDUHM_VSSVUS
vss __builtin_vec_madd (vus, vss, vss);
VMLADDUHM VMLADDUHM_VUSVSS
- vus __builtin_vec_madd (vss, vus, vus);
+ vus __builtin_vec_madd (vus, vus, vus);
VMLADDUHM VMLADDUHM_VUS
vf __builtin_vec_madd (vf, vf, vf);
VMADDFP
@@ -2896,19 +2897,19 @@
VPMSUMD VPMSUMD_V
[VEC_POPCNT, vec_popcnt, __builtin_vec_vpopcnt, _ARCH_PWR8]
- vsc __builtin_vec_vpopcnt (vsc);
+ vuc __builtin_vec_vpopcnt (vsc);
VPOPCNTB
vuc __builtin_vec_vpopcnt (vuc);
VPOPCNTUB
- vss __builtin_vec_vpopcnt (vss);
+ vus __builtin_vec_vpopcnt (vss);
VPOPCNTH
vus __builtin_vec_vpopcnt (vus);
VPOPCNTUH
- vsi __builtin_vec_vpopcnt (vsi);
+ vui __builtin_vec_vpopcnt (vsi);
VPOPCNTW
vui __builtin_vec_vpopcnt (vui);
VPOPCNTUW
- vsll __builtin_vec_vpopcnt (vsll);
+ vull __builtin_vec_vpopcnt (vsll);
VPOPCNTD
vull __builtin_vec_vpopcnt (vull);
VPOPCNTUD
@@ -3082,9 +3083,10 @@
vull __builtin_vec_rlnm (vull, vull);
VRLDNM
+; #### XVRSPI{TARGET_VSX};VRFIN
[VEC_ROUND, vec_round, __builtin_vec_round]
vf __builtin_vec_round (vf);
- XVRSPI
+ VRFIN
vd __builtin_vec_round (vd);
XVRDPI
@@ -3193,11 +3195,11 @@
VEC_VSIGNED2_V2DF
[VEC_SIGNEDE, vec_signede, __builtin_vec_vsignede]
- vui __builtin_vec_vsignede (vd);
+ vsi __builtin_vec_vsignede (vd);
VEC_VSIGNEDE_V2DF
[VEC_SIGNEDO, vec_signedo, __builtin_vec_vsignedo]
- vui __builtin_vec_vsignedo (vd);
+ vsi __builtin_vec_vsignedo (vd);
VEC_VSIGNEDO_V2DF
[VEC_SL, vec_sl, __builtin_vec_sl]
@@ -3356,8 +3358,8 @@
VSL VSL_VBLL_VUC
vbll __builtin_vec_sll (vbll, vus);
VSL VSL_VBLL_VUS
- vbll __builtin_vec_sll (vbll, vui);
- VSL VSL_VBLL_VUI
+ vbll __builtin_vec_sll (vbll, vull);
+ VSL VSL_VBLL_VULL
[VEC_SLO, vec_slo, __builtin_vec_slo]
vsc __builtin_vec_slo (vsc, vsc);
@@ -3686,14 +3688,10 @@
STVX_V4SI STVX_VSI
void __builtin_vec_st (vsi, signed long long, signed int *);
STVX_V4SI STVX_SI
- void __builtin_vec_st (vsi, signed long long, signed long *);
- STVX_V4SI STVX_SL
void __builtin_vec_st (vui, signed long long, vui *);
STVX_V4SI STVX_VUI
void __builtin_vec_st (vui, signed long long, unsigned int *);
STVX_V4SI STVX_UI
- void __builtin_vec_st (vui, signed long long, unsigned long *);
- STVX_V4SI STVX_UL
void __builtin_vec_st (vbi, signed long long, vbi *);
STVX_V4SI STVX_VBI
void __builtin_vec_st (vbi, signed long long, signed int *);
@@ -4190,7 +4188,7 @@
[VEC_SUM4S, vec_sum4s, __builtin_vec_sum4s]
vui __builtin_vec_sum4s (vuc, vui);
VSUM4UBS
- vsi __builtin_vec_sum4s (vsc, vui);
+ vsi __builtin_vec_sum4s (vsc, vsi);
VSUM4SBS
vsi __builtin_vec_sum4s (vss, vsi);
VSUM4SHS
@@ -4219,9 +4217,10 @@
signed int __builtin_vec_xvtlsbb_all_zeros (vuc);
XVTLSBB_ZEROS
+; #### XVRSPIZ{TARGET_VSX}; VRFIZ
[VEC_TRUNC, vec_trunc, __builtin_vec_trunc]
vf __builtin_vec_trunc (vf);
- XVRSPIZ
+ VRFIZ
vd __builtin_vec_trunc (vd);
XVRDPIZ
@@ -4286,13 +4285,13 @@
DOUBLEL_V4SF VUPKLF
[VEC_UNSIGNED, vec_unsigned, __builtin_vec_vunsigned]
- vsi __builtin_vec_vunsigned (vf);
+ vui __builtin_vec_vunsigned (vf);
VEC_VUNSIGNED_V4SF
- vsll __builtin_vec_vunsigned (vd);
+ vull __builtin_vec_vunsigned (vd);
VEC_VUNSIGNED_V2DF
[VEC_UNSIGNED2, vec_unsigned2, __builtin_vec_vunsigned2]
- vsi __builtin_vec_vunsigned2 (vd, vd);
+ vui __builtin_vec_vunsigned2 (vd, vd);
VEC_VUNSIGNED2_V2DF
[VEC_UNSIGNEDE, vec_unsignede, __builtin_vec_vunsignede]
diff --git a/gcc/testsuite/gcc.dg/vmx/ops.c b/gcc/testsuite/gcc.dg/vmx/ops.c
index 735710819f9..b8f80930078 100644
--- a/gcc/testsuite/gcc.dg/vmx/ops.c
+++ b/gcc/testsuite/gcc.dg/vmx/ops.c
@@ -317,8 +317,6 @@ void f2() {
*var_vec_b16++ = vec_cmpgt(var_vec_u16[0], var_vec_u16[1]);
*var_vec_b16++ = vec_ld(var_int[0], var_vec_b16_ptr[1]);
*var_vec_b16++ = vec_ldl(var_int[0], var_vec_b16_ptr[1]);
- *var_vec_b16++ = vec_lvx(var_int[0], var_vec_b16_ptr[1]);
- *var_vec_b16++ = vec_lvxl(var_int[0], var_vec_b16_ptr[1]);
*var_vec_b16++ = vec_mergeh(var_vec_b16[0], var_vec_b16[1]);
*var_vec_b16++ = vec_mergel(var_vec_b16[0], var_vec_b16[1]);
*var_vec_b16++ = vec_nor(var_vec_b16[0], var_vec_b16[1]);
@@ -357,8 +355,6 @@ void f3() {
*var_vec_b32++ = vec_cmpgt(var_vec_u32[0], var_vec_u32[1]);
*var_vec_b32++ = vec_ld(var_int[0], var_vec_b32_ptr[1]);
*var_vec_b32++ = vec_ldl(var_int[0], var_vec_b32_ptr[1]);
- *var_vec_b32++ = vec_lvx(var_int[0], var_vec_b32_ptr[1]);
- *var_vec_b32++ = vec_lvxl(var_int[0], var_vec_b32_ptr[1]);
*var_vec_b32++ = vec_mergeh(var_vec_b32[0], var_vec_b32[1]);
*var_vec_b32++ = vec_mergel(var_vec_b32[0], var_vec_b32[1]);
*var_vec_b32++ = vec_nor(var_vec_b32[0], var_vec_b32[1]);
@@ -389,8 +385,6 @@ void f4() {
*var_vec_b8++ = vec_cmpgt(var_vec_u8[0], var_vec_u8[1]);
*var_vec_b8++ = vec_ld(var_int[0], var_vec_b8_ptr[1]);
*var_vec_b8++ = vec_ldl(var_int[0], var_vec_b8_ptr[1]);
- *var_vec_b8++ = vec_lvx(var_int[0], var_vec_b8_ptr[1]);
- *var_vec_b8++ = vec_lvxl(var_int[0], var_vec_b8_ptr[1]);
}
void f5() {
*var_vec_b8++ = vec_mergeh(var_vec_b8[0], var_vec_b8[1]);
@@ -506,11 +500,6 @@ void f6() {
*var_vec_f32++ = vec_ldl(var_int[0], var_float_ptr[1]);
*var_vec_f32++ = vec_ldl(var_int[0], var_vec_f32_ptr[1]);
*var_vec_f32++ = vec_loge(var_vec_f32[0]);
- *var_vec_f32++ = vec_lvewx(var_int[0], var_float_ptr[1]);
- *var_vec_f32++ = vec_lvx(var_int[0], var_float_ptr[1]);
- *var_vec_f32++ = vec_lvx(var_int[0], var_vec_f32_ptr[1]);
- *var_vec_f32++ = vec_lvxl(var_int[0], var_float_ptr[1]);
- *var_vec_f32++ = vec_lvxl(var_int[0], var_vec_f32_ptr[1]);
*var_vec_f32++ = vec_madd(var_vec_f32[0], var_vec_f32[1], var_vec_f32[2]);
*var_vec_f32++ = vec_max(var_vec_f32[0], var_vec_f32[1]);
*var_vec_f32++ = vec_mergeh(var_vec_f32[0], var_vec_f32[1]);
@@ -562,8 +551,6 @@ void f9() {
*var_vec_f32++ = vec_xor(var_vec_f32[0], var_vec_f32[1]);
*var_vec_p16++ = vec_ld(var_int[0], var_vec_p16_ptr[1]);
*var_vec_p16++ = vec_ldl(var_int[0], var_vec_p16_ptr[1]);
- *var_vec_p16++ = vec_lvx(var_int[0], var_vec_p16_ptr[1]);
- *var_vec_p16++ = vec_lvxl(var_int[0], var_vec_p16_ptr[1]);
*var_vec_p16++ = vec_mergeh(var_vec_p16[0], var_vec_p16[1]);
*var_vec_p16++ = vec_mergel(var_vec_p16[0], var_vec_p16[1]);
*var_vec_p16++ = vec_packpx(var_vec_u32[0], var_vec_u32[1]);
@@ -622,11 +609,6 @@ void f10() {
*var_vec_s16++ = vec_lde(var_int[0], var_short_ptr[1]);
*var_vec_s16++ = vec_ldl(var_int[0], var_short_ptr[1]);
*var_vec_s16++ = vec_ldl(var_int[0], var_vec_s16_ptr[1]);
- *var_vec_s16++ = vec_lvehx(var_int[0], var_short_ptr[1]);
- *var_vec_s16++ = vec_lvx(var_int[0], var_short_ptr[1]);
- *var_vec_s16++ = vec_lvx(var_int[0], var_vec_s16_ptr[1]);
- *var_vec_s16++ = vec_lvxl(var_int[0], var_short_ptr[1]);
- *var_vec_s16++ = vec_lvxl(var_int[0], var_vec_s16_ptr[1]);
*var_vec_s16++ = vec_madds(var_vec_s16[0], var_vec_s16[1], var_vec_s16[2]);
*var_vec_s16++ = vec_max(var_vec_b16[0], var_vec_s16[1]);
*var_vec_s16++ = vec_max(var_vec_s16[0], var_vec_b16[1]);
@@ -787,11 +769,6 @@ void f13() {
*var_vec_s32++ = vec_lde(var_int[0], var_int_ptr[1]);
*var_vec_s32++ = vec_ldl(var_int[0], var_int_ptr[1]);
*var_vec_s32++ = vec_ldl(var_int[0], var_vec_s32_ptr[1]);
- *var_vec_s32++ = vec_lvewx(var_int[0], var_int_ptr[1]);
- *var_vec_s32++ = vec_lvx(var_int[0], var_int_ptr[1]);
- *var_vec_s32++ = vec_lvx(var_int[0], var_vec_s32_ptr[1]);
- *var_vec_s32++ = vec_lvxl(var_int[0], var_int_ptr[1]);
- *var_vec_s32++ = vec_lvxl(var_int[0], var_vec_s32_ptr[1]);
*var_vec_s32++ = vec_max(var_vec_b32[0], var_vec_s32[1]);
*var_vec_s32++ = vec_max(var_vec_s32[0], var_vec_b32[1]);
*var_vec_s32++ = vec_max(var_vec_s32[0], var_vec_s32[1]);
@@ -919,11 +896,6 @@ void f17() {
*var_vec_s8++ = vec_lde(var_int[0], var_signed_char_ptr[1]);
*var_vec_s8++ = vec_ldl(var_int[0], var_signed_char_ptr[1]);
*var_vec_s8++ = vec_ldl(var_int[0], var_vec_s8_ptr[1]);
- *var_vec_s8++ = vec_lvebx(var_int[0], var_signed_char_ptr[1]);
- *var_vec_s8++ = vec_lvx(var_int[0], var_signed_char_ptr[1]);
- *var_vec_s8++ = vec_lvx(var_int[0], var_vec_s8_ptr[1]);
- *var_vec_s8++ = vec_lvxl(var_int[0], var_signed_char_ptr[1]);
- *var_vec_s8++ = vec_lvxl(var_int[0], var_vec_s8_ptr[1]);
*var_vec_s8++ = vec_max(var_vec_b8[0], var_vec_s8[1]);
*var_vec_s8++ = vec_max(var_vec_s8[0], var_vec_b8[1]);
*var_vec_s8++ = vec_max(var_vec_s8[0], var_vec_s8[1]);
@@ -1050,11 +1022,6 @@ void f19() {
*var_vec_u16++ = vec_lde(var_int[0], var_unsigned_short_ptr[1]);
*var_vec_u16++ = vec_ldl(var_int[0], var_unsigned_short_ptr[1]);
*var_vec_u16++ = vec_ldl(var_int[0], var_vec_u16_ptr[1]);
- *var_vec_u16++ = vec_lvehx(var_int[0], var_unsigned_short_ptr[1]);
- *var_vec_u16++ = vec_lvx(var_int[0], var_unsigned_short_ptr[1]);
- *var_vec_u16++ = vec_lvx(var_int[0], var_vec_u16_ptr[1]);
- *var_vec_u16++ = vec_lvxl(var_int[0], var_unsigned_short_ptr[1]);
- *var_vec_u16++ = vec_lvxl(var_int[0], var_vec_u16_ptr[1]);
*var_vec_u16++ = vec_max(var_vec_b16[0], var_vec_u16[1]);
*var_vec_u16++ = vec_max(var_vec_u16[0], var_vec_b16[1]);
*var_vec_u16++ = vec_max(var_vec_u16[0], var_vec_u16[1]);
@@ -1213,11 +1180,6 @@ void f22() {
*var_vec_u32++ = vec_lde(var_int[0], var_unsigned_int_ptr[1]);
*var_vec_u32++ = vec_ldl(var_int[0], var_unsigned_int_ptr[1]);
*var_vec_u32++ = vec_ldl(var_int[0], var_vec_u32_ptr[1]);
- *var_vec_u32++ = vec_lvewx(var_int[0], var_unsigned_int_ptr[1]);
- *var_vec_u32++ = vec_lvx(var_int[0], var_unsigned_int_ptr[1]);
- *var_vec_u32++ = vec_lvx(var_int[0], var_vec_u32_ptr[1]);
- *var_vec_u32++ = vec_lvxl(var_int[0], var_unsigned_int_ptr[1]);
- *var_vec_u32++ = vec_lvxl(var_int[0], var_vec_u32_ptr[1]);
*var_vec_u32++ = vec_max(var_vec_b32[0], var_vec_u32[1]);
*var_vec_u32++ = vec_max(var_vec_u32[0], var_vec_b32[1]);
*var_vec_u32++ = vec_max(var_vec_u32[0], var_vec_u32[1]);
@@ -1341,7 +1303,6 @@ void f25() {
*var_vec_u8++ = vec_lde(var_int[0], var_unsigned_char_ptr[1]);
*var_vec_u8++ = vec_ldl(var_int[0], var_unsigned_char_ptr[1]);
*var_vec_u8++ = vec_ldl(var_int[0], var_vec_u8_ptr[1]);
- *var_vec_u8++ = vec_lvebx(var_int[0], var_unsigned_char_ptr[1]);
*var_vec_u8++ = vec_lvsl(var_int[0], var_float_ptr[1]);
*var_vec_u8++ = vec_lvsl(var_int[0], var_int_ptr[1]);
*var_vec_u8++ = vec_lvsl(var_int[0], var_short_ptr[1]);
@@ -1356,12 +1317,8 @@ void f25() {
*var_vec_u8++ = vec_lvsr(var_int[0], var_unsigned_char_ptr[1]);
*var_vec_u8++ = vec_lvsr(var_int[0], var_unsigned_int_ptr[1]);
*var_vec_u8++ = vec_lvsr(var_int[0], var_unsigned_short_ptr[1]);
- *var_vec_u8++ = vec_lvx(var_int[0], var_unsigned_char_ptr[1]);
- *var_vec_u8++ = vec_lvx(var_int[0], var_vec_u8_ptr[1]);
}
void f26() {
- *var_vec_u8++ = vec_lvxl(var_int[0], var_unsigned_char_ptr[1]);
- *var_vec_u8++ = vec_lvxl(var_int[0], var_vec_u8_ptr[1]);
*var_vec_u8++ = vec_max(var_vec_b8[0], var_vec_u8[1]);
*var_vec_u8++ = vec_max(var_vec_u8[0], var_vec_b8[1]);
*var_vec_u8++ = vec_max(var_vec_u8[0], var_vec_u8[1]);
@@ -2353,47 +2310,4 @@ void f37() {
vec_stl(var_vec_u32[0], var_int[1], var_vec_u32_ptr[2]);
vec_stl(var_vec_u8[0], var_int[1], var_unsigned_char_ptr[2]);
vec_stl(var_vec_u8[0], var_int[1], var_vec_u8_ptr[2]);
- vec_stvebx(var_vec_s8[0], var_int[1], var_signed_char_ptr[2]);
- vec_stvebx(var_vec_u8[0], var_int[1], var_unsigned_char_ptr[2]);
- vec_stvehx(var_vec_s16[0], var_int[1], var_short_ptr[2]);
- vec_stvehx(var_vec_u16[0], var_int[1], var_unsigned_short_ptr[2]);
- vec_stvewx(var_vec_f32[0], var_int[1], var_float_ptr[2]);
- vec_stvewx(var_vec_s32[0], var_int[1], var_int_ptr[2]);
- vec_stvewx(var_vec_u32[0], var_int[1], var_unsigned_int_ptr[2]);
- vec_stvx(var_vec_b16[0], var_int[1], var_vec_b16_ptr[2]);
- vec_stvx(var_vec_b32[0], var_int[1], var_vec_b32_ptr[2]);
- vec_stvx(var_vec_b8[0], var_int[1], var_vec_b8_ptr[2]);
- vec_stvx(var_vec_f32[0], var_int[1], var_float_ptr[2]);
- vec_stvx(var_vec_f32[0], var_int[1], var_vec_f32_ptr[2]);
- vec_stvx(var_vec_p16[0], var_int[1], var_vec_p16_ptr[2]);
- vec_stvx(var_vec_s16[0], var_int[1], var_short_ptr[2]);
- vec_stvx(var_vec_s16[0], var_int[1], var_vec_s16_ptr[2]);
- vec_stvx(var_vec_s32[0], var_int[1], var_int_ptr[2]);
- vec_stvx(var_vec_s32[0], var_int[1], var_vec_s32_ptr[2]);
- vec_stvx(var_vec_s8[0], var_int[1], var_signed_char_ptr[2]);
- vec_stvx(var_vec_s8[0], var_int[1], var_vec_s8_ptr[2]);
- vec_stvx(var_vec_u16[0], var_int[1], var_unsigned_short_ptr[2]);
- vec_stvx(var_vec_u16[0], var_int[1], var_vec_u16_ptr[2]);
- vec_stvx(var_vec_u32[0], var_int[1], var_unsigned_int_ptr[2]);
- vec_stvx(var_vec_u32[0], var_int[1], var_vec_u32_ptr[2]);
- vec_stvx(var_vec_u8[0], var_int[1], var_unsigned_char_ptr[2]);
- vec_stvx(var_vec_u8[0], var_int[1], var_vec_u8_ptr[2]);
- vec_stvxl(var_vec_b16[0], var_int[1], var_vec_b16_ptr[2]);
- vec_stvxl(var_vec_b32[0], var_int[1], var_vec_b32_ptr[2]);
- vec_stvxl(var_vec_b8[0], var_int[1], var_vec_b8_ptr[2]);
- vec_stvxl(var_vec_f32[0], var_int[1], var_float_ptr[2]);
- vec_stvxl(var_vec_f32[0], var_int[1], var_vec_f32_ptr[2]);
- vec_stvxl(var_vec_p16[0], var_int[1], var_vec_p16_ptr[2]);
- vec_stvxl(var_vec_s16[0], var_int[1], var_short_ptr[2]);
- vec_stvxl(var_vec_s16[0], var_int[1], var_vec_s16_ptr[2]);
- vec_stvxl(var_vec_s32[0], var_int[1], var_int_ptr[2]);
- vec_stvxl(var_vec_s32[0], var_int[1], var_vec_s32_ptr[2]);
- vec_stvxl(var_vec_s8[0], var_int[1], var_signed_char_ptr[2]);
- vec_stvxl(var_vec_s8[0], var_int[1], var_vec_s8_ptr[2]);
- vec_stvxl(var_vec_u16[0], var_int[1], var_unsigned_short_ptr[2]);
- vec_stvxl(var_vec_u16[0], var_int[1], var_vec_u16_ptr[2]);
- vec_stvxl(var_vec_u32[0], var_int[1], var_unsigned_int_ptr[2]);
- vec_stvxl(var_vec_u32[0], var_int[1], var_vec_u32_ptr[2]);
- vec_stvxl(var_vec_u8[0], var_int[1], var_unsigned_char_ptr[2]);
- vec_stvxl(var_vec_u8[0], var_int[1], var_vec_u8_ptr[2]);
}
diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-7.c b/gcc/testsuite/gcc.target/powerpc/altivec-7.c
index 42c04a1ed79..0cef426fcd9 100644
--- a/gcc/testsuite/gcc.target/powerpc/altivec-7.c
+++ b/gcc/testsuite/gcc.target/powerpc/altivec-7.c
@@ -26,25 +26,23 @@ int main ()
{
*vecfloat++ = vec_andc((vector bool int)vecint[0], vecfloat[1]);
*vecfloat++ = vec_andc(vecfloat[0], (vector bool int)vecint[1]);
- *vecfloat++ = vec_vxor((vector bool int)vecint[0], vecfloat[1]);
- *vecfloat++ = vec_vxor(vecfloat[0], (vector bool int)vecint[1]);
+ *vecfloat++ = vec_xor((vector bool int)vecint[0], vecfloat[1]);
+ *vecfloat++ = vec_xor(vecfloat[0], (vector bool int)vecint[1]);
*varpixel++ = vec_packpx(vecuint[0], vecuint[1]);
- *varpixel++ = vec_vpkpx(vecuint[0], vecuint[1]);
- *vecshort++ = vec_vmulesb(vecchar[0], vecchar[1]);
- *vecshort++ = vec_vmulosb(vecchar[0], vecchar[1]);
+ *vecshort++ = vec_mule(vecchar[0], vecchar[1]);
+ *vecshort++ = vec_mulo(vecchar[0], vecchar[1]);
*vecint++ = vec_ld(var_int[0], intp[1]);
*vecint++ = vec_lde(var_int[0], intp[1]);
*vecint++ = vec_ldl(var_int[0], intp[1]);
- *vecint++ = vec_lvewx(var_int[0], intp[1]);
*vecint++ = vec_unpackh(vecshort[0]);
*vecint++ = vec_unpackl(vecshort[0]);
*vecushort++ = vec_andc((vector bool short)vecshort[0], vecushort[1]);
*vecushort++ = vec_andc(vecushort[0], (vector bool short)vecshort[1]);
- *vecushort++ = vec_vxor((vector bool short)vecshort[0], vecushort[1]);
- *vecushort++ = vec_vxor(vecushort[0], (vector bool short)vecshort[1]);
+ *vecushort++ = vec_xor((vector bool short)vecshort[0], vecushort[1]);
+ *vecushort++ = vec_xor(vecushort[0], (vector bool short)vecshort[1]);
*vecuint++ = vec_ld(var_int[0], uintp[1]);
*vecuint++ = vec_lvx(var_int[0], uintp[1]);
- *vecuint++ = vec_vmsumubm(vecuchar[0], vecuchar[1], vecuint[2]);
+ *vecuint++ = vec_msum(vecuchar[0], vecuchar[1], vecuint[2]);
*vecuchar++ = vec_xor(vecuchar[0], (vector unsigned char)vecchar[1]);
*vecubi++ = vec_unpackh(vecubsi[0]);
@@ -62,11 +60,10 @@ int main ()
/* Expected results:
vec_packpx vpkpx
- vec_vmulosb vmulesb
+ vec_mulo vmulesb
vec_ld lxv2x
vec_lde lvewx
vec_ldl lxvl
- vec_lvewx lvewx
vec_unpackh vupklsh
vec_unpackh vupklpx
vec_unpackh vupklsb
@@ -75,10 +72,10 @@ int main ()
vec_unpackl vupkhsb
vec_andc xxlnor (vnor AIX)
xxland (vand AIX)
- vec_vxor xxlxor
- vec_vmsumubm vmsumubm
- vec_vmulesb vmulosb
- vec_vmulosb vmulesb
+ vec_xor xxlxor
+ vec_msum vmsumubm
+ vec_mule vmulosb
+ vec_mulo vmulesb
vec_ld lvx
*/
@@ -89,7 +86,7 @@ int main ()
/* { dg-final { scan-assembler-times {\mlxv} 0 { target { ! powerpc_vsx } } } } */
/* { dg-final { scan-assembler-times {\mlvx\M} 0 { target powerpc_vsx } } } */
/* { dg-final { scan-assembler-times {\mlxv} 42 { target powerpc_vsx } } } */
-/* { dg-final { scan-assembler-times "lvewx" 2 } } */
+/* { dg-final { scan-assembler-times "lvewx" 1 } } */
/* { dg-final { scan-assembler-times "lvxl" 1 } } */
/* { dg-final { scan-assembler-times "vupklsh" 2 } } */
/* { dg-final { scan-assembler-times "vupkhsh" 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-2.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-2.c
index 7a1e8e8bd30..46d743a899b 100644
--- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-2.c
+++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-2.c
@@ -10,5 +10,5 @@ test_neg (float *p)
{
float source = *p;
- return __builtin_vec_scalar_test_neg (source); /* { dg-error "'__builtin_vsx_scalar_test_neg' requires" } */
+ return __builtin_vec_scalar_test_neg (source); /* { dg-error "'__builtin_vsx_scalar_test_neg_sp' requires" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-3.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-3.c
index c9b90927693..bfc892b116e 100644
--- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-3.c
@@ -10,5 +10,5 @@ test_neg (double *p)
{
double source = *p;
- return __builtin_vec_scalar_test_neg (source); /* { dg-error "'__builtin_vsx_scalar_test_neg' requires" } */
+ return __builtin_vec_scalar_test_neg (source); /* { dg-error "'__builtin_vsx_scalar_test_neg_dp' requires" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-5.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-5.c
index e70eb2d46f8..8c55c1cfb5c 100644
--- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-5.c
+++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-5.c
@@ -10,5 +10,5 @@ test_neg (__ieee128 *p)
{
__ieee128 source = *p;
- return __builtin_vec_scalar_test_neg (source); /* { dg-error "'__builtin_vsx_scalar_test_neg' requires" } */
+ return __builtin_vec_scalar_test_neg (source); /* { dg-error "'__builtin_vsx_scalar_test_neg_qp' requires" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-3-p9-runnable.c b/gcc/testsuite/gcc.target/powerpc/builtins-3-p9-runnable.c
index 44c0397c49a..e023076bac7 100644
--- a/gcc/testsuite/gcc.target/powerpc/builtins-3-p9-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/builtins-3-p9-runnable.c
@@ -73,10 +73,10 @@ int main() {
abort();
}
vfexpt = (vector float){1.0, -2.0, 0.0, 8.5};
- vfr = vec_extract_fp_from_shorth(vusha);
+ vfr = vec_extract_fp32_from_shorth(vusha);
#ifdef DEBUG
- printf ("vec_extract_fp_from_shorth\n");
+ printf ("vec_extract_fp32_from_shorth\n");
for (i=0; i<4; i++)
printf("result[%d] = %f; expected[%d] = %f\n",
i, vfr[i], i, vfexpt[i]);
@@ -88,10 +88,10 @@ int main() {
}
vfexpt = (vector float){1.5, 0.5, 1.25, -0.25};
- vfr = vec_extract_fp_from_shortl(vusha);
+ vfr = vec_extract_fp32_from_shortl(vusha);
#ifdef DEBUG
- printf ("\nvec_extract_fp_from_shortl\n");
+ printf ("\nvec_extract_fp32_from_shortl\n");
for (i=0; i<4; i++)
printf("result[%d] = %f; expected[%d] = %f\n",
i, vfr[i], i, vfexpt[i]);
^ permalink raw reply [flat|nested] 29+ messages in thread
* [gcc(refs/users/wschmidt/heads/builtins4)] rs6000: More bug fixes
@ 2021-01-08 23:09 William Schmidt
0 siblings, 0 replies; 29+ messages in thread
From: William Schmidt @ 2021-01-08 23:09 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:4b6d9a8f037aeb19064bb3befb297cb76d20a346
commit 4b6d9a8f037aeb19064bb3befb297cb76d20a346
Author: Bill Schmidt <wschmidt@linux.ibm.com>
Date: Fri Jan 8 17:08:42 2021 -0600
rs6000: More bug fixes
2021-01-08 Bill Schmidt <wschmidt@linux.ibm.com>
gcc/
* config/rs6000/rs6000-builtin-new.def (__builtin_altivec_vsr):
Fix argument types.
(__builtin_altivec_vsro): Likewise.
gcc/testsuite/
* gcc.target/powerpc/dfp/dtstsfi-11.c: Fix expected error message.
* gcc.target/powerpc/dfp/dtstsfi-16.c: Likewise.
* gcc.target/powerpc/dfp/dtstsfi-51.c: Likewise.
* gcc.target/powerpc/dfp/dtstsfi-56.c: Likewise.
* gcc.target/powerpc/dfp/dtstsfi-71.c: Likewise.
* gcc.target/powerpc/dfp/dtstsfi-76.c: Likewise.
Diff:
---
gcc/config/rs6000/rs6000-builtin-new.def | 4 ++--
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-11.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-16.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-31.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-36.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-51.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-56.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-71.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-76.c | 2 +-
9 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-builtin-new.def b/gcc/config/rs6000/rs6000-builtin-new.def
index 645d4b0425f..6fa121bb38d 100644
--- a/gcc/config/rs6000/rs6000-builtin-new.def
+++ b/gcc/config/rs6000/rs6000-builtin-new.def
@@ -933,7 +933,7 @@
const vsi __builtin_altivec_vspltw (vsi, const int<2>);
VSPLTW altivec_vspltw {}
- const vop __builtin_altivec_vsr (vop, vuc);
+ const vop __builtin_altivec_vsr (vop, vop);
VSR altivec_vsr {}
const vsc __builtin_altivec_vsrab (vsc, vuc);
@@ -951,7 +951,7 @@
const vss __builtin_altivec_vsrh (vss, vus);
VSRH vlshrv8hi3 {}
- const vop __builtin_altivec_vsro (vop, vuc);
+ const vop __builtin_altivec_vsro (vop, vop);
VSRO altivec_vsro {}
const vsi __builtin_altivec_vsrw (vsi, vui);
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-11.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-11.c
index b5bea3cf1a0..6338a0e4278 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-11.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-11.c
@@ -8,6 +8,6 @@ int doTestBCDSignificance (_Decimal64 *p)
{
_Decimal64 source = *p;
- return __builtin_dfp_dtstsfi_lt (5, source); /* { dg-error "'__builtin_dtstsfi_lt' requires" } */ /* { dg-error "'__builtin_dtstsfi_lt_dd' requires" } */
+ return __builtin_dfp_dtstsfi_lt (5, source); /* { dg-error "'__builtin_dtstsfi_lt_dd' requires" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-16.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-16.c
index c6a42f089e0..d889bdd385c 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-16.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-16.c
@@ -8,7 +8,7 @@ int doTestBCDSignificance (_Decimal128 *p)
{
_Decimal128 source = *p;
- return __builtin_dfp_dtstsfi_lt (5, source); /* { dg-error "'__builtin_dtstsfi_lt' requires" } */
+ return __builtin_dfp_dtstsfi_lt (5, source); /* { dg-error "'__builtin_dtstsfi_lt_td' requires" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-31.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-31.c
index 5d9d5d61b42..0d47cc27897 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-31.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-31.c
@@ -8,6 +8,6 @@ int doTestBCDSignificance (_Decimal64 *p)
{
_Decimal64 source = *p;
- return __builtin_dfp_dtstsfi_gt (5, source); /* { dg-error "'__builtin_dtstsfi_gt' requires" } */
+ return __builtin_dfp_dtstsfi_gt (5, source); /* { dg-error "'__builtin_dtstsfi_gt_dd' requires" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-36.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-36.c
index ca5e0098411..f070a0c4a7b 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-36.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-36.c
@@ -8,7 +8,7 @@ int doTestBCDSignificance (_Decimal128 *p)
{
_Decimal128 source = *p;
- return __builtin_dfp_dtstsfi_gt (5, source); /* { dg-error "'__builtin_dtstsfi_gt' requires" } */
+ return __builtin_dfp_dtstsfi_gt (5, source); /* { dg-error "'__builtin_dtstsfi_gt_td' requires" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-51.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-51.c
index 5e4f4964aaa..451a9e74c28 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-51.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-51.c
@@ -8,6 +8,6 @@ int doTestBCDSignificance (_Decimal64 *p)
{
_Decimal64 source = *p;
- return __builtin_dfp_dtstsfi_eq (5, source); /* { dg-error "'__builtin_dtstsfi_eq' requires" } */
+ return __builtin_dfp_dtstsfi_eq (5, source); /* { dg-error "'__builtin_dtstsfi_eq_dd' requires" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-56.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-56.c
index 02ff47441e5..d0833c80f60 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-56.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-56.c
@@ -8,7 +8,7 @@ int doTestBCDSignificance (_Decimal128 *p)
{
_Decimal128 source = *p;
- return __builtin_dfp_dtstsfi_eq (5, source); /* { dg-error "'__builtin_dtstsfi_eq' requires" } */
+ return __builtin_dfp_dtstsfi_eq (5, source); /* { dg-error "'__builtin_dtstsfi_eq_td' requires" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-71.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-71.c
index 6c64021a479..1a54150617e 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-71.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-71.c
@@ -8,6 +8,6 @@ int doTestBCDSignificance (_Decimal64 *p)
{
_Decimal64 source = *p;
- return __builtin_dfp_dtstsfi_ov (5, source); /* { dg-error "'__builtin_dtstsfi_ov' requires" } */
+ return __builtin_dfp_dtstsfi_ov (5, source); /* { dg-error "'__builtin_dtstsfi_ov_dd' requires" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-76.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-76.c
index 982ed5d79df..74269fac328 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-76.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-76.c
@@ -8,7 +8,7 @@ int doTestBCDSignificance (_Decimal128 *p)
{
_Decimal128 source = *p;
- return __builtin_dfp_dtstsfi_ov (5, source); /* { dg-error "'__builtin_dtstsfi_ov' requires" } */
+ return __builtin_dfp_dtstsfi_ov (5, source); /* { dg-error "'__builtin_dtstsfi_ov_td' requires" } */
}
^ permalink raw reply [flat|nested] 29+ messages in thread
* [gcc(refs/users/wschmidt/heads/builtins4)] rs6000: More bug fixes
@ 2021-01-08 20:42 William Schmidt
0 siblings, 0 replies; 29+ messages in thread
From: William Schmidt @ 2021-01-08 20:42 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:3f60eb2cde4607e4ebe05c0c1a67bdaa87c3a374
commit 3f60eb2cde4607e4ebe05c0c1a67bdaa87c3a374
Author: Bill Schmidt <wschmidt@linux.ibm.com>
Date: Fri Jan 8 14:42:22 2021 -0600
rs6000: More bug fixes
2021-01-08 Bill Schmidt <wschmidt@linux.ibm.com>
gcc/
* config/rs6000/emmintrin.h: Change deprecated built-in calls.
* config/rs6000/rs6000-builtin-new.def
(__builtin_altivec_vcmpgtud_p): Fix arguments.
(__builtin_altivec_vcmpaeb_p et al.): Remove {pred}.
gcc/testsuite/
* gcc.target/powerpc/dfp/dtstsfi-11.c: Add second expected error
message.
Diff:
---
gcc/config/rs6000/emmintrin.h | 30 +++++++++++------------
gcc/config/rs6000/rs6000-builtin-new.def | 26 ++++++++++----------
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-11.c | 2 +-
3 files changed, 29 insertions(+), 29 deletions(-)
diff --git a/gcc/config/rs6000/emmintrin.h b/gcc/config/rs6000/emmintrin.h
index b957c1bf798..3ba0df593e7 100644
--- a/gcc/config/rs6000/emmintrin.h
+++ b/gcc/config/rs6000/emmintrin.h
@@ -892,8 +892,8 @@ _mm_cvtpd_epi32 (__m128d __A)
#else
temp = vec_mergee (temp, temp);
#endif
- result = (__v4si) vec_vpkudum ((__vector long long) temp,
- (__vector long long) vzero);
+ result = (__v4si) vec_pack ((__vector long long) temp,
+ (__vector long long) vzero);
#else
{
const __v16qu pkperm = {0x00, 0x01, 0x02, 0x03, 0x08, 0x09, 0x0a, 0x0b,
@@ -931,8 +931,8 @@ _mm_cvtpd_ps (__m128d __A)
#else
temp = vec_mergee (temp, temp);
#endif
- result = (__v4sf) vec_vpkudum ((__vector long long) temp,
- (__vector long long) vzero);
+ result = (__v4sf) vec_pack ((__vector long long) temp,
+ (__vector long long) vzero);
#else
{
const __v16qu pkperm = {0x00, 0x01, 0x02, 0x03, 0x08, 0x09, 0x0a, 0x0b,
@@ -964,8 +964,8 @@ _mm_cvttpd_epi32 (__m128d __A)
#else
temp = vec_mergee (temp, temp);
#endif
- result = (__v4si) vec_vpkudum ((__vector long long) temp,
- (__vector long long) vzero);
+ result = (__v4si) vec_pack ((__vector long long) temp,
+ (__vector long long) vzero);
#else
{
const __v16qu pkperm = {0x00, 0x01, 0x02, 0x03, 0x08, 0x09, 0x0a, 0x0b,
@@ -1254,8 +1254,8 @@ _mm_movemask_pd (__m128d __A)
};
result = ((__vector unsigned long long)
- vec_vbpermq ((__vector unsigned char) __A,
- (__vector unsigned char) perm_mask));
+ vec_bperm ((__vector unsigned char) __A,
+ (__vector unsigned char) perm_mask));
#ifdef __LITTLE_ENDIAN__
return result[1];
@@ -1434,7 +1434,7 @@ _mm_madd_epi16 (__m128i __A, __m128i __B)
{
__vector signed int zero = {0, 0, 0, 0};
- return (__m128i) vec_vmsumshm ((__v8hi)__A, (__v8hi)__B, zero);
+ return (__m128i) vec_msum ((__v8hi)__A, (__v8hi)__B, zero);
}
extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
@@ -1452,8 +1452,8 @@ _mm_mulhi_epi16 (__m128i __A, __m128i __B)
#endif
};
- w0 = vec_vmulesh ((__v8hi)__A, (__v8hi)__B);
- w1 = vec_vmulosh ((__v8hi)__A, (__v8hi)__B);
+ w0 = vec_mule ((__v8hi)__A, (__v8hi)__B);
+ w1 = vec_mulo ((__v8hi)__A, (__v8hi)__B);
return (__m128i) vec_perm (w0, w1, xform1);
}
@@ -2046,8 +2046,8 @@ _mm_movemask_epi8 (__m128i __A)
};
result = ((__vector unsigned long long)
- vec_vbpermq ((__vector unsigned char) __A,
- (__vector unsigned char) perm_mask));
+ vec_bperm ((__vector unsigned char) __A,
+ (__vector unsigned char) perm_mask));
#ifdef __LITTLE_ENDIAN__
return result[1];
@@ -2071,8 +2071,8 @@ _mm_mulhi_epu16 (__m128i __A, __m128i __B)
#endif
};
- w0 = vec_vmuleuh ((__v8hu)__A, (__v8hu)__B);
- w1 = vec_vmulouh ((__v8hu)__A, (__v8hu)__B);
+ w0 = vec_mule ((__v8hu)__A, (__v8hu)__B);
+ w1 = vec_mulo ((__v8hu)__A, (__v8hu)__B);
return (__m128i) vec_perm (w0, w1, xform1);
}
diff --git a/gcc/config/rs6000/rs6000-builtin-new.def b/gcc/config/rs6000/rs6000-builtin-new.def
index 2c1eabd4fde..645d4b0425f 100644
--- a/gcc/config/rs6000/rs6000-builtin-new.def
+++ b/gcc/config/rs6000/rs6000-builtin-new.def
@@ -2214,7 +2214,7 @@
const vsll __builtin_altivec_vcmpgtud (vull, vull);
VCMPGTUD vector_gtuv2di {}
- const int __builtin_altivec_vcmpgtud_p (vull, vull);
+ const int __builtin_altivec_vcmpgtud_p (int, vull, vull);
VCMPGTUD_P vector_gtu_v2di_p {pred}
const vsll __builtin_altivec_vmaxsd (vsll, vsll);
@@ -2582,49 +2582,49 @@
VCTZLSBB_V8HI vctzlsbb_v8hi {}
const signed int __builtin_altivec_vcmpaeb_p (vsc, vsc);
- VCMPAEB_P vector_ae_v16qi_p {pred}
+ VCMPAEB_P vector_ae_v16qi_p {}
const signed int __builtin_altivec_vcmpaed_p (vsll, vsll);
- VCMPAED_P vector_ae_v2di_p {pred}
+ VCMPAED_P vector_ae_v2di_p {}
const signed int __builtin_altivec_vcmpaedp_p (vd, vd);
- VCMPAEDP_P vector_ae_v2df_p {pred}
+ VCMPAEDP_P vector_ae_v2df_p {}
const signed int __builtin_altivec_vcmpaefp_p (vf, vf);
- VCMPAEFP_P vector_ae_v4sf_p {pred}
+ VCMPAEFP_P vector_ae_v4sf_p {}
const signed int __builtin_altivec_vcmpaeh_p (vss, vss);
- VCMPAEH_P vector_ae_v8hi_p {pred}
+ VCMPAEH_P vector_ae_v8hi_p {}
const signed int __builtin_altivec_vcmpaew_p (vsi, vsi);
- VCMPAEW_P vector_ae_v4si_p {pred}
+ VCMPAEW_P vector_ae_v4si_p {}
const vsc __builtin_altivec_vcmpneb (vsc, vsc);
VCMPNEB vcmpneb {}
const signed int __builtin_altivec_vcmpneb_p (vsc, vsc);
- VCMPNEB_P vector_ne_v16qi_p {pred}
+ VCMPNEB_P vector_ne_v16qi_p {}
const signed int __builtin_altivec_vcmpned_p (vsll, vsll);
- VCMPNED_P vector_ne_v2di_p {pred}
+ VCMPNED_P vector_ne_v2di_p {}
const signed int __builtin_altivec_vcmpnedp_p (vd, vd);
- VCMPNEDP_P vector_ne_v2df_p {pred}
+ VCMPNEDP_P vector_ne_v2df_p {}
const signed int __builtin_altivec_vcmpnefp_p (vf, vf);
- VCMPNEFP_P vector_ne_v4sf_p {pred}
+ VCMPNEFP_P vector_ne_v4sf_p {}
const vss __builtin_altivec_vcmpneh (vss, vss);
VCMPNEH vcmpneh {}
const signed int __builtin_altivec_vcmpneh_p (vss, vss);
- VCMPNEH_P vector_ne_v8hi_p {pred}
+ VCMPNEH_P vector_ne_v8hi_p {}
const vsi __builtin_altivec_vcmpnew (vsi, vsi);
VCMPNEW vcmpnew {}
const signed int __builtin_altivec_vcmpnew_p (vsi, vsi);
- VCMPNEW_P vector_ne_v4si_p {pred}
+ VCMPNEW_P vector_ne_v4si_p {}
const vsc __builtin_altivec_vcmpnezb (vsc, vsc);
CMPNEZB vcmpnezb {}
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-11.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-11.c
index c56a24e0db4..b5bea3cf1a0 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-11.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-11.c
@@ -8,6 +8,6 @@ int doTestBCDSignificance (_Decimal64 *p)
{
_Decimal64 source = *p;
- return __builtin_dfp_dtstsfi_lt (5, source); /* { dg-error "'__builtin_dtstsfi_lt' requires" } */
+ return __builtin_dfp_dtstsfi_lt (5, source); /* { dg-error "'__builtin_dtstsfi_lt' requires" } */ /* { dg-error "'__builtin_dtstsfi_lt_dd' requires" } */
}
^ permalink raw reply [flat|nested] 29+ messages in thread
* [gcc(refs/users/wschmidt/heads/builtins4)] rs6000: More bug fixes
@ 2021-01-07 18:23 William Schmidt
0 siblings, 0 replies; 29+ messages in thread
From: William Schmidt @ 2021-01-07 18:23 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:0732844addff2822e74d2fd862d72781b96f44bd
commit 0732844addff2822e74d2fd862d72781b96f44bd
Author: Bill Schmidt <wschmidt@linux.ibm.com>
Date: Thu Jan 7 12:17:54 2021 -0600
rs6000: More bug fixes
2021-01-07 Bill Schmidt <wschmidt@linux.ibm.com>
gcc/
* config/rs6000/rs6000-builtin-new.def
* config/rs6000-overload.def
gcc/testsuite/
* gcc.target/powerpc/altivec-10.c: Adjust.
* gcc.target/powerpc/bfp/scalar-test-neg-2.c: Adjust.
* gcc.target/powerpc/bfp/scalar-test-neg-3.c: Adjust.
* gcc.target/powerpc/bfp/scalar-test-neg-5.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-10.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-11.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-12.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-13.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-14.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-15.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-16.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-17.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-18.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-19.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-30.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-31.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-32.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-33.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-34.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-35.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-36.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-37.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-38.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-39.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-50.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-51.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-52.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-53.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-54.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-55.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-56.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-57.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-58.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-59.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-70.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-71.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-72.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-73.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-74.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-75.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-76.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-77.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-78.c: Adjust.
* gcc.target/powerpc/dfp/dtstsfi-79.c: Adjust.
Diff:
---
gcc/config/rs6000/rs6000-builtin-new.def | 26 ++++++++---------
gcc/config/rs6000/rs6000-overload.def | 34 +++++++++++-----------
gcc/testsuite/gcc.target/powerpc/altivec-10.c | 2 +-
.../gcc.target/powerpc/bfp/scalar-test-neg-2.c | 2 +-
.../gcc.target/powerpc/bfp/scalar-test-neg-3.c | 2 +-
.../gcc.target/powerpc/bfp/scalar-test-neg-5.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-10.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-11.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-12.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-13.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-14.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-15.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-16.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-17.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-18.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-19.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-30.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-31.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-32.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-33.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-34.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-35.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-36.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-37.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-38.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-39.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-50.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-51.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-52.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-53.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-54.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-55.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-56.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-57.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-58.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-59.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-70.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-71.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-72.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-73.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-74.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-75.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-76.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-77.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-78.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-79.c | 2 +-
46 files changed, 74 insertions(+), 74 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-builtin-new.def b/gcc/config/rs6000/rs6000-builtin-new.def
index 8b54b17e1ce..2c1eabd4fde 100644
--- a/gcc/config/rs6000/rs6000-builtin-new.def
+++ b/gcc/config/rs6000/rs6000-builtin-new.def
@@ -2734,10 +2734,10 @@
const signed int __builtin_vsx_scalar_cmp_exp_dp_unordered (double, double);
VSCEDPUO xscmpexpdp_unordered {}
- const unsigned int __builtin_vsx_scalar_test_data_class_dp (double, signed int);
+ const unsigned int __builtin_vsx_scalar_test_data_class_dp (double, const int<7>);
VSTDCDP xststdcdp {}
- const unsigned int __builtin_vsx_scalar_test_data_class_sp (float, signed int);
+ const unsigned int __builtin_vsx_scalar_test_data_class_sp (float, const int<7>);
VSTDCSP xststdcsp {}
const unsigned int __builtin_vsx_scalar_test_neg_dp (double);
@@ -2746,10 +2746,10 @@
const unsigned int __builtin_vsx_scalar_test_neg_sp (float);
VSTDCNSP xststdcnegsp {}
- const vbll __builtin_vsx_test_data_class_dp (vd, signed int);
+ const vbll __builtin_vsx_test_data_class_dp (vd, const int<7>);
VTDCDP xvtstdcdp {}
- const vbi __builtin_vsx_test_data_class_sp (vf, signed int);
+ const vbi __builtin_vsx_test_data_class_sp (vf, const int<7>);
VTDCSP xvtstdcsp {}
const vf __builtin_vsx_vextract_fp_from_shorth (vus);
@@ -2794,28 +2794,28 @@
double __builtin_mffsl ();
MFFSL rs6000_mffsl {}
- const signed int __builtin_dtstsfi_eq_dd (unsigned int, _Decimal64);
+ const signed int __builtin_dtstsfi_eq_dd (const int<6>, _Decimal64);
TSTSFI_EQ_DD dfptstsfi_eq_dd {}
- const signed int __builtin_dtstsfi_eq_td (unsigned int, _Decimal128);
+ const signed int __builtin_dtstsfi_eq_td (const int<6>, _Decimal128);
TSTSFI_EQ_TD dfptstsfi_eq_td {}
- const signed int __builtin_dtstsfi_gt_dd (unsigned int, _Decimal64);
+ const signed int __builtin_dtstsfi_gt_dd (const int<6>, _Decimal64);
TSTSFI_GT_DD dfptstsfi_gt_dd {}
- const signed int __builtin_dtstsfi_gt_td (unsigned int, _Decimal128);
+ const signed int __builtin_dtstsfi_gt_td (const int<6>, _Decimal128);
TSTSFI_GT_TD dfptstsfi_gt_td {}
- const signed int __builtin_dtstsfi_lt_dd (unsigned int, _Decimal64);
+ const signed int __builtin_dtstsfi_lt_dd (const int<6>, _Decimal64);
TSTSFI_LT_DD dfptstsfi_lt_dd {}
- const signed int __builtin_dtstsfi_lt_td (unsigned int, _Decimal128);
+ const signed int __builtin_dtstsfi_lt_td (const int<6>, _Decimal128);
TSTSFI_LT_TD dfptstsfi_lt_td {}
- const signed int __builtin_dtstsfi_ov_dd (unsigned int, _Decimal64);
+ const signed int __builtin_dtstsfi_ov_dd (const int<6>, _Decimal64);
TSTSFI_OV_DD dfptstsfi_unordered_dd {}
- const signed int __builtin_dtstsfi_ov_td (unsigned int, _Decimal128);
+ const signed int __builtin_dtstsfi_ov_td (const int<6>, _Decimal128);
TSTSFI_OV_TD dfptstsfi_unordered_td {}
@@ -2905,7 +2905,7 @@
const _Float128 __builtin_vsx_scalar_insert_exp_qp (_Float128, unsigned long long);
VSIEQPF xsiexpqpf_kf {}
- const unsigned int __builtin_vsx_scalar_test_data_class_qp (_Float128, signed int);
+ const unsigned int __builtin_vsx_scalar_test_data_class_qp (_Float128, const int<7>);
VSTDCQP xststdcqp_kf {}
const unsigned int __builtin_vsx_scalar_test_neg_qp (_Float128);
diff --git a/gcc/config/rs6000/rs6000-overload.def b/gcc/config/rs6000/rs6000-overload.def
index 60a18a79416..45e95ea3063 100644
--- a/gcc/config/rs6000/rs6000-overload.def
+++ b/gcc/config/rs6000/rs6000-overload.def
@@ -3548,27 +3548,27 @@
XVRDPIZ
[VEC_TSTSFI_GT, SKIP, __builtin_dfp_dtstsfi_gt]
- signed int __builtin_dfp_dtstsfi_gt (unsigned int, _Decimal64);
+ signed int __builtin_dfp_dtstsfi_gt (const int, _Decimal64);
TSTSFI_GT_DD
- signed int __builtin_dfp_dtstsfi_gt (unsigned int, _Decimal128);
+ signed int __builtin_dfp_dtstsfi_gt (const int, _Decimal128);
TSTSFI_GT_TD
[VEC_TSTSFI_EQ, SKIP, __builtin_dfp_dtstsfi_eq]
- signed int __builtin_dfp_dtstsfi_eq (unsigned int, _Decimal64);
+ signed int __builtin_dfp_dtstsfi_eq (const int, _Decimal64);
TSTSFI_EQ_DD
- signed int __builtin_dfp_dtstsfi_eq (unsigned int, _Decimal128);
+ signed int __builtin_dfp_dtstsfi_eq (const int, _Decimal128);
TSTSFI_EQ_TD
[VEC_TSTSFI_LT, SKIP, __builtin_dfp_dtstsfi_lt]
- signed int __builtin_dfp_dtstsfi_lt (unsigned int, _Decimal64);
+ signed int __builtin_dfp_dtstsfi_lt (const int, _Decimal64);
TSTSFI_LT_DD
- signed int __builtin_dfp_dtstsfi_lt (unsigned int, _Decimal128);
+ signed int __builtin_dfp_dtstsfi_lt (const int, _Decimal128);
TSTSFI_LT_TD
[VEC_TSTSFI_OV, SKIP, __builtin_dfp_dtstsfi_ov]
- signed int __builtin_dfp_dtstsfi_ov (unsigned int, _Decimal64);
+ signed int __builtin_dfp_dtstsfi_ov (const int, _Decimal64);
TSTSFI_OV_DD
- signed int __builtin_dfp_dtstsfi_ov (unsigned int, _Decimal128);
+ signed int __builtin_dfp_dtstsfi_ov (const int, _Decimal128);
TSTSFI_OV_TD
[VEC_UNPACKH, vec_unpackh, __builtin_vec_unpackh]
@@ -3637,7 +3637,7 @@
vull __builtin_vec_extract_sig (vd);
VESDP
-[VEC_VIE, vec_insert_exp, __builtin_vec_insert_exp, ARCH_PWR9]
+[VEC_VIE, vec_insert_exp, __builtin_vec_insert_exp, _ARCH_PWR9]
vf __builtin_vec_insert_exp (vf, vui);
VIESP VIESP_VF
vf __builtin_vec_insert_exp (vui, vui);
@@ -3694,25 +3694,25 @@
VSIEQPF
[VEC_VSTDC, scalar_test_data_class, __builtin_vec_scalar_test_data_class, _ARCH_PWR9]
- bool __builtin_vec_scalar_test_data_class (float, signed int);
+ unsigned int __builtin_vec_scalar_test_data_class (float, const int);
VSTDCSP
- bool __builtin_vec_scalar_test_data_class (double, signed int);
+ unsigned int __builtin_vec_scalar_test_data_class (double, const int);
VSTDCDP
- bool __builtin_vec_scalar_test_data_class (_Float128, signed int);
+ unsigned int __builtin_vec_scalar_test_data_class (_Float128, const int);
VSTDCQP
[VEC_VSTDCN, scalar_test_neg, __builtin_vec_scalar_test_neg, _ARCH_PWR9]
- bool __builtin_vec_scalar_test_neg (float);
+ unsigned int __builtin_vec_scalar_test_neg (float);
VSTDCNSP
- bool __builtin_vec_scalar_test_neg (double);
+ unsigned int __builtin_vec_scalar_test_neg (double);
VSTDCNDP
- bool __builtin_vec_scalar_test_neg (_Float128);
+ unsigned int __builtin_vec_scalar_test_neg (_Float128);
VSTDCNQP
[VEC_VTDC, vec_test_data_class, __builtin_vec_test_data_class, _ARCH_PWR9]
- vbi __builtin_vec_test_data_class (vf, signed int);
+ vbi __builtin_vec_test_data_class (vf, const int);
VTDCSP
- vbll __builtin_vec_test_data_class (vd, signed int);
+ vbll __builtin_vec_test_data_class (vd, const int);
VTDCDP
[VEC_XL, vec_xl, __builtin_vec_vsx_ld, __VSX__]
diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-10.c b/gcc/testsuite/gcc.target/powerpc/altivec-10.c
index f532eebbfab..e12b88a165b 100644
--- a/gcc/testsuite/gcc.target/powerpc/altivec-10.c
+++ b/gcc/testsuite/gcc.target/powerpc/altivec-10.c
@@ -61,7 +61,7 @@ check_cmple()
vector float a = {1.0, 2.0, 3.0, 4.0};
vector float b = {1.0, 3.0, 2.0, 5.0};
vector bool int aux;
- vector signed int le = {-1, -1, 0, -1};
+ vector bool int le = (vector bool int){-1, -1, 0, -1};
aux = vec_cmple (a, b);
diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-2.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-2.c
index 7d2b4deefc3..7a1e8e8bd30 100644
--- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-2.c
+++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-2.c
@@ -10,5 +10,5 @@ test_neg (float *p)
{
float source = *p;
- return __builtin_vec_scalar_test_neg_sp (source); /* { dg-error "'__builtin_vsx_scalar_test_neg_sp' requires" } */
+ return __builtin_vec_scalar_test_neg (source); /* { dg-error "'__builtin_vsx_scalar_test_neg' requires" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-3.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-3.c
index b503dfa8b56..c9b90927693 100644
--- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-3.c
@@ -10,5 +10,5 @@ test_neg (double *p)
{
double source = *p;
- return __builtin_vec_scalar_test_neg_dp (source); /* { dg-error "'__builtin_vsx_scalar_test_neg_dp' requires" } */
+ return __builtin_vec_scalar_test_neg (source); /* { dg-error "'__builtin_vsx_scalar_test_neg' requires" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-5.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-5.c
index bab86040a7b..e70eb2d46f8 100644
--- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-5.c
+++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-5.c
@@ -10,5 +10,5 @@ test_neg (__ieee128 *p)
{
__ieee128 source = *p;
- return __builtin_vec_scalar_test_neg_qp (source); /* { dg-error "'__builtin_vsx_scalar_test_neg_qp' requires" } */
+ return __builtin_vec_scalar_test_neg (source); /* { dg-error "'__builtin_vsx_scalar_test_neg' requires" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-10.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-10.c
index 822030bf737..4f7562b9c38 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-10.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-10.c
@@ -9,7 +9,7 @@ int doTestBCDSignificance (_Decimal64 *p)
{
_Decimal64 source = *p;
- return __builtin_dfp_dtstsfi_lt_dd (5, source);
+ return __builtin_dfp_dtstsfi_lt (5, source);
}
/* { dg-final { scan-assembler "dtstsfi" } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-11.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-11.c
index 044e7683cf1..c56a24e0db4 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-11.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-11.c
@@ -8,6 +8,6 @@ int doTestBCDSignificance (_Decimal64 *p)
{
_Decimal64 source = *p;
- return __builtin_dfp_dtstsfi_lt_dd (5, source); /* { dg-error "'__builtin_dtstsfi_lt_dd' requires" } */
+ return __builtin_dfp_dtstsfi_lt (5, source); /* { dg-error "'__builtin_dtstsfi_lt' requires" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-12.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-12.c
index 350b4c10205..4b72fa8edc3 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-12.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-12.c
@@ -8,6 +8,6 @@ int doTestBCDSignificance (_Decimal64 *p)
{
_Decimal64 source = *p;
- return __builtin_dfp_dtstsfi_lt_dd (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
+ return __builtin_dfp_dtstsfi_lt (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-13.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-13.c
index cc54c6b265e..af07fbb4a01 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-13.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-13.c
@@ -8,7 +8,7 @@ int doTestBCDSignificance (_Decimal64 *p)
{
_Decimal64 source = *p;
- if (__builtin_dfp_dtstsfi_lt_dd (63, source))
+ if (__builtin_dfp_dtstsfi_lt (63, source))
return 3;
else
return 5;
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-14.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-14.c
index 011d20039d0..6397aae3e56 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-14.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-14.c
@@ -8,6 +8,6 @@ int doTestBCDSignificance (_Decimal64 *p, unsigned int significance)
{
_Decimal64 source = *p;
- return __builtin_dfp_dtstsfi_lt_dd (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
+ return __builtin_dfp_dtstsfi_lt (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-15.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-15.c
index 54d2557fa2f..6f57baf0150 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-15.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-15.c
@@ -9,7 +9,7 @@ int doTestBCDSignificance (_Decimal128 *p)
{
_Decimal128 source = *p;
- return __builtin_dfp_dtstsfi_lt_td (5, source);
+ return __builtin_dfp_dtstsfi_lt (5, source);
}
/* { dg-final { scan-assembler "dtstsfiq" } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-16.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-16.c
index 8626c579a25..c6a42f089e0 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-16.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-16.c
@@ -8,7 +8,7 @@ int doTestBCDSignificance (_Decimal128 *p)
{
_Decimal128 source = *p;
- return __builtin_dfp_dtstsfi_lt_td (5, source); /* { dg-error "'__builtin_dtstsfi_lt_td' requires" } */
+ return __builtin_dfp_dtstsfi_lt (5, source); /* { dg-error "'__builtin_dtstsfi_lt' requires" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-17.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-17.c
index 28033dbac18..ea934ea4652 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-17.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-17.c
@@ -8,7 +8,7 @@ int doTestBCDSignificance (_Decimal128 *p)
{
_Decimal128 source = *p;
- return __builtin_dfp_dtstsfi_lt_td (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
+ return __builtin_dfp_dtstsfi_lt (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-18.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-18.c
index 8ce9390feaf..28bc10c3145 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-18.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-18.c
@@ -8,7 +8,7 @@ int doTestBCDSignificance (_Decimal128 *p)
{
_Decimal128 source = *p;
- if (__builtin_dfp_dtstsfi_lt_td (63, source))
+ if (__builtin_dfp_dtstsfi_lt (63, source))
return 3;
else
return 5;
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-19.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-19.c
index 092b9c0f7c5..b2073f56b05 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-19.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-19.c
@@ -8,5 +8,5 @@ int doTestBCDSignificance (_Decimal128 *p, unsigned int significance)
{
_Decimal128 source = *p;
- return __builtin_dfp_dtstsfi_lt_td (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
+ return __builtin_dfp_dtstsfi_lt (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-30.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-30.c
index 6d8869e5435..ee098bcb999 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-30.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-30.c
@@ -9,7 +9,7 @@ int doTestBCDSignificance (_Decimal64 *p)
{
_Decimal64 source = *p;
- return __builtin_dfp_dtstsfi_gt_dd (5, source);
+ return __builtin_dfp_dtstsfi_gt (5, source);
}
/* { dg-final { scan-assembler "dtstsfi" } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-31.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-31.c
index 439fcb2a548..5d9d5d61b42 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-31.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-31.c
@@ -8,6 +8,6 @@ int doTestBCDSignificance (_Decimal64 *p)
{
_Decimal64 source = *p;
- return __builtin_dfp_dtstsfi_gt_dd (5, source); /* { dg-error "'__builtin_dtstsfi_gt_dd' requires" } */
+ return __builtin_dfp_dtstsfi_gt (5, source); /* { dg-error "'__builtin_dtstsfi_gt' requires" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-32.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-32.c
index d24f3982ee9..15d7a352fdf 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-32.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-32.c
@@ -8,6 +8,6 @@ int doTestBCDSignificance (_Decimal64 *p)
{
_Decimal64 source = *p;
- return __builtin_dfp_dtstsfi_gt_dd (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
+ return __builtin_dfp_dtstsfi_gt (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-33.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-33.c
index 6d978a09750..236f39393e0 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-33.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-33.c
@@ -8,7 +8,7 @@ int doTestBCDSignificance (_Decimal64 *p)
{
_Decimal64 source = *p;
- if (__builtin_dfp_dtstsfi_gt_dd (63, source))
+ if (__builtin_dfp_dtstsfi_gt (63, source))
return 3;
else
return 5;
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-34.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-34.c
index b6620c51f2a..f6ed00a73dd 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-34.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-34.c
@@ -8,6 +8,6 @@ int doTestBCDSignificance (_Decimal64 *p, unsigned int significance)
{
_Decimal64 source = *p;
- return __builtin_dfp_dtstsfi_gt_dd (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
+ return __builtin_dfp_dtstsfi_gt (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-35.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-35.c
index fdafaf9ceb8..1390c8381f8 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-35.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-35.c
@@ -9,7 +9,7 @@ int doTestBCDSignificance (_Decimal128 *p)
{
_Decimal128 source = *p;
- return __builtin_dfp_dtstsfi_gt_td (5, source);
+ return __builtin_dfp_dtstsfi_gt (5, source);
}
/* { dg-final { scan-assembler "dtstsfiq" } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-36.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-36.c
index 822f6d57003..ca5e0098411 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-36.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-36.c
@@ -8,7 +8,7 @@ int doTestBCDSignificance (_Decimal128 *p)
{
_Decimal128 source = *p;
- return __builtin_dfp_dtstsfi_gt_td (5, source); /* { dg-error "'__builtin_dtstsfi_gt_td' requires" } */
+ return __builtin_dfp_dtstsfi_gt (5, source); /* { dg-error "'__builtin_dtstsfi_gt' requires" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-37.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-37.c
index dc4c8ecdd00..8e3954d6b93 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-37.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-37.c
@@ -8,7 +8,7 @@ int doTestBCDSignificance (_Decimal128 *p)
{
_Decimal128 source = *p;
- return __builtin_dfp_dtstsfi_gt_td (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
+ return __builtin_dfp_dtstsfi_gt (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-38.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-38.c
index fce744cd916..a2b922955f6 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-38.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-38.c
@@ -8,7 +8,7 @@ int doTestBCDSignificance (_Decimal128 *p)
{
_Decimal128 source = *p;
- if (__builtin_dfp_dtstsfi_gt_td (63, source))
+ if (__builtin_dfp_dtstsfi_gt (63, source))
return 3;
else
return 5;
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-39.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-39.c
index 1aee9efe919..f6c0ede46cc 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-39.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-39.c
@@ -8,5 +8,5 @@ int doTestBCDSignificance (_Decimal128 *p, unsigned int significance)
{
_Decimal128 source = *p;
- return __builtin_dfp_dtstsfi_gt_td (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
+ return __builtin_dfp_dtstsfi_gt (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-50.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-50.c
index 25b35ed4bc9..4663fc653bb 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-50.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-50.c
@@ -9,7 +9,7 @@ int doTestBCDSignificance (_Decimal64 *p)
{
_Decimal64 source = *p;
- return __builtin_dfp_dtstsfi_eq_dd (5, source);
+ return __builtin_dfp_dtstsfi_eq (5, source);
}
/* { dg-final { scan-assembler "dtstsfi" } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-51.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-51.c
index e6b5fe5469e..5e4f4964aaa 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-51.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-51.c
@@ -8,6 +8,6 @@ int doTestBCDSignificance (_Decimal64 *p)
{
_Decimal64 source = *p;
- return __builtin_dfp_dtstsfi_eq_dd (5, source); /* { dg-error "'__builtin_dtstsfi_eq_dd' requires" } */
+ return __builtin_dfp_dtstsfi_eq (5, source); /* { dg-error "'__builtin_dtstsfi_eq' requires" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-52.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-52.c
index c9431b5ea1a..fc6b3568d09 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-52.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-52.c
@@ -8,6 +8,6 @@ int doTestBCDSignificance (_Decimal64 *p)
{
_Decimal64 source = *p;
- return __builtin_dfp_dtstsfi_eq_dd (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
+ return __builtin_dfp_dtstsfi_eq (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-53.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-53.c
index d11f497b137..9c194374187 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-53.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-53.c
@@ -8,7 +8,7 @@ int doTestBCDSignificance (_Decimal64 *p)
{
_Decimal64 source = *p;
- if (__builtin_dfp_dtstsfi_eq_dd (63, source))
+ if (__builtin_dfp_dtstsfi_eq (63, source))
return 3;
else
return 5;
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-54.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-54.c
index 2fdb58f6748..b896865e6bb 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-54.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-54.c
@@ -8,6 +8,6 @@ int doTestBCDSignificance (_Decimal64 *p, unsigned int significance)
{
_Decimal64 source = *p;
- return __builtin_dfp_dtstsfi_eq_dd (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
+ return __builtin_dfp_dtstsfi_eq (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-55.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-55.c
index 912ae7f3492..5c6fcc4ec83 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-55.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-55.c
@@ -9,7 +9,7 @@ int doTestBCDSignificance (_Decimal128 *p)
{
_Decimal128 source = *p;
- return __builtin_dfp_dtstsfi_eq_td (5, source);
+ return __builtin_dfp_dtstsfi_eq (5, source);
}
/* { dg-final { scan-assembler "dtstsfiq" } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-56.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-56.c
index 218d2f64d3e..02ff47441e5 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-56.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-56.c
@@ -8,7 +8,7 @@ int doTestBCDSignificance (_Decimal128 *p)
{
_Decimal128 source = *p;
- return __builtin_dfp_dtstsfi_eq_td (5, source); /* { dg-error "'__builtin_dtstsfi_eq_td' requires" } */
+ return __builtin_dfp_dtstsfi_eq (5, source); /* { dg-error "'__builtin_dtstsfi_eq' requires" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-57.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-57.c
index 275bf8d0ac2..edfac68b0e8 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-57.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-57.c
@@ -8,7 +8,7 @@ int doTestBCDSignificance (_Decimal128 *p)
{
_Decimal128 source = *p;
- return __builtin_dfp_dtstsfi_eq_td (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
+ return __builtin_dfp_dtstsfi_eq (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-58.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-58.c
index 0626d87d9be..9a94371da35 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-58.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-58.c
@@ -8,7 +8,7 @@ int doTestBCDSignificance (_Decimal128 *p)
{
_Decimal128 source = *p;
- if (__builtin_dfp_dtstsfi_eq_td (63, source))
+ if (__builtin_dfp_dtstsfi_eq (63, source))
return 3;
else
return 5;
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-59.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-59.c
index e1da3d810ef..e7b50dc108e 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-59.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-59.c
@@ -8,5 +8,5 @@ int doTestBCDSignificance (_Decimal128 *p, unsigned int significance)
{
_Decimal128 source = *p;
- return __builtin_dfp_dtstsfi_eq_td (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
+ return __builtin_dfp_dtstsfi_eq (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-70.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-70.c
index 875354c9ab8..c584d988b4b 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-70.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-70.c
@@ -9,7 +9,7 @@ int doTestBCDSignificance (_Decimal64 *p)
{
_Decimal64 source = *p;
- return __builtin_dfp_dtstsfi_ov_dd (5, source);
+ return __builtin_dfp_dtstsfi_ov (5, source);
}
/* { dg-final { scan-assembler "dtstsfi" } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-71.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-71.c
index 68758cf535a..6c64021a479 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-71.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-71.c
@@ -8,6 +8,6 @@ int doTestBCDSignificance (_Decimal64 *p)
{
_Decimal64 source = *p;
- return __builtin_dfp_dtstsfi_ov_dd (5, source); /* { dg-error "'__builtin_dtstsfi_ov_dd' requires" } */
+ return __builtin_dfp_dtstsfi_ov (5, source); /* { dg-error "'__builtin_dtstsfi_ov' requires" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-72.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-72.c
index 725cc5432b9..44aaab201f9 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-72.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-72.c
@@ -8,6 +8,6 @@ int doTestBCDSignificance (_Decimal64 *p)
{
_Decimal64 source = *p;
- return __builtin_dfp_dtstsfi_ov_dd (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
+ return __builtin_dfp_dtstsfi_ov (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-73.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-73.c
index f368c38204b..e7d2a27ecfd 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-73.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-73.c
@@ -8,7 +8,7 @@ int doTestBCDSignificance (_Decimal64 *p)
{
_Decimal64 source = *p;
- if (__builtin_dfp_dtstsfi_ov_dd (63, source))
+ if (__builtin_dfp_dtstsfi_ov (63, source))
return 3;
else
return 5;
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-74.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-74.c
index c6ffd51d9f4..fb3331162c7 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-74.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-74.c
@@ -8,6 +8,6 @@ int doTestBCDSignificance (_Decimal64 *p, unsigned int significance)
{
_Decimal64 source = *p;
- return __builtin_dfp_dtstsfi_ov_dd (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
+ return __builtin_dfp_dtstsfi_ov (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-75.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-75.c
index 910fb7d98c8..7c75265de08 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-75.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-75.c
@@ -9,7 +9,7 @@ int doTestBCDSignificance (_Decimal128 *p)
{
_Decimal128 source = *p;
- return __builtin_dfp_dtstsfi_ov_td (5, source);
+ return __builtin_dfp_dtstsfi_ov (5, source);
}
/* { dg-final { scan-assembler "dtstsfiq" } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-76.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-76.c
index d867a987df8..982ed5d79df 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-76.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-76.c
@@ -8,7 +8,7 @@ int doTestBCDSignificance (_Decimal128 *p)
{
_Decimal128 source = *p;
- return __builtin_dfp_dtstsfi_ov_td (5, source); /* { dg-error "'__builtin_dtstsfi_ov_td' requires" } */
+ return __builtin_dfp_dtstsfi_ov (5, source); /* { dg-error "'__builtin_dtstsfi_ov' requires" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-77.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-77.c
index d279bfb5751..59471cfb645 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-77.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-77.c
@@ -8,7 +8,7 @@ int doTestBCDSignificance (_Decimal128 *p)
{
_Decimal128 source = *p;
- return __builtin_dfp_dtstsfi_ov_td (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
+ return __builtin_dfp_dtstsfi_ov (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-78.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-78.c
index 3034300f72b..1bda795b55a 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-78.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-78.c
@@ -8,7 +8,7 @@ int doTestBCDSignificance (_Decimal128 *p)
{
_Decimal128 source = *p;
- if (__builtin_dfp_dtstsfi_ov_td (63, source))
+ if (__builtin_dfp_dtstsfi_ov (63, source))
return 3;
else
return 5;
diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-79.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-79.c
index b88b5a86bcb..c9e1721b3d6 100644
--- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-79.c
+++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-79.c
@@ -8,5 +8,5 @@ int doTestBCDSignificance (_Decimal128 *p, unsigned int significance)
{
_Decimal128 source = *p;
- return __builtin_dfp_dtstsfi_ov_td (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
+ return __builtin_dfp_dtstsfi_ov (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
}
^ permalink raw reply [flat|nested] 29+ messages in thread
* [gcc(refs/users/wschmidt/heads/builtins4)] rs6000: More bug fixes
@ 2021-01-06 21:07 William Schmidt
0 siblings, 0 replies; 29+ messages in thread
From: William Schmidt @ 2021-01-06 21:07 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:4e6f54a98669614e30c8989e9dcf0529b9f92bf4
commit 4e6f54a98669614e30c8989e9dcf0529b9f92bf4
Author: Bill Schmidt <wschmidt@linux.ibm.com>
Date: Wed Jan 6 15:06:45 2021 -0600
rs6000: More bug fixes
2021-01-06 Bill Schmidt <wschmidt@linux.ibm.com>
gcc/
* config/rs6000/rs6000-c.c
(altivec_resolve_new_overloaded_builtin): Fix arg access thinko.
* config/rs6000/rs6000-overload-def (VEC_OR): Add missing forms.
(VEC_VSCEUO): Fix typo.
gcc/testsuite/
* gcc.dg/vmx/ops.c: Remove bad srl and vec_v* forms.
Diff:
---
gcc/config/rs6000/rs6000-c.c | 2 +-
gcc/config/rs6000/rs6000-overload.def | 52 +++++++++++++--
gcc/testsuite/gcc.dg/vmx/ops.c | 120 ----------------------------------
3 files changed, 47 insertions(+), 127 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c
index c5402cc2d8e..1de614ba2b3 100644
--- a/gcc/config/rs6000/rs6000-c.c
+++ b/gcc/config/rs6000/rs6000-c.c
@@ -2884,7 +2884,7 @@ altivec_resolve_new_overloaded_builtin (location_t loc, tree fndecl,
gcc_assert (instance != NULL);
tree fntype = rs6000_builtin_info_x[instance->bifid].fntype;
tree parmtype0 = TREE_VALUE (TYPE_ARG_TYPES (fntype));
- tree parmtype1 = TREE_VALUE (TREE_CHAIN (parmtype0));
+ tree parmtype1 = TREE_VALUE (TREE_CHAIN (TYPE_ARG_TYPES (fntype)));
if (rs6000_new_builtin_type_compatible (types[0], parmtype0)
&& rs6000_new_builtin_type_compatible (types[1], parmtype1))
diff --git a/gcc/config/rs6000/rs6000-overload.def b/gcc/config/rs6000/rs6000-overload.def
index 0876b8068bc..60a18a79416 100644
--- a/gcc/config/rs6000/rs6000-overload.def
+++ b/gcc/config/rs6000/rs6000-overload.def
@@ -2175,32 +2175,72 @@
[VEC_OR, vec_or, __builtin_vec_or]
vsc __builtin_vec_or (vsc, vsc);
VOR_V16QI
+ vsc __builtin_vec_or (vsc, vbc);
+ VOR_V16QI VOR_VSC_VBC
+ vsc __builtin_vec_or (vbc, vsc);
+ VOR_V16QI VOR_VBC_VSC
vuc __builtin_vec_or (vuc, vuc);
VOR_V16QI_UNS VOR_V16QI_U
vbc __builtin_vec_or (vbc, vbc);
VOR_V16QI_UNS VOR_V16QI_B
+ vuc __builtin_vec_or (vuc, vbc);
+ VOR_V16QI_UNS VOR_V16QI_UB
+ vuc __builtin_vec_or (vbc, vuc);
+ VOR_V16QI_UNS VOR_V16QI_BU
vss __builtin_vec_or (vss, vss);
VOR_V8HI
+ vss __builtin_vec_or (vss, vbs);
+ VOR_V8HI VOR_VSS_VBS
+ vss __builtin_vec_or (vbs, vss);
+ VOR_V8HI VOR_VBS_VSS
vus __builtin_vec_or (vus, vus);
VOR_V8HI_UNS VOR_V8HI_U
vbs __builtin_vec_or (vbs, vbs);
VOR_V8HI_UNS VOR_V8HI_B
+ vus __builtin_vec_or (vus, vbs);
+ VOR_V8HI_UNS VOR_V8HI_UB
+ vus __builtin_vec_or (vbs, vus);
+ VOR_V8HI_UNS VOR_V8HI_BU
vsi __builtin_vec_or (vsi, vsi);
VOR_V4SI
+ vsi __builtin_vec_or (vsi, vbi);
+ VOR_V4SI VOR_VSI_VBI
+ vsi __builtin_vec_or (vbi, vsi);
+ VOR_V4SI VOR_VBI_VSI
vui __builtin_vec_or (vui, vui);
VOR_V4SI_UNS VOR_V4SI_U
vbi __builtin_vec_or (vbi, vbi);
VOR_V4SI_UNS VOR_V4SI_B
+ vui __builtin_vec_or (vui, vbi);
+ VOR_V4SI_UNS VOR_V4SI_UB
+ vui __builtin_vec_or (vui, vbi);
+ VOR_V4SI_UNS VOR_V4SI_BU
vsll __builtin_vec_or (vsll, vsll);
VOR_V2DI
+ vsll __builtin_vec_or (vsll, vbll);
+ VOR_V2DI VOR_VSLL_VBLL
+ vsll __builtin_vec_or (vbll, vsll);
+ VOR_V2DI VOR_VBLL_VSLL
vull __builtin_vec_or (vull, vull);
VOR_V2DI_UNS VOR_V2DI_U
vbll __builtin_vec_or (vbll, vbll);
VOR_V2DI_UNS VOR_V2DI_B
+ vull __builtin_vec_or (vull, vbll);
+ VOR_V2DI_UNS VOR_V2DI_UB
+ vull __builtin_vec_or (vbll, vull);
+ VOR_V2DI_UNS VOR_V2DI_BU
vf __builtin_vec_or (vf, vf);
VOR_V4SF
+ vf __builtin_vec_or (vf, vbi);
+ VOR_V4SF VOR_VF_VBI
+ vf __builtin_vec_or (vbi, vf);
+ VOR_V4SF VOR_VBI_VF
vd __builtin_vec_or (vd, vd);
VOR_V2DF
+ vd __builtin_vec_or (vd, vbll);
+ VOR_V2DF VOR_VD_VBLL
+ vd __builtin_vec_or (vbll, vd);
+ VOR_V2DF VOR_VBLL_VD
[VEC_ORC, vec_orc, __builtin_vec_orc, _ARCH_PWR8]
vsc __builtin_vec_orc (vsc, vsc);
@@ -3625,7 +3665,7 @@
signed int __builtin_vec_scalar_cmp_exp_lt (_Float128, _Float128);
VSCEQPLT
-[VEC_VSCEUO, scalar_cmp_exp_unordered, __builtin_vec_scalar_cmp_exp_unordered, ARCH_PWR9]
+[VEC_VSCEUO, scalar_cmp_exp_unordered, __builtin_vec_scalar_cmp_exp_unordered, _ARCH_PWR9]
signed int __builtin_vec_scalar_cmp_exp_unordered (double, double);
VSCEDPUO
signed int __builtin_vec_scalar_cmp_exp_unordered (_Float128, _Float128);
@@ -3638,17 +3678,17 @@
VSEEQP
[VEC_VSES, scalar_extract_sig, __builtin_vec_scalar_extract_sig, _ARCH_PWR9]
- unsigned int __builtin_vec_scalar_extract_sig (double);
+ unsigned long long __builtin_vec_scalar_extract_sig (double);
VSESDP
- unsigned int __builtin_vec_scalar_extract_sig (_Float128);
+ unsigned __int128 __builtin_vec_scalar_extract_sig (_Float128);
VSESQP
[VEC_VSIE, scalar_insert_exp, __builtin_vec_scalar_insert_exp, _ARCH_PWR9]
- double __builtin_vec_scalar_insert_exp (unsigned int, unsigned int);
+ double __builtin_vec_scalar_insert_exp (unsigned long long, unsigned long long);
VSIEDP
- double __builtin_vec_scalar_insert_exp (double, unsigned int);
+ double __builtin_vec_scalar_insert_exp (double, unsigned long long);
VSIEDPF
- _Float128 __builtin_vec_scalar_insert_exp (unsigned long long, unsigned long long);
+ _Float128 __builtin_vec_scalar_insert_exp (unsigned __int128, unsigned long long);
VSIEQP
_Float128 __builtin_vec_scalar_insert_exp (_Float128, unsigned long long);
VSIEQPF
diff --git a/gcc/testsuite/gcc.dg/vmx/ops.c b/gcc/testsuite/gcc.dg/vmx/ops.c
index 5ba559e6f4b..7b56e9d8afa 100644
--- a/gcc/testsuite/gcc.dg/vmx/ops.c
+++ b/gcc/testsuite/gcc.dg/vmx/ops.c
@@ -192,42 +192,8 @@ void f2() {
*var_vec_b16++ = vec_splat(var_vec_b16[0], 7);
}
void f3() {
- *var_vec_b16++ = vec_srl(var_vec_b16[0], var_vec_u16[1]);
- *var_vec_b16++ = vec_srl(var_vec_b16[0], var_vec_u32[1]);
- *var_vec_b16++ = vec_srl(var_vec_b16[0], var_vec_u8[1]);
*var_vec_b16++ = vec_unpackh(var_vec_b8[0]);
*var_vec_b16++ = vec_unpackl(var_vec_b8[0]);
- *var_vec_b16++ = vec_vand(var_vec_b16[0], var_vec_b16[1]);
- *var_vec_b16++ = vec_vandc(var_vec_b16[0], var_vec_b16[1]);
- *var_vec_b16++ = vec_vcmpequh(var_vec_s16[0], var_vec_s16[1]);
- *var_vec_b16++ = vec_vcmpequh(var_vec_u16[0], var_vec_u16[1]);
- *var_vec_b16++ = vec_vcmpgtsh(var_vec_s16[0], var_vec_s16[1]);
- *var_vec_b16++ = vec_vcmpgtuh(var_vec_u16[0], var_vec_u16[1]);
- *var_vec_b16++ = vec_vmrghh(var_vec_b16[0], var_vec_b16[1]);
- *var_vec_b16++ = vec_vmrglh(var_vec_b16[0], var_vec_b16[1]);
- *var_vec_b16++ = vec_vnor(var_vec_b16[0], var_vec_b16[1]);
- *var_vec_b16++ = vec_vor(var_vec_b16[0], var_vec_b16[1]);
- *var_vec_b16++ = vec_vperm(var_vec_b16[0], var_vec_b16[1], var_vec_u8[2]);
- *var_vec_b16++ = vec_vpkuwum(var_vec_b32[0], var_vec_b32[1]);
- *var_vec_b16++ = vec_vsel(var_vec_b16[0], var_vec_b16[1], var_vec_b16[2]);
- *var_vec_b16++ = vec_vsel(var_vec_b16[0], var_vec_b16[1], var_vec_u16[2]);
- *var_vec_b16++ = vec_vsl(var_vec_b16[0], var_vec_u16[1]);
- *var_vec_b16++ = vec_vsl(var_vec_b16[0], var_vec_u32[1]);
- *var_vec_b16++ = vec_vsl(var_vec_b16[0], var_vec_u8[1]);
- *var_vec_b16++ = vec_vsplth(var_vec_b16[0], 0);
- *var_vec_b16++ = vec_vsplth(var_vec_b16[0], 1);
- *var_vec_b16++ = vec_vsplth(var_vec_b16[0], 2);
- *var_vec_b16++ = vec_vsplth(var_vec_b16[0], 3);
- *var_vec_b16++ = vec_vsplth(var_vec_b16[0], 4);
- *var_vec_b16++ = vec_vsplth(var_vec_b16[0], 5);
- *var_vec_b16++ = vec_vsplth(var_vec_b16[0], 6);
- *var_vec_b16++ = vec_vsplth(var_vec_b16[0], 7);
- *var_vec_b16++ = vec_vsr(var_vec_b16[0], var_vec_u16[1]);
- *var_vec_b16++ = vec_vsr(var_vec_b16[0], var_vec_u32[1]);
- *var_vec_b16++ = vec_vsr(var_vec_b16[0], var_vec_u8[1]);
- *var_vec_b16++ = vec_vupkhsb(var_vec_b8[0]);
- *var_vec_b16++ = vec_vupklsb(var_vec_b8[0]);
- *var_vec_b16++ = vec_vxor(var_vec_b16[0], var_vec_b16[1]);
*var_vec_b16++ = vec_xor(var_vec_b16[0], var_vec_b16[1]);
*var_vec_b32++ = vec_and(var_vec_b32[0], var_vec_b32[1]);
*var_vec_b32++ = vec_andc(var_vec_b32[0], var_vec_b32[1]);
@@ -255,40 +221,8 @@ void f3() {
*var_vec_b32++ = vec_splat(var_vec_b32[0], 3);
}
void f4() {
- *var_vec_b32++ = vec_srl(var_vec_b32[0], var_vec_u16[1]);
- *var_vec_b32++ = vec_srl(var_vec_b32[0], var_vec_u32[1]);
- *var_vec_b32++ = vec_srl(var_vec_b32[0], var_vec_u8[1]);
*var_vec_b32++ = vec_unpackh(var_vec_b16[0]);
*var_vec_b32++ = vec_unpackl(var_vec_b16[0]);
- *var_vec_b32++ = vec_vand(var_vec_b32[0], var_vec_b32[1]);
- *var_vec_b32++ = vec_vandc(var_vec_b32[0], var_vec_b32[1]);
- *var_vec_b32++ = vec_vcmpeqfp(var_vec_f32[0], var_vec_f32[1]);
- *var_vec_b32++ = vec_vcmpequw(var_vec_s32[0], var_vec_s32[1]);
- *var_vec_b32++ = vec_vcmpequw(var_vec_u32[0], var_vec_u32[1]);
- *var_vec_b32++ = vec_vcmpgefp(var_vec_f32[0], var_vec_f32[1]);
- *var_vec_b32++ = vec_vcmpgtfp(var_vec_f32[0], var_vec_f32[1]);
- *var_vec_b32++ = vec_vcmpgtsw(var_vec_s32[0], var_vec_s32[1]);
- *var_vec_b32++ = vec_vcmpgtuw(var_vec_u32[0], var_vec_u32[1]);
- *var_vec_b32++ = vec_vmrghw(var_vec_b32[0], var_vec_b32[1]);
- *var_vec_b32++ = vec_vmrglw(var_vec_b32[0], var_vec_b32[1]);
- *var_vec_b32++ = vec_vnor(var_vec_b32[0], var_vec_b32[1]);
- *var_vec_b32++ = vec_vor(var_vec_b32[0], var_vec_b32[1]);
- *var_vec_b32++ = vec_vperm(var_vec_b32[0], var_vec_b32[1], var_vec_u8[2]);
- *var_vec_b32++ = vec_vsel(var_vec_b32[0], var_vec_b32[1], var_vec_b32[2]);
- *var_vec_b32++ = vec_vsel(var_vec_b32[0], var_vec_b32[1], var_vec_u32[2]);
- *var_vec_b32++ = vec_vsl(var_vec_b32[0], var_vec_u16[1]);
- *var_vec_b32++ = vec_vsl(var_vec_b32[0], var_vec_u32[1]);
- *var_vec_b32++ = vec_vsl(var_vec_b32[0], var_vec_u8[1]);
- *var_vec_b32++ = vec_vspltw(var_vec_b32[0], 0);
- *var_vec_b32++ = vec_vspltw(var_vec_b32[0], 1);
- *var_vec_b32++ = vec_vspltw(var_vec_b32[0], 2);
- *var_vec_b32++ = vec_vspltw(var_vec_b32[0], 3);
- *var_vec_b32++ = vec_vsr(var_vec_b32[0], var_vec_u16[1]);
- *var_vec_b32++ = vec_vsr(var_vec_b32[0], var_vec_u32[1]);
- *var_vec_b32++ = vec_vsr(var_vec_b32[0], var_vec_u8[1]);
- *var_vec_b32++ = vec_vupkhsh(var_vec_b16[0]);
- *var_vec_b32++ = vec_vupklsh(var_vec_b16[0]);
- *var_vec_b32++ = vec_vxor(var_vec_b32[0], var_vec_b32[1]);
*var_vec_b32++ = vec_xor(var_vec_b32[0], var_vec_b32[1]);
*var_vec_b8++ = vec_and(var_vec_b8[0], var_vec_b8[1]);
*var_vec_b8++ = vec_andc(var_vec_b8[0], var_vec_b8[1]);
@@ -324,46 +258,6 @@ void f5() {
*var_vec_b8++ = vec_splat(var_vec_b8[0], 13);
*var_vec_b8++ = vec_splat(var_vec_b8[0], 14);
*var_vec_b8++ = vec_splat(var_vec_b8[0], 15);
- *var_vec_b8++ = vec_srl(var_vec_b8[0], var_vec_u16[1]);
- *var_vec_b8++ = vec_srl(var_vec_b8[0], var_vec_u32[1]);
- *var_vec_b8++ = vec_srl(var_vec_b8[0], var_vec_u8[1]);
- *var_vec_b8++ = vec_vand(var_vec_b8[0], var_vec_b8[1]);
- *var_vec_b8++ = vec_vandc(var_vec_b8[0], var_vec_b8[1]);
- *var_vec_b8++ = vec_vcmpequb(var_vec_s8[0], var_vec_s8[1]);
- *var_vec_b8++ = vec_vcmpequb(var_vec_u8[0], var_vec_u8[1]);
- *var_vec_b8++ = vec_vcmpgtsb(var_vec_s8[0], var_vec_s8[1]);
- *var_vec_b8++ = vec_vcmpgtub(var_vec_u8[0], var_vec_u8[1]);
- *var_vec_b8++ = vec_vmrghb(var_vec_b8[0], var_vec_b8[1]);
- *var_vec_b8++ = vec_vmrglb(var_vec_b8[0], var_vec_b8[1]);
- *var_vec_b8++ = vec_vnor(var_vec_b8[0], var_vec_b8[1]);
- *var_vec_b8++ = vec_vor(var_vec_b8[0], var_vec_b8[1]);
- *var_vec_b8++ = vec_vperm(var_vec_b8[0], var_vec_b8[1], var_vec_u8[2]);
- *var_vec_b8++ = vec_vpkuhum(var_vec_b16[0], var_vec_b16[1]);
- *var_vec_b8++ = vec_vsel(var_vec_b8[0], var_vec_b8[1], var_vec_b8[2]);
- *var_vec_b8++ = vec_vsel(var_vec_b8[0], var_vec_b8[1], var_vec_u8[2]);
- *var_vec_b8++ = vec_vsl(var_vec_b8[0], var_vec_u16[1]);
- *var_vec_b8++ = vec_vsl(var_vec_b8[0], var_vec_u32[1]);
- *var_vec_b8++ = vec_vsl(var_vec_b8[0], var_vec_u8[1]);
- *var_vec_b8++ = vec_vspltb(var_vec_b8[0], 0);
- *var_vec_b8++ = vec_vspltb(var_vec_b8[0], 1);
- *var_vec_b8++ = vec_vspltb(var_vec_b8[0], 2);
- *var_vec_b8++ = vec_vspltb(var_vec_b8[0], 3);
- *var_vec_b8++ = vec_vspltb(var_vec_b8[0], 4);
- *var_vec_b8++ = vec_vspltb(var_vec_b8[0], 5);
- *var_vec_b8++ = vec_vspltb(var_vec_b8[0], 6);
- *var_vec_b8++ = vec_vspltb(var_vec_b8[0], 7);
- *var_vec_b8++ = vec_vspltb(var_vec_b8[0], 8);
- *var_vec_b8++ = vec_vspltb(var_vec_b8[0], 9);
- *var_vec_b8++ = vec_vspltb(var_vec_b8[0], 10);
- *var_vec_b8++ = vec_vspltb(var_vec_b8[0], 11);
- *var_vec_b8++ = vec_vspltb(var_vec_b8[0], 12);
- *var_vec_b8++ = vec_vspltb(var_vec_b8[0], 13);
- *var_vec_b8++ = vec_vspltb(var_vec_b8[0], 14);
- *var_vec_b8++ = vec_vspltb(var_vec_b8[0], 15);
- *var_vec_b8++ = vec_vsr(var_vec_b8[0], var_vec_u16[1]);
- *var_vec_b8++ = vec_vsr(var_vec_b8[0], var_vec_u32[1]);
- *var_vec_b8++ = vec_vsr(var_vec_b8[0], var_vec_u8[1]);
- *var_vec_b8++ = vec_vxor(var_vec_b8[0], var_vec_b8[1]);
*var_vec_b8++ = vec_xor(var_vec_b8[0], var_vec_b8[1]);
}
void f6() {
@@ -525,8 +419,6 @@ void f9() {
*var_vec_p16++ = vec_splat(var_vec_p16[0], 5);
*var_vec_p16++ = vec_splat(var_vec_p16[0], 6);
*var_vec_p16++ = vec_splat(var_vec_p16[0], 7);
- *var_vec_p16++ = vec_srl(var_vec_p16[0], var_vec_u16[1]);
- *var_vec_p16++ = vec_srl(var_vec_p16[0], var_vec_u32[1]);
*var_vec_p16++ = vec_srl(var_vec_p16[0], var_vec_u8[1]);
*var_vec_p16++ = vec_sro(var_vec_p16[0], var_vec_s8[1]);
*var_vec_p16++ = vec_sro(var_vec_p16[0], var_vec_u8[1]);
@@ -631,8 +523,6 @@ void f11() {
*var_vec_s16++ = vec_splat_s16(-16);
*var_vec_s16++ = vec_sr(var_vec_s16[0], var_vec_u16[1]);
*var_vec_s16++ = vec_sra(var_vec_s16[0], var_vec_u16[1]);
- *var_vec_s16++ = vec_srl(var_vec_s16[0], var_vec_u16[1]);
- *var_vec_s16++ = vec_srl(var_vec_s16[0], var_vec_u32[1]);
*var_vec_s16++ = vec_srl(var_vec_s16[0], var_vec_u8[1]);
*var_vec_s16++ = vec_sro(var_vec_s16[0], var_vec_s8[1]);
*var_vec_s16++ = vec_sro(var_vec_s16[0], var_vec_u8[1]);
@@ -771,8 +661,6 @@ void f14() {
}
void f15() {
*var_vec_s32++ = vec_sra(var_vec_s32[0], var_vec_u32[1]);
- *var_vec_s32++ = vec_srl(var_vec_s32[0], var_vec_u16[1]);
- *var_vec_s32++ = vec_srl(var_vec_s32[0], var_vec_u32[1]);
*var_vec_s32++ = vec_srl(var_vec_s32[0], var_vec_u8[1]);
*var_vec_s32++ = vec_sro(var_vec_s32[0], var_vec_s8[1]);
*var_vec_s32++ = vec_sro(var_vec_s32[0], var_vec_u8[1]);
@@ -891,8 +779,6 @@ void f18() {
*var_vec_s8++ = vec_splat_s8(-16);
*var_vec_s8++ = vec_sr(var_vec_s8[0], var_vec_u8[1]);
*var_vec_s8++ = vec_sra(var_vec_s8[0], var_vec_u8[1]);
- *var_vec_s8++ = vec_srl(var_vec_s8[0], var_vec_u16[1]);
- *var_vec_s8++ = vec_srl(var_vec_s8[0], var_vec_u32[1]);
*var_vec_s8++ = vec_srl(var_vec_s8[0], var_vec_u8[1]);
*var_vec_s8++ = vec_sro(var_vec_s8[0], var_vec_s8[1]);
*var_vec_s8++ = vec_sro(var_vec_s8[0], var_vec_u8[1]);
@@ -1002,8 +888,6 @@ void f21() {
*var_vec_u16++ = vec_splat_u16(-16);
*var_vec_u16++ = vec_sr(var_vec_u16[0], var_vec_u16[1]);
*var_vec_u16++ = vec_sra(var_vec_u16[0], var_vec_u16[1]);
- *var_vec_u16++ = vec_srl(var_vec_u16[0], var_vec_u16[1]);
- *var_vec_u16++ = vec_srl(var_vec_u16[0], var_vec_u32[1]);
*var_vec_u16++ = vec_srl(var_vec_u16[0], var_vec_u8[1]);
*var_vec_u16++ = vec_sro(var_vec_u16[0], var_vec_s8[1]);
*var_vec_u16++ = vec_sro(var_vec_u16[0], var_vec_u8[1]);
@@ -1140,8 +1024,6 @@ void f23() {
*var_vec_u32++ = vec_sra(var_vec_u32[0], var_vec_u32[1]);
}
void f24() {
- *var_vec_u32++ = vec_srl(var_vec_u32[0], var_vec_u16[1]);
- *var_vec_u32++ = vec_srl(var_vec_u32[0], var_vec_u32[1]);
*var_vec_u32++ = vec_srl(var_vec_u32[0], var_vec_u8[1]);
*var_vec_u32++ = vec_sro(var_vec_u32[0], var_vec_s8[1]);
*var_vec_u32++ = vec_sro(var_vec_u32[0], var_vec_u8[1]);
@@ -1274,8 +1156,6 @@ void f27() {
*var_vec_u8++ = vec_splat_u8(-16);
*var_vec_u8++ = vec_sr(var_vec_u8[0], var_vec_u8[1]);
*var_vec_u8++ = vec_sra(var_vec_u8[0], var_vec_u8[1]);
- *var_vec_u8++ = vec_srl(var_vec_u8[0], var_vec_u16[1]);
- *var_vec_u8++ = vec_srl(var_vec_u8[0], var_vec_u32[1]);
*var_vec_u8++ = vec_srl(var_vec_u8[0], var_vec_u8[1]);
*var_vec_u8++ = vec_sro(var_vec_u8[0], var_vec_s8[1]);
*var_vec_u8++ = vec_sro(var_vec_u8[0], var_vec_u8[1]);
^ permalink raw reply [flat|nested] 29+ messages in thread
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