From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1725) id 7A75C396E850; Thu, 14 Jan 2021 23:07:16 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 7A75C396E850 Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: William Schmidt To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/wschmidt/heads/builtins4)] rs6000: More bug fixes X-Act-Checkin: gcc X-Git-Author: Bill Schmidt X-Git-Refname: refs/users/wschmidt/heads/builtins4 X-Git-Oldrev: 20bd4638aba09d1077f585a00e42d4cfb312fb38 X-Git-Newrev: 37e08634788ae74488be734f9cce3a87e9be96bc Message-Id: <20210114230716.7A75C396E850@sourceware.org> Date: Thu, 14 Jan 2021 23:07:16 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 14 Jan 2021 23:07:16 -0000 https://gcc.gnu.org/g:37e08634788ae74488be734f9cce3a87e9be96bc commit 37e08634788ae74488be734f9cce3a87e9be96bc Author: Bill Schmidt Date: Thu Jan 14 17:06:55 2021 -0600 rs6000: More bug fixes 2021-01-14 Bill Schmidt gcc/ * config/rs6000/rs6000-builtin-new.def: Assorted fixes. * config/rs6000/rs6000-overload.def: Assorted fixes. gcc/testsuite/ * gcc.target/powerpc/altivec-7.c: Adjust. * gcc.target/powerpc/cmpb-2.c: Adjust. * gcc.target/powerpc/cmpb32-2.c: Adjust. * gcc.target/powerpc/fold-vec-mule-misc.c: Adjust. * gcc.target/powerpc/fold-vec-splat-floatdouble.c: Adjust. * gcc.target/powerpc/fold-vec-splat-longlong.c: Adjust. * gcc.target/powerpc/fold-vec-splat-misc-invalid.c: Adjust. * gcc.target/powerpc/p8vector-builtin-2.c: Adjust. * gcc.target/powerpc/p8vector-builtin-3.c: Adjust. * gcc.target/powerpc/p8vector-builtin-4.c: Adjust. * gcc.target/powerpc/p8vector-builtin-7.c: Adjust. Diff: --- gcc/config/rs6000/altivec.h | 2 + gcc/config/rs6000/rs6000-builtin-new.def | 24 ++-- gcc/config/rs6000/rs6000-overload.def | 11 +- gcc/testsuite/gcc.target/powerpc/altivec-7.c | 2 +- gcc/testsuite/gcc.target/powerpc/cmpb-2.c | 2 +- gcc/testsuite/gcc.target/powerpc/cmpb32-2.c | 2 +- .../gcc.target/powerpc/fold-vec-mule-misc.c | 8 +- .../powerpc/fold-vec-splat-floatdouble.c | 4 +- .../gcc.target/powerpc/fold-vec-splat-longlong.c | 10 +- .../powerpc/fold-vec-splat-misc-invalid.c | 8 +- .../gcc.target/powerpc/p8vector-builtin-2.c | 55 --------- .../gcc.target/powerpc/p8vector-builtin-3.c | 27 +---- .../gcc.target/powerpc/p8vector-builtin-4.c | 124 ++++----------------- .../gcc.target/powerpc/p8vector-builtin-7.c | 8 +- 14 files changed, 61 insertions(+), 226 deletions(-) diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h index 0eae8a6404a..8904d2c545d 100644 --- a/gcc/config/rs6000/altivec.h +++ b/gcc/config/rs6000/altivec.h @@ -66,6 +66,8 @@ /* VSX additions */ #define vec_vsx_ld __builtin_vec_vsx_ld #define vec_vsx_st __builtin_vec_vsx_st +#define __builtin_vec_xl __builtin_vec_vsx_ld +#define __builtin_vec_xst __builtin_vec_vsx_st #define __builtin_bcdadd_ofl __builtin_vec_bcdadd_ov #define __builtin_bcdsub_ofl __builtin_vec_bcdsub_ov diff --git a/gcc/config/rs6000/rs6000-builtin-new.def b/gcc/config/rs6000/rs6000-builtin-new.def index 9c4470bf400..449dcd5e257 100644 --- a/gcc/config/rs6000/rs6000-builtin-new.def +++ b/gcc/config/rs6000/rs6000-builtin-new.def @@ -805,13 +805,13 @@ const vus __builtin_altivec_vpkswus (vsi, vsi); VPKSWUS altivec_vpkswus {} - const vuc __builtin_altivec_vpkuhum (vus, vus); + const vsc __builtin_altivec_vpkuhum (vss, vss); VPKUHUM altivec_vpkuhum {} const vuc __builtin_altivec_vpkuhus (vus, vus); VPKUHUS altivec_vpkuhus {} - const vus __builtin_altivec_vpkuwum (vui, vui); + const vss __builtin_altivec_vpkuwum (vsi, vsi); VPKUWUM altivec_vpkuwum {} const vus __builtin_altivec_vpkuwus (vui, vui); @@ -1219,7 +1219,7 @@ const vsll __builtin_altivec_vreve_v2di (vsll); VREVE_V2DI altivec_vrevev2di2 {} - const vd __builtin_altivec_vsel_2df (vd, vd, vull); + const vd __builtin_altivec_vsel_2df (vd, vd, vd); VSEL_2DF vector_select_v2df {} const vsll __builtin_altivec_vsel_2di (vsll, vsll, vull); @@ -2263,7 +2263,7 @@ const vui __builtin_altivec_vpksdus (vsll, vsll); VPKSDUS altivec_vpksdus {} - const vui __builtin_altivec_vpkudum (vull, vull); + const vsi __builtin_altivec_vpkudum (vsll, vsll); VPKUDUM altivec_vpkudum {} const vui __builtin_altivec_vpkudus (vull, vull); @@ -2285,13 +2285,13 @@ ; const vull __builtin_altivec_vpmsumw (vui, vui); ; VPMSUMW crypto_vpmsumw {} - const vuc __builtin_altivec_vpopcntb (vsc); + const vsc __builtin_altivec_vpopcntb (vsc); VPOPCNTB popcountv16qi2 {} - const vull __builtin_altivec_vpopcntd (vsll); + const vsll __builtin_altivec_vpopcntd (vsll); VPOPCNTD popcountv2di2 {} - const vus __builtin_altivec_vpopcnth (vss); + const vss __builtin_altivec_vpopcnth (vss); VPOPCNTH popcountv8hi2 {} const vuc __builtin_altivec_vpopcntub (vuc); @@ -2306,16 +2306,16 @@ const vui __builtin_altivec_vpopcntuw (vui); VPOPCNTUW popcountv4si2 {} - const vui __builtin_altivec_vpopcntw (vsi); + const vsi __builtin_altivec_vpopcntw (vsi); VPOPCNTW popcountv4si2 {} - const vsll __builtin_altivec_vrld (vsll, vull); + const vsll __builtin_altivec_vrld (vsll, vsll); VRLD vrotlv2di3 {} - const vsll __builtin_altivec_vsld (vsll, vull); + const vsll __builtin_altivec_vsld (vsll, vsll); VSLD vashlv2di3 {} - const vsll __builtin_altivec_vsrad (vsll, vull); + const vsll __builtin_altivec_vsrad (vsll, vsll); VSRAD vashrv2di3 {} const vsll __builtin_altivec_vsrd (vsll, vull); @@ -2330,7 +2330,7 @@ const vuq __builtin_altivec_vsubeuqm (vuq, vuq, vuq); VSUBEUQM altivec_vsubeuqm {} - const vull __builtin_altivec_vsubudm (vull, vull); + const vsll __builtin_altivec_vsubudm (vsll, vsll); VSUBUDM subv2di3 {} const vuq __builtin_altivec_vsubuqm (vuq, vuq); diff --git a/gcc/config/rs6000/rs6000-overload.def b/gcc/config/rs6000/rs6000-overload.def index e80e163f8ec..f6e43b88e07 100644 --- a/gcc/config/rs6000/rs6000-overload.def +++ b/gcc/config/rs6000/rs6000-overload.def @@ -3830,7 +3830,7 @@ void __builtin_vec_stl (vd, signed long long, double *); STVXL_V2DF STVXL_D -[VEC_STRIL, vec_stril, __builtin_vec_stril, ARCH_PWR10] +[VEC_STRIL, vec_stril, __builtin_vec_stril, _ARCH_PWR10] vuc __builtin_vec_stril (vuc); VSTRIBL VSTRIBL_U vsc __builtin_vec_stril (vsc); @@ -3860,7 +3860,7 @@ vss __builtin_vec_strir (vss); VSTRIHR VSTRIHR_S -[VEC_STRIR_P, vec_strir_p, __builtin_vec_strir_p, ARCH_PWR10] +[VEC_STRIR_P, vec_strir_p, __builtin_vec_strir_p, _ARCH_PWR10] signed int __builtin_vec_strir_p (vuc); VSTRIBR_P VSTRIBR_PU signed int __builtin_vec_strir_p (vsc); @@ -4131,11 +4131,8 @@ VSUBEUQM VSUBEUQM_VUQ ; TODO: Note that the entry for VEC_SUBEC currently gets ignored in -; altivec_resolve_overloaded_builtin. There are also forms for -; vsi and vui arguments, but rather than building a define_expand -; for the instruction sequence generated for those, we do some RTL -; hackery. Revisit whether we can remove that. For now, keep this -; much of the entry here to generate the #define, at least. +; altivec_resolve_overloaded_builtin. Revisit whether we can remove +; that. We still need to register the legal builtin forms here. [VEC_SUBEC, vec_subec, __builtin_vec_subec] vsq __builtin_vec_subec (vsq, vsq, vsq); VSUBECUQ VSUBECUQ_VSQ diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-7.c b/gcc/testsuite/gcc.target/powerpc/altivec-7.c index 46bf7148b20..52f5ecc8d59 100644 --- a/gcc/testsuite/gcc.target/powerpc/altivec-7.c +++ b/gcc/testsuite/gcc.target/powerpc/altivec-7.c @@ -84,7 +84,7 @@ int main () /* { dg-final { scan-assembler-times {\mlvx\M} 39 { target { ! powerpc_vsx } } } } */ /* { dg-final { scan-assembler-times {\mlxv} 0 { target { ! powerpc_vsx } } } } */ /* { dg-final { scan-assembler-times {\mlvx\M} 0 { target powerpc_vsx } } } */ -/* { dg-final { scan-assembler-times {\mlxv} 42 { target powerpc_vsx } } } */ +/* { dg-final { scan-assembler-times {\mlxv} 39 { target powerpc_vsx } } } */ /* { dg-final { scan-assembler-times "lvewx" 1 } } */ /* { dg-final { scan-assembler-times "lvxl" 1 } } */ /* { dg-final { scan-assembler-times "vupklsh" 2 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/cmpb-2.c b/gcc/testsuite/gcc.target/powerpc/cmpb-2.c index 113ab6a5f99..02b84d0731d 100644 --- a/gcc/testsuite/gcc.target/powerpc/cmpb-2.c +++ b/gcc/testsuite/gcc.target/powerpc/cmpb-2.c @@ -8,7 +8,7 @@ void abort (); unsigned long long int do_compare (unsigned long long int a, unsigned long long int b) { - return __builtin_cmpb (a, b); /* { dg-warning "implicit declaration of function '__builtin_cmpb'" } */ + return __builtin_cmpb (a, b); /* { dg-error "'__builtin_p6_cmpb' requires the '-mcpu=power6' option" } */ } void diff --git a/gcc/testsuite/gcc.target/powerpc/cmpb32-2.c b/gcc/testsuite/gcc.target/powerpc/cmpb32-2.c index 37b54745e0e..d4264ab6e7d 100644 --- a/gcc/testsuite/gcc.target/powerpc/cmpb32-2.c +++ b/gcc/testsuite/gcc.target/powerpc/cmpb32-2.c @@ -7,7 +7,7 @@ void abort (); unsigned int do_compare (unsigned int a, unsigned int b) { - return __builtin_cmpb (a, b); /* { dg-warning "implicit declaration of function '__builtin_cmpb'" } */ + return __builtin_cmpb (a, b); /* { dg-error "'__builtin_p6_cmpb_32' requires the '-mcpu=power6' option" } */ } void diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-mule-misc.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-mule-misc.c index 7daf30215b8..19a5d044c4d 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-mule-misc.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-mule-misc.c @@ -11,7 +11,7 @@ test_eub_char () { volatile vector unsigned char v0 = {1, 0, 0, 0, 0, 0, 0, 0}; volatile vector unsigned char v1 = {0xff, 0, 0, 0, 0, 0, 0, 0}; - vector unsigned short res = vec_vmuleub (v0, v1); + vector unsigned short res = vec_mule (v0, v1); if (res[0] != (unsigned short)v0[0] * (unsigned short)v1[0]) __builtin_abort (); } @@ -21,7 +21,7 @@ test_oub_char () { volatile vector unsigned char v0 = {0, 1, 0, 0, 0, 0, 0, 0}; volatile vector unsigned char v1 = {0, 0xff, 0, 0, 0, 0, 0, 0}; - vector unsigned short res = vec_vmuloub (v0, v1); + vector unsigned short res = vec_mulo (v0, v1); if (res[0] != (unsigned short)v0[1] * (unsigned short)v1[1]) __builtin_abort (); } @@ -31,7 +31,7 @@ test_euh_short () { volatile vector unsigned short v0 = {1, 0, 0, 0}; volatile vector unsigned short v1 = {0xff, 0, 0, 0}; - vector unsigned int res = vec_vmuleuh (v0, v1); + vector unsigned int res = vec_mule (v0, v1); if (res[0] != (unsigned int)v0[0] * (unsigned int)v1[0]) __builtin_abort (); } @@ -41,7 +41,7 @@ test_ouh_short () { volatile vector unsigned short v0 = {0, 1, 0, 0}; volatile vector unsigned short v1 = {0, 0xff, 0, 0}; - vector unsigned int res = vec_vmulouh (v0, v1); + vector unsigned int res = vec_mulo (v0, v1); if (res[0] != (unsigned int)v0[1] * (unsigned int)v1[1]) __builtin_abort (); } diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-floatdouble.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-floatdouble.c index ab396967c3d..3f22ba31862 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-floatdouble.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-floatdouble.c @@ -18,7 +18,7 @@ vector float test_fc () vector double testd_00 (vector double x) { return vec_splat (x, 0b00000); } vector double testd_01 (vector double x) { return vec_splat (x, 0b00001); } vector double test_dc () -{ const vector double y = { 3.0, 5.0 }; return vec_splat (y, 0b00010); } +{ const vector double y = { 3.0, 5.0 }; return vec_splat (y, 0b00001); } /* If the source vector is a known constant, we will generate a load. */ /* { dg-final { scan-assembler-times {\mlvx\M|\mlxvd2x\M|\mlxv\M} 2 } } */ @@ -27,5 +27,5 @@ vector double test_dc () /* { dg-final { scan-assembler-times "vspltw|xxspltw" 3 } } */ /* For double types, we will generate xxpermdi instructions. */ -/* { dg-final { scan-assembler-times "xxpermdi" 3 } } */ +/* { dg-final { scan-assembler-times "xxpermdi" 2 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-longlong.c index 4fa06c85ecc..9376f702a7a 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-longlong.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-longlong.c @@ -9,23 +9,19 @@ vector bool long long testb_00 (vector bool long long x) { return vec_splat (x, 0b00000); } vector bool long long testb_01 (vector bool long long x) { return vec_splat (x, 0b00001); } -vector bool long long testb_02 (vector bool long long x) { return vec_splat (x, 0b00010); } vector signed long long tests_00 (vector signed long long x) { return vec_splat (x, 0b00000); } vector signed long long tests_01 (vector signed long long x) { return vec_splat (x, 0b00001); } -vector signed long long tests_02 (vector signed long long x) { return vec_splat (x, 0b00010); } vector unsigned long long testu_00 (vector unsigned long long x) { return vec_splat (x, 0b00000); } vector unsigned long long testu_01 (vector unsigned long long x) { return vec_splat (x, 0b00001); } -vector unsigned long long testu_02 (vector unsigned long long x) { return vec_splat (x, 0b00010); } /* Similar test as above, but the source vector is a known constant. */ -vector bool long long test_bll () { const vector bool long long y = {12, 23}; return vec_splat (y, 0b00010); } -vector signed long long test_sll () { const vector signed long long y = {34, 45}; return vec_splat (y, 0b00010); } -vector unsigned long long test_ull () { const vector unsigned long long y = {56, 67}; return vec_splat (y, 0b00010); } +vector bool long long test_bll () { const vector bool long long y = {12, 23}; return vec_splat (y, 0b00001); } +vector signed long long test_sll () { const vector signed long long y = {34, 45}; return vec_splat (y, 0b00001); } /* Assorted load instructions for the initialization with known constants. */ -/* { dg-final { scan-assembler-times {\mlvx\M|\mlxvd2x\M|\mlxv\M} 3 } } */ +/* { dg-final { scan-assembler-times {\mlvx\M|\mlxvd2x\M|\mlxv\M|\mxxspltib\M} 2 } } */ /* xxpermdi for vec_splat of long long vectors. At the time of this writing, the number of xxpermdi instructions diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-misc-invalid.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-misc-invalid.c index 20f5b05561e..263a1723d31 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-misc-invalid.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-misc-invalid.c @@ -10,24 +10,24 @@ vector signed short testss_1 (unsigned int ui) { - return vec_splat_s16 (ui);/* { dg-error "argument 1 must be a 5-bit signed literal" } */ + return vec_splat_s16 (ui);/* { dg-error "argument 1 must be a literal between -16 and 15, inclusive" } */ } vector unsigned short testss_2 (signed int si) { - return vec_splat_u16 (si);/* { dg-error "argument 1 must be a 5-bit signed literal" } */ + return vec_splat_u16 (si);/* { dg-error "argument 1 must be a literal between -16 and 15, inclusive" } */ } vector signed char testsc_1 (unsigned int ui) { - return vec_splat_s8 (ui); /* { dg-error "argument 1 must be a 5-bit signed literal" } */ + return vec_splat_s8 (ui); /* { dg-error "argument 1 must be a literal between -16 and 15, inclusive" } */ } vector unsigned char testsc_2 (signed int si) { - return vec_splat_u8 (si);/* { dg-error "argument 1 must be a 5-bit signed literal" } */ + return vec_splat_u8 (si);/* { dg-error "argument 1 must be a literal between -16 and 15, inclusive" } */ } diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c index 102e1d1f813..0259e364aa6 100644 --- a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c +++ b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c @@ -27,11 +27,6 @@ v_sign sign_add_2 (v_sign a, v_sign b) return vec_add (a, b); } -v_sign sign_add_3 (v_sign a, v_sign b) -{ - return vec_vaddudm (a, b); -} - v_sign sign_sub_1 (v_sign a, v_sign b) { return __builtin_altivec_vsubudm (a, b); @@ -43,11 +38,6 @@ v_sign sign_sub_2 (v_sign a, v_sign b) } -v_sign sign_sub_3 (v_sign a, v_sign b) -{ - return vec_vsubudm (a, b); -} - v_sign sign_min_1 (v_sign a, v_sign b) { return __builtin_altivec_vminsd (a, b); @@ -58,11 +48,6 @@ v_sign sign_min_2 (v_sign a, v_sign b) return vec_min (a, b); } -v_sign sign_min_3 (v_sign a, v_sign b) -{ - return vec_vminsd (a, b); -} - v_sign sign_max_1 (v_sign a, v_sign b) { return __builtin_altivec_vmaxsd (a, b); @@ -73,11 +58,6 @@ v_sign sign_max_2 (v_sign a, v_sign b) return vec_max (a, b); } -v_sign sign_max_3 (v_sign a, v_sign b) -{ - return vec_vmaxsd (a, b); -} - v_sign sign_abs (v_sign a) { return vec_abs (a); /* xor, vsubudm, vmaxsd. */ @@ -98,41 +78,21 @@ v_uns uns_add_2 (v_uns a, v_uns b) return vec_add (a, b); } -v_uns uns_add_3 (v_uns a, v_uns b) -{ - return vec_vaddudm (a, b); -} - v_uns uns_sub_2 (v_uns a, v_uns b) { return vec_sub (a, b); } -v_uns uns_sub_3 (v_uns a, v_uns b) -{ - return vec_vsubudm (a, b); -} - v_uns uns_min_2 (v_uns a, v_uns b) { return vec_min (a, b); } -v_uns uns_min_3 (v_uns a, v_uns b) -{ - return vec_vminud (a, b); -} - v_uns uns_max_2 (v_uns a, v_uns b) { return vec_max (a, b); } -v_uns uns_max_3 (v_uns a, v_uns b) -{ - return vec_vmaxud (a, b); -} - v_bool uns_eq (v_uns a, v_uns b) { return vec_cmpeq (a, b); @@ -168,21 +128,11 @@ v_sign sign_sl_2 (v_sign a, v_uns b) return vec_sl (a, b); } -v_sign sign_sl_3 (v_sign a, v_uns b) -{ - return vec_vsld (a, b); -} - v_uns uns_sl_2 (v_uns a, v_uns b) { return vec_sl (a, b); } -v_uns uns_sl_3 (v_uns a, v_uns b) -{ - return vec_vsld (a, b); -} - v_sign sign_sra_1 (v_sign a, v_sign b) { return __builtin_altivec_vsrad (a, b); @@ -193,11 +143,6 @@ v_sign sign_sra_2 (v_sign a, v_uns b) return vec_sra (a, b); } -v_sign sign_sra_3 (v_sign a, v_uns b) -{ - return vec_vsrad (a, b); -} - v_bchar vbchar_eq (v_bchar a, v_bchar b) { return vec_cmpeq (a, b); diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-3.c b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-3.c index 33304fe6132..ae6a3a8437b 100644 --- a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-3.c +++ b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-3.c @@ -37,11 +37,6 @@ vi_uns vi_pack_3 (vll_uns a, vll_uns b) return vec_pack (a, b); } -vi_sign vi_pack_4 (vll_sign a, vll_sign b) -{ - return vec_vpkudum (a, b); -} - vs_sign vs_pack_1 (vi_sign a, vi_sign b) { return __builtin_altivec_vpkuwum (a, b); @@ -52,11 +47,6 @@ vs_sign vs_pack_2 (vi_sign a, vi_sign b) return vec_pack (a, b); } -vs_sign vs_pack_3 (vi_sign a, vi_sign b) -{ - return vec_vpkuwum (a, b); -} - vc_sign vc_pack_1 (vs_sign a, vs_sign b) { return __builtin_altivec_vpkuhum (a, b); @@ -67,11 +57,6 @@ vc_sign vc_pack_2 (vs_sign a, vs_sign b) return vec_pack (a, b); } -vc_sign vc_pack_3 (vs_sign a, vs_sign b) -{ - return vec_vpkuhum (a, b); -} - vll_sign vll_unpack_hi_1 (vi_sign a) { return __builtin_altivec_vupkhsw (a); @@ -84,12 +69,7 @@ vll_sign vll_unpack_hi_2 (vi_sign a) vll_sign vll_unpack_hi_3 (vi_sign a) { - return __builtin_vec_vupkhsw (a); -} - -vll_sign vll_unpack_lo_1 (vi_sign a) -{ - return vec_vupklsw (a); + return __builtin_altivec_vupkhsw (a); } vll_sign vll_unpack_lo_2 (vi_sign a) @@ -97,11 +77,6 @@ vll_sign vll_unpack_lo_2 (vi_sign a) return vec_unpackl (a); } -vll_sign vll_unpack_lo_3 (vi_sign a) -{ - return vec_vupklsw (a); -} - /* { dg-final { scan-assembler-times "vpkudum" 4 } } */ /* { dg-final { scan-assembler-times "vpkuwum" 3 } } */ /* { dg-final { scan-assembler-times "vpkuhum" 3 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-4.c b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-4.c index 8329e2bae5a..2d2d141948f 100644 --- a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-4.c +++ b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-4.c @@ -28,22 +28,12 @@ vll_sign vll_clz_1 (vll_sign a) vll_sign vll_clz_2 (vll_sign a) { - return vec_vclz (a); -} - -vll_sign vll_clz_3 (vll_sign a) -{ - return vec_vclzd (a); + return vec_cntlz (a); } vll_uns vll_clz_4 (vll_uns a) { - return vec_vclz (a); -} - -vll_uns vll_clz_5 (vll_uns a) -{ - return vec_vclzd (a); + return vec_cntlz (a); } vi_sign vi_clz_1 (vi_sign a) @@ -53,22 +43,12 @@ vi_sign vi_clz_1 (vi_sign a) vi_sign vi_clz_2 (vi_sign a) { - return vec_vclz (a); -} - -vi_sign vi_clz_3 (vi_sign a) -{ - return vec_vclzw (a); + return vec_cntlz (a); } vi_uns vi_clz_4 (vi_uns a) { - return vec_vclz (a); -} - -vi_uns vi_clz_5 (vi_uns a) -{ - return vec_vclzw (a); + return vec_cntlz (a); } vs_sign vs_clz_1 (vs_sign a) @@ -78,22 +58,12 @@ vs_sign vs_clz_1 (vs_sign a) vs_sign vs_clz_2 (vs_sign a) { - return vec_vclz (a); -} - -vs_sign vs_clz_3 (vs_sign a) -{ - return vec_vclzh (a); + return vec_cntlz (a); } vs_uns vs_clz_4 (vs_uns a) { - return vec_vclz (a); -} - -vs_uns vs_clz_5 (vs_uns a) -{ - return vec_vclzh (a); + return vec_cntlz (a); } vc_sign vc_clz_1 (vc_sign a) @@ -103,22 +73,12 @@ vc_sign vc_clz_1 (vc_sign a) vc_sign vc_clz_2 (vc_sign a) { - return vec_vclz (a); -} - -vc_sign vc_clz_3 (vc_sign a) -{ - return vec_vclzb (a); + return vec_cntlz (a); } vc_uns vc_clz_4 (vc_uns a) { - return vec_vclz (a); -} - -vc_uns vc_clz_5 (vc_uns a) -{ - return vec_vclzb (a); + return vec_cntlz (a); } vll_sign vll_popcnt_1 (vll_sign a) @@ -126,24 +86,14 @@ vll_sign vll_popcnt_1 (vll_sign a) return __builtin_altivec_vpopcntd (a); } -vll_sign vll_popcnt_2 (vll_sign a) +vll_uns vll_popcnt_2 (vll_sign a) { - return vec_vpopcnt (a); -} - -vll_sign vll_popcnt_3 (vll_sign a) -{ - return vec_vpopcntd (a); + return vec_popcnt (a); } vll_uns vll_popcnt_4 (vll_uns a) { - return vec_vpopcnt (a); -} - -vll_uns vll_popcnt_5 (vll_uns a) -{ - return vec_vpopcntd (a); + return vec_popcnt (a); } vi_sign vi_popcnt_1 (vi_sign a) @@ -151,24 +101,14 @@ vi_sign vi_popcnt_1 (vi_sign a) return __builtin_altivec_vpopcntw (a); } -vi_sign vi_popcnt_2 (vi_sign a) +vi_uns vi_popcnt_2 (vi_sign a) { - return vec_vpopcnt (a); -} - -vi_sign vi_popcnt_3 (vi_sign a) -{ - return vec_vpopcntw (a); + return vec_popcnt (a); } vi_uns vi_popcnt_4 (vi_uns a) { - return vec_vpopcnt (a); -} - -vi_uns vi_popcnt_5 (vi_uns a) -{ - return vec_vpopcntw (a); + return vec_popcnt (a); } vs_sign vs_popcnt_1 (vs_sign a) @@ -176,24 +116,14 @@ vs_sign vs_popcnt_1 (vs_sign a) return __builtin_altivec_vpopcnth (a); } -vs_sign vs_popcnt_2 (vs_sign a) +vs_uns vs_popcnt_2 (vs_sign a) { - return vec_vpopcnt (a); -} - -vs_sign vs_popcnt_3 (vs_sign a) -{ - return vec_vpopcnth (a); + return vec_popcnt (a); } vs_uns vs_popcnt_4 (vs_uns a) { - return vec_vpopcnt (a); -} - -vs_uns vs_popcnt_5 (vs_uns a) -{ - return vec_vpopcnth (a); + return vec_popcnt (a); } vc_sign vc_popcnt_1 (vc_sign a) @@ -201,24 +131,14 @@ vc_sign vc_popcnt_1 (vc_sign a) return __builtin_altivec_vpopcntb (a); } -vc_sign vc_popcnt_2 (vc_sign a) +vc_uns vc_popcnt_2 (vc_sign a) { - return vec_vpopcnt (a); -} - -vc_sign vc_popcnt_3 (vc_sign a) -{ - return vec_vpopcntb (a); + return vec_popcnt (a); } vc_uns vc_popcnt_4 (vc_uns a) { - return vec_vpopcnt (a); -} - -vc_uns vc_popcnt_5 (vc_uns a) -{ - return vec_vpopcntb (a); + return vec_popcnt (a); } vc_uns vc_gbb_1 (vc_uns a) @@ -228,12 +148,12 @@ vc_uns vc_gbb_1 (vc_uns a) vc_sign vc_gbb_2 (vc_sign a) { - return vec_vgbbd (a); + return vec_gb (a); } vc_uns vc_gbb_3 (vc_uns a) { - return vec_vgbbd (a); + return vec_gb (a); } /* { dg-final { scan-assembler-times "vclzd" 5 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-7.c b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-7.c index fcfac7c50b1..f3035000fe7 100644 --- a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-7.c +++ b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-7.c @@ -10,22 +10,22 @@ typedef vector unsigned int v_uns; v_sign even_sign (v_sign a, v_sign b) { - return vec_vmrgew (a, b); + return vec_mergee (a, b); } v_uns even_uns (v_uns a, v_uns b) { - return vec_vmrgew (a, b); + return vec_mergee (a, b); } v_sign odd_sign (v_sign a, v_sign b) { - return vec_vmrgow (a, b); + return vec_mergeo (a, b); } v_uns odd_uns (v_uns a, v_uns b) { - return vec_vmrgow (a, b); + return vec_mergeo (a, b); } /* { dg-final { scan-assembler-times "vmrgew" 2 } } */