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From: William Schmidt <wschmidt@gcc.gnu.org>
To: gcc-cvs@gcc.gnu.org
Subject: [gcc(refs/users/wschmidt/heads/builtins4)] rs6000: More bug fixes
Date: Wed, 27 Jan 2021 16:07:18 +0000 (GMT) [thread overview]
Message-ID: <20210127160718.3B78E3846405@sourceware.org> (raw)
https://gcc.gnu.org/g:5865fad98276e06e5ac02354240e065befbf1242
commit 5865fad98276e06e5ac02354240e065befbf1242
Author: Bill Schmidt <wschmidt@linux.ibm.com>
Date: Wed Jan 27 10:06:53 2021 -0600
rs6000: More bug fixes
2021-01-27 Bill Schmidt <wschmidt@linux.ibm.com>
gcc/
* config/rs6000/altivec.h: Add some deprecated interfaces.
* config/rs6000/rs6000-builtin-new.def: Miscellaneous fixes.
* config/rs6000/rs6000-c.c
(altivec_resolve_new_overloaded_builtin): Add missing break
statements.
* config/rs6000/rs6000-overload.def: Miscellaneous fixes.
* config/rs6000/rs6000.c
(rs6000_new_builtin_md_vectorized_function): Use
rs6000_gen_builtins.
gcc/testsuite/
* gcc.target/powerpc/p8vector-builtin-2.c: Adjust.
* gcc.target/powerpc/p8vector-builtin-3.c: Adjust.
* gcc.target/powerpc/p8vector-builtin-4.c: Adjust.
* gcc.target/powerpc/p8vector-builtin-8.c: Remove deprecated
builtins.
* gcc.target/powerpc/p8vector-int128-2.c: Likewise.
* gcc.target/powerpc/p8vector-vbpermq.c: Likewise.
* gcc.target/powerpc/p9-vparity.c: Likewise.
* gcc.target/powerpc/pr79544.c: Likewise.
* gcc.target/powerpc/pr80315-1.c: Adjust.
* gcc.target/powerpc/pr80315-2.c: Adjust.
* gcc.target/powerpc/pr80315-3.c: Adjust.
* gcc.target/powerpc/pr80315-4.c: Adjust.
* gcc.target/powerpc/pr88100.c: Adjust.
* gcc.target/powerpc/pragma_misc9.c: Adjust.
* gcc.target/powerpc/pragma_power9.c: Undefine
_RS6000_VECDEFINES_H before including altivec.h.
* gcc.target/powerpc/swaps-p8-46.c: Remove deprecated builtins.
* gcc.target/powerpc/test_fpscr_drn_builtin_error.c: Adjust.
* gcc.target/powerpc/test_fpscr_rn_builtin_error.c: Adjust.
Diff:
---
gcc/config/rs6000/altivec.h | 7 ++++
gcc/config/rs6000/rs6000-builtin-new.def | 10 +++---
gcc/config/rs6000/rs6000-c.c | 9 +++--
gcc/config/rs6000/rs6000-overload.def | 39 +++++++++++-----------
gcc/config/rs6000/rs6000.c | 12 +++----
.../gcc.target/powerpc/p8vector-builtin-2.c | 16 ++++-----
.../gcc.target/powerpc/p8vector-builtin-3.c | 8 ++---
.../gcc.target/powerpc/p8vector-builtin-4.c | 18 +++++-----
.../gcc.target/powerpc/p8vector-builtin-8.c | 4 +--
.../gcc.target/powerpc/p8vector-int128-1.c | 16 ++++-----
.../gcc.target/powerpc/p8vector-int128-2.c | 4 +--
.../gcc.target/powerpc/p8vector-vbpermq.c | 4 +--
gcc/testsuite/gcc.target/powerpc/p9-vparity.c | 32 +++++++++---------
gcc/testsuite/gcc.target/powerpc/pr79544.c | 8 +----
gcc/testsuite/gcc.target/powerpc/pr80315-1.c | 2 +-
gcc/testsuite/gcc.target/powerpc/pr80315-2.c | 2 +-
gcc/testsuite/gcc.target/powerpc/pr80315-3.c | 2 +-
gcc/testsuite/gcc.target/powerpc/pr80315-4.c | 2 +-
gcc/testsuite/gcc.target/powerpc/pr88100.c | 12 +++----
gcc/testsuite/gcc.target/powerpc/pragma_misc9.c | 2 +-
gcc/testsuite/gcc.target/powerpc/pragma_power9.c | 1 +
gcc/testsuite/gcc.target/powerpc/swaps-p8-46.c | 5 +--
.../powerpc/test_fpscr_drn_builtin_error.c | 4 +--
.../powerpc/test_fpscr_rn_builtin_error.c | 12 +++----
24 files changed, 117 insertions(+), 114 deletions(-)
diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h
index 8904d2c545d..5a4c366e0f1 100644
--- a/gcc/config/rs6000/altivec.h
+++ b/gcc/config/rs6000/altivec.h
@@ -264,4 +264,11 @@ __altivec_scalar_pred(vec_any_nle,
to #define vec_step to __builtin_vec_step. */
#define vec_step(x) __builtin_vec_step (* (__typeof__ (x) *) 0)
+/* Deprecated interfaces. */
+#ifdef _ARCH_PWR9
+#define __builtin_vec_vadub __builtin_vec_vadu
+#define __builtin_vec_vaduh __builtin_vec_vaduh
+#define __builtin_vec_vaduw __builtin_vec_vaduw
+#endif
+
#endif /* _ALTIVEC_H */
diff --git a/gcc/config/rs6000/rs6000-builtin-new.def b/gcc/config/rs6000/rs6000-builtin-new.def
index 449dcd5e257..061470d8198 100644
--- a/gcc/config/rs6000/rs6000-builtin-new.def
+++ b/gcc/config/rs6000/rs6000-builtin-new.def
@@ -203,7 +203,7 @@
const __ibm128 __builtin_pack_ibm128 (double, double);
PACK_IF packif {}
- void __builtin_set_fpscr_rn (signed long long);
+ void __builtin_set_fpscr_rn (const int[0,7]);
SET_FPSCR_RN rs6000_set_fpscr_rn {}
const double __builtin_unpack_ibm128 (__ibm128, const int<1>);
@@ -1698,7 +1698,7 @@
const vull __builtin_vsx_xvcvdpuxds (vd);
XVCVDPUXDS vsx_fixuns_truncv2dfv2di2 {}
- const vull __builtin_vsx_xvcvdpuxds_scale (vd, const int);
+ const vsll __builtin_vsx_xvcvdpuxds_scale (vd, const int);
XVCVDPUXDS_SCALE vsx_xvcvdpuxds_scale {}
; Redundant with __builtin_vsx_xvcvdpuxds
@@ -2946,7 +2946,7 @@
const _Decimal128 __builtin_pack_dec128 (unsigned long long, unsigned long long);
PACK_TD packtd {}
- void __builtin_set_fpscr_drn (signed long long);
+ void __builtin_set_fpscr_drn (const int[0,7]);
SET_FPSCR_DRN rs6000_set_fpscr_drn {}
const unsigned long long __builtin_unpack_dec128 (_Decimal128, const int<1>);
@@ -3348,13 +3348,13 @@
const vuc __builtin_vsx_xxblend_v16qi (vuc, vuc, vuc);
VXXBLEND_V16QI xxblend_v16qi {}
- const vd __builtin_vsx_xxblend_v2df (vd, vd, vull);
+ const vd __builtin_vsx_xxblend_v2df (vd, vd, vd);
VXXBLEND_V2DF xxblend_v2df {}
const vull __builtin_vsx_xxblend_v2di (vull, vull, vull);
VXXBLEND_V2DI xxblend_v2di {}
- const vf __builtin_vsx_xxblend_v4sf (vf, vf, vui);
+ const vf __builtin_vsx_xxblend_v4sf (vf, vf, vf);
VXXBLEND_V4SF xxblend_v4sf {}
const vui __builtin_vsx_xxblend_v4si (vui, vui, vui);
diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c
index 11099d21006..64924df97f9 100644
--- a/gcc/config/rs6000/rs6000-c.c
+++ b/gcc/config/rs6000/rs6000-c.c
@@ -2245,10 +2245,9 @@ altivec_resolve_new_overloaded_builtin (location_t loc, tree fndecl,
params);
}
/* For {un}signed __int128s use the vaddeuqm/vsubeuqm instruction
- directly. This is done by the normal processing. */
+ directly. */
case E_TImode:
- {
- }
+ break;
/* Types other than {un}signed int and {un}signed __int128
are errors. */
@@ -2345,8 +2344,8 @@ altivec_resolve_new_overloaded_builtin (location_t loc, tree fndecl,
/* For {un}signed __int128s use the vaddecuq/vsubbecuq
instructions. This occurs through normal processing. */
case E_TImode:
- {
- }
+ break;
+
/* Types other than {un}signed int and {un}signed __int128
are errors. */
default:
diff --git a/gcc/config/rs6000/rs6000-overload.def b/gcc/config/rs6000/rs6000-overload.def
index f6e43b88e07..f9bf995de28 100644
--- a/gcc/config/rs6000/rs6000-overload.def
+++ b/gcc/config/rs6000/rs6000-overload.def
@@ -433,7 +433,7 @@
vui __builtin_vec_andc (vui, vui);
VANDC_V4SI_UNS VANDC_VUI
vbll __builtin_vec_andc (vbll, vbll);
- VANDC_V4SI_UNS VANDC_VBLL
+ VANDC_V2DI_UNS VANDC_VBLL
vsll __builtin_vec_andc (vsll, vsll);
VANDC_V2DI
vull __builtin_vec_andc (vull, vull);
@@ -526,7 +526,9 @@
vull __builtin_vec_vbperm_api (vuq, vuc);
VBPERMD VBPERMD_VUQ
vuc __builtin_vec_vbperm_api (vuc, vuc);
- VBPERMQ2
+ VBPERMQ2 VBPERMQ2_U
+ vsc __builtin_vec_vbperm_api (vsc, vsc);
+ VBPERMQ2 VBPERMQ2_S
; #### XVRSPIP{TARGET_VSX};VRFIP
[VEC_CEIL, vec_ceil, __builtin_vec_ceil]
@@ -2915,17 +2917,17 @@
VPOPCNTUD
[VEC_PARITY_LSBB, vec_parity_lsbb, __builtin_vec_vparity_lsbb, _ARCH_PWR9]
- vui __builtin_vec_vparity_lsbb (vsi);
+ vsi __builtin_vec_vparity_lsbb (vsi);
VPRTYBW VPRTYBW_S
- vui __builtin_vec_vparity_lsbb (vui);
+ vsi __builtin_vec_vparity_lsbb (vui);
VPRTYBW VPRTYBW_U
- vull __builtin_vec_vparity_lsbb (vsll);
+ vsll __builtin_vec_vparity_lsbb (vsll);
VPRTYBD VPRTYBD_S
- vull __builtin_vec_vparity_lsbb (vull);
+ vsll __builtin_vec_vparity_lsbb (vull);
VPRTYBD VPRTYBD_U
- vuq __builtin_vec_vparity_lsbb (vsq);
+ vsq __builtin_vec_vparity_lsbb (vsq);
VPRTYBQ VPRTYBQ_S
- vuq __builtin_vec_vparity_lsbb (vuq);
+ vsq __builtin_vec_vparity_lsbb (vuq);
VPRTYBQ VPRTYBQ_U
; There are no actual builtins for vec_promote. There is special handling for
@@ -3276,17 +3278,17 @@
vuc __builtin_vec_sldw (vuc, vuc, const int);
XXSLDWI_16QI XXSLDWI_VUC
vss __builtin_vec_sldw (vss, vss, const int);
- XXSLDWI_16QI XXSLDWI_VSS
+ XXSLDWI_8HI XXSLDWI_VSS
vus __builtin_vec_sldw (vus, vus, const int);
- XXSLDWI_16QI XXSLDWI_VUS
+ XXSLDWI_8HI XXSLDWI_VUS
vsi __builtin_vec_sldw (vsi, vsi, const int);
- XXSLDWI_16QI XXSLDWI_VSI
+ XXSLDWI_4SI XXSLDWI_VSI
vui __builtin_vec_sldw (vui, vui, const int);
- XXSLDWI_16QI XXSLDWI_VUI
+ XXSLDWI_4SI XXSLDWI_VUI
vsll __builtin_vec_sldw (vsll, vsll, const int);
- XXSLDWI_16QI XXSLDWI_VSLL
+ XXSLDWI_2DI XXSLDWI_VSLL
vull __builtin_vec_sldw (vull, vull, const int);
- XXSLDWI_16QI XXSLDWI_VULL
+ XXSLDWI_2DI XXSLDWI_VULL
[VEC_SLL, vec_sll, __builtin_vec_sll]
vsc __builtin_vec_sll (vsc, vuc);
@@ -4119,11 +4121,8 @@
VSUBCUQ VSUBCUQ_VUQ
; TODO: Note that the entry for VEC_SUBE currently gets ignored in
-; altivec_resolve_overloaded_builtin. There are also forms for
-; vsi and vui arguments, but rather than building a define_expand
-; for the instruction sequence generated for those, we do some RTL
-; hackery. Revisit whether we can remove that. For now, keep this
-; much of the entry here to generate the #define, at least.
+; altivec_resolve_overloaded_builtin. Revisit whether we can remove
+; that. We still need to register the legal builtin forms here.
[VEC_SUBE, vec_sube, __builtin_vec_sube]
vsq __builtin_vec_sube (vsq, vsq, vsq);
VSUBEUQM VSUBEUQM_VSQ
@@ -4406,6 +4405,8 @@
LXVW4X_V8HI LXVW4X_VUS
vus __builtin_vec_vsx_ld (signed long long, const unsigned short *);
LXVW4X_V8HI LXVW4X_US
+ vp __builtin_vec_vsx_ld (signed long long, const vp *);
+ LXVW4X_V8HI LXVW4X_P
vsi __builtin_vec_vsx_ld (signed long long, const vsi *);
LXVW4X_V4SI LXVW4X_VSI
vsi __builtin_vec_vsx_ld (signed long long, const signed int *);
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 8b7b7820f42..e48cf0ca702 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -5570,29 +5570,29 @@ rs6000_new_builtin_md_vectorized_function (tree fndecl, tree type_out,
in_mode = TYPE_MODE (TREE_TYPE (type_in));
in_n = TYPE_VECTOR_SUBPARTS (type_in);
- enum rs6000_builtins fn
- = (enum rs6000_builtins) DECL_MD_FUNCTION_CODE (fndecl);
+ enum rs6000_gen_builtins fn
+ = (enum rs6000_gen_builtins) DECL_MD_FUNCTION_CODE (fndecl);
switch (fn)
{
- case RS6000_BUILTIN_RSQRTF:
+ case RS6000_BIF_RSQRTF:
if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
&& out_mode == SFmode && out_n == 4
&& in_mode == SFmode && in_n == 4)
return rs6000_builtin_decls_x[RS6000_BIF_VRSQRTFP];
break;
- case RS6000_BUILTIN_RSQRT:
+ case RS6000_BIF_RSQRT:
if (VECTOR_UNIT_VSX_P (V2DFmode)
&& out_mode == DFmode && out_n == 2
&& in_mode == DFmode && in_n == 2)
return rs6000_builtin_decls_x[RS6000_BIF_RSQRT_2DF];
break;
- case RS6000_BUILTIN_RECIPF:
+ case RS6000_BIF_RECIPF:
if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
&& out_mode == SFmode && out_n == 4
&& in_mode == SFmode && in_n == 4)
return rs6000_builtin_decls_x[RS6000_BIF_VRECIPFP];
break;
- case RS6000_BUILTIN_RECIP:
+ case RS6000_BIF_RECIP:
if (VECTOR_UNIT_VSX_P (V2DFmode)
&& out_mode == DFmode && out_n == 2
&& in_mode == DFmode && in_n == 2)
diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c
index 0259e364aa6..a1f4e4e9a4e 100644
--- a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c
+++ b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c
@@ -214,17 +214,17 @@ v_bshort vbshort_ne (v_bshort a, v_bshort b)
}
-/* { dg-final { scan-assembler-times "vaddudm" 5 } } */
-/* { dg-final { scan-assembler-times "vsubudm" 6 } } */
-/* { dg-final { scan-assembler-times "vmaxsd" 4 } } */
-/* { dg-final { scan-assembler-times "vminsd" 3 } } */
-/* { dg-final { scan-assembler-times "vmaxud" 2 } } */
-/* { dg-final { scan-assembler-times "vminud" 2 } } */
+/* { dg-final { scan-assembler-times "vaddudm" 3 } } */
+/* { dg-final { scan-assembler-times "vsubudm" 4 } } */
+/* { dg-final { scan-assembler-times "vmaxsd" 3 } } */
+/* { dg-final { scan-assembler-times "vminsd" 2 } } */
+/* { dg-final { scan-assembler-times "vmaxud" 1 } } */
+/* { dg-final { scan-assembler-times "vminud" 1 } } */
/* { dg-final { scan-assembler-times "vcmpequd" 6 } } */
/* { dg-final { scan-assembler-times "vcmpgtsd" 1 } } */
/* { dg-final { scan-assembler-times "vcmpgtud" 1 } } */
/* { dg-final { scan-assembler-times "vrld" 3 } } */
-/* { dg-final { scan-assembler-times "vsld" 5 } } */
-/* { dg-final { scan-assembler-times "vsrad" 3 } } */
+/* { dg-final { scan-assembler-times "vsld" 3 } } */
+/* { dg-final { scan-assembler-times "vsrad" 2 } } */
/* { dg-final { scan-assembler-times "vcmpequb" 3 } } */
/* { dg-final { scan-assembler-times "vcmpequw" 6 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-3.c b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-3.c
index ae6a3a8437b..0b038edfafe 100644
--- a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-3.c
@@ -77,8 +77,8 @@ vll_sign vll_unpack_lo_2 (vi_sign a)
return vec_unpackl (a);
}
-/* { dg-final { scan-assembler-times "vpkudum" 4 } } */
-/* { dg-final { scan-assembler-times "vpkuwum" 3 } } */
-/* { dg-final { scan-assembler-times "vpkuhum" 3 } } */
+/* { dg-final { scan-assembler-times "vpkudum" 3 } } */
+/* { dg-final { scan-assembler-times "vpkuwum" 2 } } */
+/* { dg-final { scan-assembler-times "vpkuhum" 2 } } */
/* { dg-final { scan-assembler-times "vupklsw" 3 } } */
-/* { dg-final { scan-assembler-times "vupkhsw" 3 } } */
+/* { dg-final { scan-assembler-times "vupkhsw" 1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-4.c b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-4.c
index 2d2d141948f..e814c648843 100644
--- a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-4.c
+++ b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-4.c
@@ -156,14 +156,14 @@ vc_uns vc_gbb_3 (vc_uns a)
return vec_gb (a);
}
-/* { dg-final { scan-assembler-times "vclzd" 5 } } */
-/* { dg-final { scan-assembler-times "vclzw" 5 } } */
-/* { dg-final { scan-assembler-times "vclzh" 5 } } */
-/* { dg-final { scan-assembler-times "vclzb" 5 } } */
-
-/* { dg-final { scan-assembler-times "vpopcntd" 5 } } */
-/* { dg-final { scan-assembler-times "vpopcntw" 5 } } */
-/* { dg-final { scan-assembler-times "vpopcnth" 5 } } */
-/* { dg-final { scan-assembler-times "vpopcntb" 5 } } */
+/* { dg-final { scan-assembler-times "vclzd" 3 } } */
+/* { dg-final { scan-assembler-times "vclzw" 3 } } */
+/* { dg-final { scan-assembler-times "vclzh" 3 } } */
+/* { dg-final { scan-assembler-times "vclzb" 3 } } */
+
+/* { dg-final { scan-assembler-times "vpopcntd" 3 } } */
+/* { dg-final { scan-assembler-times "vpopcntw" 3 } } */
+/* { dg-final { scan-assembler-times "vpopcnth" 3 } } */
+/* { dg-final { scan-assembler-times "vpopcntb" 3 } } */
/* { dg-final { scan-assembler-times "vgbbd" 3 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-8.c b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-8.c
index 0cfbe68c3a4..b5c81ab1ace 100644
--- a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-8.c
+++ b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-8.c
@@ -112,7 +112,6 @@ void foo (vector signed char *vscr,
*vsir++ = vec_sum4s (vsca, vsib);
*vsir++ = vec_sum4s (vssa, vsib);
*vuir++ = vec_sum4s (vuca, vuib);
-
}
/* { dg-final { scan-assembler-times "vaddcuq" 2 } } */
@@ -125,7 +124,8 @@ void foo (vector signed char *vscr,
/* { dg-final { scan-assembler-times "vsubecuq" 2 } } */
/* { dg-final { scan-assembler-times "vsubcuw" 4 } } */
/* { dg-final { scan-assembler-times "vsubuwm" 4 } } */
-/* { dg-final { scan-assembler-times "vbpermq" 2 } } */
+/* { dg-final { scan-assembler-times "vbpermq" 1 } } */
+/* { dg-final { scan-assembler-times "vbpermd" 1 } } */
/* { dg-final { scan-assembler-times "xxleqv" 4 } } */
/* { dg-final { scan-assembler-times "vgbbd" 1 } } */
/* { dg-final { scan-assembler-times "xxlnand" 4 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-int128-1.c b/gcc/testsuite/gcc.target/powerpc/p8vector-int128-1.c
index 28b148c692c..8a7484b7144 100644
--- a/gcc/testsuite/gcc.target/powerpc/p8vector-int128-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/p8vector-int128-1.c
@@ -13,49 +13,49 @@
TYPE
do_addcuq (TYPE p, TYPE q)
{
- return __builtin_vec_vaddcuq (p, q);
+ return vec_addc (p, q);
}
TYPE
do_adduqm (TYPE p, TYPE q)
{
- return __builtin_vec_add (p, q);
+ return vec_add (p, q);
}
TYPE
do_addeuqm (TYPE p, TYPE q, TYPE r)
{
- return __builtin_vec_vaddeuqm (p, q, r);
+ return vec_adde (p, q, r);
}
TYPE
do_addecuq (TYPE p, TYPE q, TYPE r)
{
- return __builtin_vec_vaddecuq (p, q, r);
+ return vec_addec (p, q, r);
}
TYPE
do_subeuqm (TYPE p, TYPE q, TYPE r)
{
- return __builtin_vec_vsubeuqm (p, q, r);
+ return vec_sube (p, q, r);
}
TYPE
do_subecuq (TYPE p, TYPE q, TYPE r)
{
- return __builtin_vec_vsubecuq (p, q, r);
+ return vec_subec (p, q, r);
}
TYPE
do_subcuq (TYPE p, TYPE q)
{
- return __builtin_vec_vsubcuq (p, q);
+ return vec_subc (p, q);
}
TYPE
do_subuqm (TYPE p, TYPE q)
{
- return __builtin_vec_vsubuqm (p, q);
+ return vec_sub (p, q);
}
TYPE
diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-int128-2.c b/gcc/testsuite/gcc.target/powerpc/p8vector-int128-2.c
index 72358d616b1..cdeebb36342 100644
--- a/gcc/testsuite/gcc.target/powerpc/p8vector-int128-2.c
+++ b/gcc/testsuite/gcc.target/powerpc/p8vector-int128-2.c
@@ -132,7 +132,7 @@ main (void)
v_reg_in1 = (V_TYPE) { s_reg_in1 };
v_reg_in2 = (V_TYPE) { s_reg_in2 };
- v_reg_res = vec_vadduqm (v_reg_in1, v_reg_in2);
+ v_reg_res = vec_add (v_reg_in1, v_reg_in2);
reg_errors += compare (s_reg_res, v_reg_res, "", "reg, res");
s_mem_in1 = s_reg_in1;
@@ -144,7 +144,7 @@ main (void)
mem_errors += compare (s_mem_in2, (V_TYPE) { s_mem_in2 }, "", "mem, in2");
s_mem_res = s_mem_in1 + s_mem_in2;
- v_mem_res = vec_vadduqm (v_mem_in1, v_mem_in2);
+ v_mem_res = vec_add (v_mem_in1, v_mem_in2);
mem_errors += compare (s_mem_res, v_mem_res, "", "mem, res");
nl = "\n";
diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-vbpermq.c b/gcc/testsuite/gcc.target/powerpc/p8vector-vbpermq.c
index c2ab68ba761..e5601b13b3a 100644
--- a/gcc/testsuite/gcc.target/powerpc/p8vector-vbpermq.c
+++ b/gcc/testsuite/gcc.target/powerpc/p8vector-vbpermq.c
@@ -17,11 +17,11 @@
long foos (vector signed char a, vector signed char b)
{
- return vec_extract (vec_vbpermq (a, b), OFFSET);
+ return vec_extract (vec_bperm (a, b), OFFSET);
}
long foou (vector unsigned char a, vector unsigned char b)
{
- return vec_extract (vec_vbpermq (a, b), OFFSET);
+ return vec_extract (vec_bperm (a, b), OFFSET);
}
diff --git a/gcc/testsuite/gcc.target/powerpc/p9-vparity.c b/gcc/testsuite/gcc.target/powerpc/p9-vparity.c
index f4aba1567cd..8897a5b6b7f 100644
--- a/gcc/testsuite/gcc.target/powerpc/p9-vparity.c
+++ b/gcc/testsuite/gcc.target/powerpc/p9-vparity.c
@@ -9,97 +9,97 @@
vector int
parity_v4si_1s (vector int a)
{
- return vec_vprtyb (a);
+ return vec_parity_lsbb (a);
}
vector int
parity_v4si_2s (vector int a)
{
- return vec_vprtybw (a);
+ return vec_parity_lsbb (a);
}
vector unsigned int
parity_v4si_1u (vector unsigned int a)
{
- return vec_vprtyb (a);
+ return vec_parity_lsbb (a);
}
vector unsigned int
parity_v4si_2u (vector unsigned int a)
{
- return vec_vprtybw (a);
+ return vec_parity_lsbb (a);
}
vector long long
parity_v2di_1s (vector long long a)
{
- return vec_vprtyb (a);
+ return vec_parity_lsbb (a);
}
vector long long
parity_v2di_2s (vector long long a)
{
- return vec_vprtybd (a);
+ return vec_parity_lsbb (a);
}
vector unsigned long long
parity_v2di_1u (vector unsigned long long a)
{
- return vec_vprtyb (a);
+ return vec_parity_lsbb (a);
}
vector unsigned long long
parity_v2di_2u (vector unsigned long long a)
{
- return vec_vprtybd (a);
+ return vec_parity_lsbb (a);
}
vector __int128_t
parity_v1ti_1s (vector __int128_t a)
{
- return vec_vprtyb (a);
+ return vec_parity_lsbb (a);
}
vector __int128_t
parity_v1ti_2s (vector __int128_t a)
{
- return vec_vprtybq (a);
+ return vec_parity_lsbb (a);
}
__int128_t
parity_ti_3s (__int128_t a)
{
- return vec_vprtyb (a);
+ return vec_parity_lsbb (a);
}
__int128_t
parity_ti_4s (__int128_t a)
{
- return vec_vprtybq (a);
+ return vec_parity_lsbb (a);
}
vector __uint128_t
parity_v1ti_1u (vector __uint128_t a)
{
- return vec_vprtyb (a);
+ return vec_parity_lsbb (a);
}
vector __uint128_t
parity_v1ti_2u (vector __uint128_t a)
{
- return vec_vprtybq (a);
+ return vec_parity_lsbb (a);
}
__uint128_t
parity_ti_3u (__uint128_t a)
{
- return vec_vprtyb (a);
+ return vec_parity_lsbb (a);
}
__uint128_t
parity_ti_4u (__uint128_t a)
{
- return vec_vprtybq (a);
+ return vec_parity_lsbb (a);
}
/* { dg-final { scan-assembler "vprtybd" } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/pr79544.c b/gcc/testsuite/gcc.target/powerpc/pr79544.c
index 3f782489bbd..ecdbbcc67bd 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr79544.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr79544.c
@@ -10,11 +10,5 @@ test_sra (vector unsigned long long x, vector unsigned long long y)
return vec_sra (x, y);
}
-vector unsigned long long
-test_vsrad (vector unsigned long long x, vector unsigned long long y)
-{
- return vec_vsrad (x, y);
-}
-
-/* { dg-final { scan-assembler-times {\mvsrad\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mvsrad\M} 1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/pr80315-1.c b/gcc/testsuite/gcc.target/powerpc/pr80315-1.c
index e2db0ff4b5f..f37f1f169a2 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr80315-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr80315-1.c
@@ -10,6 +10,6 @@ main()
int mask;
/* Argument 2 must be 0 or 1. Argument 3 must be in range 0..15. */
- res = __builtin_crypto_vshasigmaw (test, 1, 0xff); /* { dg-error {argument 3 must be in the range \[0, 15\]} } */
+ res = __builtin_crypto_vshasigmaw (test, 1, 0xff); /* { dg-error {argument 3 must be a 4-bit unsigned literal} } */
return 0;
}
diff --git a/gcc/testsuite/gcc.target/powerpc/pr80315-2.c b/gcc/testsuite/gcc.target/powerpc/pr80315-2.c
index 144b705c012..0819a0511b7 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr80315-2.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr80315-2.c
@@ -10,6 +10,6 @@ main ()
int mask;
/* Argument 2 must be 0 or 1. Argument 3 must be in range 0..15. */
- res = __builtin_crypto_vshasigmad (test, 1, 0xff); /* { dg-error {argument 3 must be in the range \[0, 15\]} } */
+ res = __builtin_crypto_vshasigmad (test, 1, 0xff); /* { dg-error {argument 3 must be a 4-bit unsigned literal} } */
return 0;
}
diff --git a/gcc/testsuite/gcc.target/powerpc/pr80315-3.c b/gcc/testsuite/gcc.target/powerpc/pr80315-3.c
index 99a3e24eadd..cc2e46cf5cb 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr80315-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr80315-3.c
@@ -12,6 +12,6 @@ main ()
int mask;
/* Argument 2 must be 0 or 1. Argument 3 must be in range 0..15. */
- res = vec_shasigma_be (test, 1, 0xff); /* { dg-error {argument 3 must be in the range \[0, 15\]} } */
+ res = vec_shasigma_be (test, 1, 0xff); /* { dg-error {argument 3 must be a 4-bit unsigned literal} } */
return res;
}
diff --git a/gcc/testsuite/gcc.target/powerpc/pr80315-4.c b/gcc/testsuite/gcc.target/powerpc/pr80315-4.c
index 7f5f6f75029..ac12910741b 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr80315-4.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr80315-4.c
@@ -12,6 +12,6 @@ main ()
int mask;
/* Argument 2 must be 0 or 1. Argument 3 must be in range 0..15. */
- res = vec_shasigma_be (test, 1, 0xff); /* { dg-error {argument 3 must be in the range \[0, 15\]} } */
+ res = vec_shasigma_be (test, 1, 0xff); /* { dg-error {argument 3 must be a 4-bit unsigned literal} } */
return res;
}
diff --git a/gcc/testsuite/gcc.target/powerpc/pr88100.c b/gcc/testsuite/gcc.target/powerpc/pr88100.c
index 4452145ce95..764c897a497 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr88100.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr88100.c
@@ -10,35 +10,35 @@
vector unsigned char
splatu1 (void)
{
- return vec_splat_u8(0x100);/* { dg-error "argument 1 must be a 5-bit signed literal" } */
+ return vec_splat_u8(0x100);/* { dg-error "argument 1 must be a literal between -16 and 15, inclusive" } */
}
vector unsigned short
splatu2 (void)
{
- return vec_splat_u16(0x10000);/* { dg-error "argument 1 must be a 5-bit signed literal" } */
+ return vec_splat_u16(0x10000);/* { dg-error "argument 1 must be a literal between -16 and 15, inclusive" } */
}
vector unsigned int
splatu3 (void)
{
- return vec_splat_u32(0x10000000);/* { dg-error "argument 1 must be a 5-bit signed literal" } */
+ return vec_splat_u32(0x10000000);/* { dg-error "argument 1 must be a literal between -16 and 15, inclusive" } */
}
vector signed char
splats1 (void)
{
- return vec_splat_s8(0x100);/* { dg-error "argument 1 must be a 5-bit signed literal" } */
+ return vec_splat_s8(0x100);/* { dg-error "argument 1 must be a literal between -16 and 15, inclusive" } */
}
vector signed short
splats2 (void)
{
- return vec_splat_s16(0x10000);/* { dg-error "argument 1 must be a 5-bit signed literal" } */
+ return vec_splat_s16(0x10000);/* { dg-error "argument 1 must be a literal between -16 and 15, inclusive" } */
}
vector signed int
splats3 (void)
{
- return vec_splat_s32(0x10000000);/* { dg-error "argument 1 must be a 5-bit signed literal" } */
+ return vec_splat_s32(0x10000000);/* { dg-error "argument 1 must be a literal between -16 and 15, inclusive" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/pragma_misc9.c b/gcc/testsuite/gcc.target/powerpc/pragma_misc9.c
index e03099bd084..61274463653 100644
--- a/gcc/testsuite/gcc.target/powerpc/pragma_misc9.c
+++ b/gcc/testsuite/gcc.target/powerpc/pragma_misc9.c
@@ -20,7 +20,7 @@ vector bool int
test2 (vector signed int a, vector signed int b)
{
return vec_cmpnez (a, b);
- /* { dg-error "'__builtin_altivec_vcmpnezw' requires the '-mcpu=power9' option" "" { target *-*-* } .-1 } */
+ /* { dg-error "'__builtin_altivec_vcmpnezw' requires the '-mpower9-vector' option" "" { target *-*-* } .-1 } */
}
#pragma GCC target ("cpu=power7")
diff --git a/gcc/testsuite/gcc.target/powerpc/pragma_power9.c b/gcc/testsuite/gcc.target/powerpc/pragma_power9.c
index e33aad1aaf7..5327c8c8cc8 100644
--- a/gcc/testsuite/gcc.target/powerpc/pragma_power9.c
+++ b/gcc/testsuite/gcc.target/powerpc/pragma_power9.c
@@ -50,6 +50,7 @@ test3b (vec_t a, vec_t b)
#pragma GCC target ("cpu=power9,power9-vector")
#undef _ALTIVEC_H
+#undef _RS6000_VECDEFINES_H
#include <altivec.h>
#ifdef _ARCH_PWR9
vector bool int
diff --git a/gcc/testsuite/gcc.target/powerpc/swaps-p8-46.c b/gcc/testsuite/gcc.target/powerpc/swaps-p8-46.c
index 4738d5e0139..3911ac9e713 100644
--- a/gcc/testsuite/gcc.target/powerpc/swaps-p8-46.c
+++ b/gcc/testsuite/gcc.target/powerpc/swaps-p8-46.c
@@ -2,6 +2,7 @@
/* { dg-require-effective-target powerpc_p8vector_ok } */
/* { dg-options "-mdejagnu-cpu=power8 -O2 " } */
+#include <altivec.h>
typedef __attribute__ ((__aligned__ (8))) unsigned long long __m64;
typedef float __m128 __attribute__ ((__vector_size__ (16), __may_alias__));
@@ -17,8 +18,8 @@ _mm_movemask_ps (__m128 *__A)
};
result = (__vector __m64)
- __builtin_vec_vbpermq ((__vector unsigned char) (*__A),
- (__vector unsigned char) perm_mask);
+ vec_bperm ((__vector unsigned char) (*__A),
+ (__vector unsigned char) perm_mask);
return result[1];
}
diff --git a/gcc/testsuite/gcc.target/powerpc/test_fpscr_drn_builtin_error.c b/gcc/testsuite/gcc.target/powerpc/test_fpscr_drn_builtin_error.c
index 028ab0b6d66..4f9d9e08e8a 100644
--- a/gcc/testsuite/gcc.target/powerpc/test_fpscr_drn_builtin_error.c
+++ b/gcc/testsuite/gcc.target/powerpc/test_fpscr_drn_builtin_error.c
@@ -9,8 +9,8 @@ int main ()
__builtin_set_fpscr_drn() also support a variable as an argument but
can't test variable value at compile time. */
- __builtin_set_fpscr_drn(-1); /* { dg-error "Argument must be a value between 0 and 7" } */
- __builtin_set_fpscr_drn(8); /* { dg-error "Argument must be a value between 0 and 7" } */
+ __builtin_set_fpscr_drn(-1); /* { dg-error "argument 1 must be a variable or a literal between 0 and 7, inclusive" } */
+ __builtin_set_fpscr_drn(8); /* { dg-error "argument 1 must be a variable or a literal between 0 and 7, inclusive" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/test_fpscr_rn_builtin_error.c b/gcc/testsuite/gcc.target/powerpc/test_fpscr_rn_builtin_error.c
index aea65091b0c..10391b71008 100644
--- a/gcc/testsuite/gcc.target/powerpc/test_fpscr_rn_builtin_error.c
+++ b/gcc/testsuite/gcc.target/powerpc/test_fpscr_rn_builtin_error.c
@@ -8,13 +8,13 @@ int main ()
int arguments. The builtins __builtin_set_fpscr_rn() also supports a
variable as an argument but can't test variable value at compile time. */
- __builtin_mtfsb0(-1); /* { dg-error "Argument must be a constant between 0 and 31" } */
- __builtin_mtfsb0(32); /* { dg-error "Argument must be a constant between 0 and 31" } */
+ __builtin_mtfsb0(-1); /* { dg-error "argument 1 must be a 5-bit unsigned literal" } */
+ __builtin_mtfsb0(32); /* { dg-error "argument 1 must be a 5-bit unsigned literal" } */
- __builtin_mtfsb1(-1); /* { dg-error "Argument must be a constant between 0 and 31" } */
- __builtin_mtfsb1(32); /* { dg-error "Argument must be a constant between 0 and 31" } */
+ __builtin_mtfsb1(-1); /* { dg-error "argument 1 must be a 5-bit unsigned literal" } */
+ __builtin_mtfsb1(32); /* { dg-error "argument 1 must be a 5-bit unsigned literal" } */
- __builtin_set_fpscr_rn(-1); /* { dg-error "Argument must be a value between 0 and 3" } */
- __builtin_set_fpscr_rn(4); /* { dg-error "Argument must be a value between 0 and 3" } */
+ __builtin_set_fpscr_rn(-1); /* { dg-error "argument 1 must be a variable or a literal between 0 and 3, inclusive" } */
+ __builtin_set_fpscr_rn(4); /* { dg-error "argument 1 must be a variable or a literal between 0 and 3, inclusive" } */
}
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