From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2153) id 1F2473857816; Fri, 29 Jan 2021 10:55:00 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 1F2473857816 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Jakub Jelinek To: gcc-cvs@gcc.gnu.org Subject: [gcc r11-6970] arm: Fix up -mcpu=iwmmxt ICEs [PR98849] X-Act-Checkin: gcc X-Git-Author: Jakub Jelinek X-Git-Refname: refs/heads/master X-Git-Oldrev: 9c445c07cda60488d7a5458b070356e05e7b2e09 X-Git-Newrev: e7429bc9d60c0cb9809a8040bb63dbb9390f40f1 Message-Id: <20210129105500.1F2473857816@sourceware.org> Date: Fri, 29 Jan 2021 10:55:00 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 29 Jan 2021 10:55:00 -0000 https://gcc.gnu.org/g:e7429bc9d60c0cb9809a8040bb63dbb9390f40f1 commit r11-6970-ge7429bc9d60c0cb9809a8040bb63dbb9390f40f1 Author: Jakub Jelinek Date: Fri Jan 29 11:54:22 2021 +0100 arm: Fix up -mcpu=iwmmxt ICEs [PR98849] The https://gcc.gnu.org/r11-6707-g7432f255b70811dafaf325d94036ac580891de69 https://gcc.gnu.org/r11-6708-gbfab355012ca0f5219da8beb04f2fdaf757d34b7 changes moved the vashl/vashr/vlshr expanders from neon.md to vec-common.md and changed their condition from TARGET_NEON to ARM_HAVE__ARITH, so that they apply also for TARGET_HAVE_MVE. But, the ARM_HAVE__ARITH macros are sometimes true also for TARGET_REALLY_IWMMXT, which at least from quick skimming of former iwmmxt*.md doesn't have such instructions, so it seems incorrect to enable them for iwmmxt. Furthermore, even if it had them, iwmmxt doesn't support any way to broadcast values in those modes (vec_duplicate and vec_init optabs) and the middle end relies on if the vector x vector shift/rotate patterns are supported it can emit vector x scalar shift/rotate by broadcasting the shift amount to a vector. As the TARGET_NEON vs. TARGET_REALLY_IWMMXT vs. TARGET_HAVE_MVE never seem to be enabled together, I think we can just write it the following way. Note, seems iwmmxt actually does support vector x scalar shifts, but doesn't really enable the optabs that would tell the middle-end code that it does (and neon and mve don't seem to support those). I'll defer that to anybody that cares about iwmmxt (if any). 2021-01-29 Jakub Jelinek PR target/98849 * config/arm/vec-common.md (mve_vshlq_, vashl3, vashr3, vlshr3): Add && !TARGET_REALLY_IWMMXT to conditions. * gcc.c-torture/compile/pr98849.c: New test. Diff: --- gcc/config/arm/vec-common.md | 8 ++-- gcc/testsuite/gcc.c-torture/compile/pr98849.c | 60 +++++++++++++++++++++++++++ 2 files changed, 64 insertions(+), 4 deletions(-) diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md index 692b28ea8cc..345ada05523 100644 --- a/gcc/config/arm/vec-common.md +++ b/gcc/config/arm/vec-common.md @@ -301,7 +301,7 @@ (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w,w") (match_operand:VDQIW 2 "imm_lshift_or_reg_neon" "w,Dm")] VSHLQ))] - "ARM_HAVE__ARITH" + "ARM_HAVE__ARITH && !TARGET_REALLY_IWMMXT" "@ vshl.%#\t%0, %1, %2 * return neon_output_shift_immediate (\"vshl\", 'i', &operands[2], mode, VALID_NEON_QREG_MODE (mode), true);" @@ -312,7 +312,7 @@ [(set (match_operand:VDQIW 0 "s_register_operand" "") (ashift:VDQIW (match_operand:VDQIW 1 "s_register_operand" "") (match_operand:VDQIW 2 "imm_lshift_or_reg_neon" "")))] - "ARM_HAVE__ARITH" + "ARM_HAVE__ARITH && !TARGET_REALLY_IWMMXT" { emit_insn (gen_mve_vshlq_u (operands[0], operands[1], operands[2])); DONE; @@ -325,7 +325,7 @@ [(set (match_operand:VDQIW 0 "s_register_operand") (ashiftrt:VDQIW (match_operand:VDQIW 1 "s_register_operand") (match_operand:VDQIW 2 "imm_rshift_or_reg_neon")))] - "ARM_HAVE__ARITH" + "ARM_HAVE__ARITH && !TARGET_REALLY_IWMMXT" { if (s_register_operand (operands[2], mode)) { @@ -343,7 +343,7 @@ [(set (match_operand:VDQIW 0 "s_register_operand") (lshiftrt:VDQIW (match_operand:VDQIW 1 "s_register_operand") (match_operand:VDQIW 2 "imm_rshift_or_reg_neon")))] - "ARM_HAVE__ARITH" + "ARM_HAVE__ARITH && !TARGET_REALLY_IWMMXT" { if (s_register_operand (operands[2], mode)) { diff --git a/gcc/testsuite/gcc.c-torture/compile/pr98849.c b/gcc/testsuite/gcc.c-torture/compile/pr98849.c new file mode 100644 index 00000000000..988b625cc79 --- /dev/null +++ b/gcc/testsuite/gcc.c-torture/compile/pr98849.c @@ -0,0 +1,60 @@ +/* PR target/98849 */ + +unsigned int a[1024], b[1024]; +int c[1024], d[1024]; + +void +f1 (void) +{ + for (int i = 0; i < 1024; i++) + a[i] = b[i] << 3; +} + +void +f2 (int x) +{ + for (int i = 0; i < 1024; i++) + a[i] = b[i] << x; +} + +void +f3 (void) +{ + for (int i = 0; i < 1024; i++) + c[i] = d[i] << 3; +} + +void +f4 (int x) +{ + for (int i = 0; i < 1024; i++) + c[i] = d[i] << x; +} + +void +f5 (void) +{ + for (int i = 0; i < 1024; i++) + a[i] = b[i] >> 3; +} + +void +f6 (int x) +{ + for (int i = 0; i < 1024; i++) + a[i] = b[i] >> x; +} + +void +f7 (void) +{ + for (int i = 0; i < 1024; i++) + c[i] = d[i] >> 3; +} + +void +f8 (int x) +{ + for (int i = 0; i < 1024; i++) + c[i] = d[i] >> x; +}