From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1816) id 9769A39DC4C4; Fri, 29 Jan 2021 13:50:04 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 9769A39DC4C4 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Kyrylo Tkachov To: gcc-cvs@gcc.gnu.org Subject: [gcc r11-6979] aarch64: Reimplement vabdl_high* intrinsics using builtins X-Act-Checkin: gcc X-Git-Author: Kyrylo Tkachov X-Git-Refname: refs/heads/master X-Git-Oldrev: 9f499a86b29507e9afbb28dde537ee2609859510 X-Git-Newrev: 9b588cfb4288ef41eb59edc6ab8cb83056b3b6a4 Message-Id: <20210129135004.9769A39DC4C4@sourceware.org> Date: Fri, 29 Jan 2021 13:50:04 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 29 Jan 2021 13:50:04 -0000 https://gcc.gnu.org/g:9b588cfb4288ef41eb59edc6ab8cb83056b3b6a4 commit r11-6979-g9b588cfb4288ef41eb59edc6ab8cb83056b3b6a4 Author: Kyrylo Tkachov Date: Fri Jan 29 13:10:46 2021 +0000 aarch64: Reimplement vabdl_high* intrinsics using builtins This patch reimplements the vabdl_high intrinsics using builtins. It slightly cleans up the RTL pattern (the mode iterators) but nothing interesting apart from that. gcc/ChangeLog: * config/aarch64/aarch64-simd-builtins.def (sabdl2, uabdl2): Define builtins. * config/aarch64/aarch64-simd.md (aarch64_abdl2_3): Rename to... (aarch64_abdl2): ... This. (sadv16qi): Adjust use of above. * config/aarch64/arm_neon.h (vabdl_high_s8): Reimplement using builtin. (vabdl_high_s16): Likewise. (vabdl_high_s32): Likewise. (vabdl_high_u8): Likewise. (vabdl_high_u16): Likewise. (vabdl_high_u32): Likewise. Diff: --- gcc/config/aarch64/aarch64-simd-builtins.def | 4 +++ gcc/config/aarch64/aarch64-simd.md | 10 +++---- gcc/config/aarch64/arm_neon.h | 42 ++++------------------------ 3 files changed, 15 insertions(+), 41 deletions(-) diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def index f3aace38577..9db259a2967 100644 --- a/gcc/config/aarch64/aarch64-simd-builtins.def +++ b/gcc/config/aarch64/aarch64-simd-builtins.def @@ -172,6 +172,10 @@ BUILTIN_VQW (TERNOP, sabal2, 0, NONE) BUILTIN_VQW (TERNOPU, uabal2, 0, NONE) + /* Implemented by aarch64_abdl2. */ + BUILTIN_VQW (BINOP, sabdl2, 0, NONE) + BUILTIN_VQW (BINOPU, uabdl2, 0, NONE) + /* Implemented by aarch64_hn. */ BUILTIN_VQN (BINOP, addhn, 0, NONE) BUILTIN_VQN (BINOP, subhn, 0, NONE) diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 98d510b6eb6..2f41d7aaa9b 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -818,10 +818,10 @@ [(set_attr "type" "neon_abd")] ) -(define_insn "aarch64_abdl2_3" +(define_insn "aarch64_abdl2" [(set (match_operand: 0 "register_operand" "=w") - (unspec: [(match_operand:VDQV_S 1 "register_operand" "w") - (match_operand:VDQV_S 2 "register_operand" "w")] + (unspec: [(match_operand:VQW 1 "register_operand" "w") + (match_operand:VQW 2 "register_operand" "w")] ABDL2))] "TARGET_SIMD" "abdl2\t%0., %1., %2." @@ -897,8 +897,8 @@ DONE; } rtx reduc = gen_reg_rtx (V8HImode); - emit_insn (gen_aarch64_abdl2v16qi_3 (reduc, operands[1], - operands[2])); + emit_insn (gen_aarch64_abdl2v16qi (reduc, operands[1], + operands[2])); emit_insn (gen_aarch64_abalv8qi (reduc, reduc, gen_lowpart (V8QImode, operands[1]), gen_lowpart (V8QImode, diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h index 66feec3cce0..2297e5b8d41 100644 --- a/gcc/config/aarch64/arm_neon.h +++ b/gcc/config/aarch64/arm_neon.h @@ -6831,72 +6831,42 @@ __extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vabdl_high_s8 (int8x16_t __a, int8x16_t __b) { - int16x8_t __result; - __asm__ ("sabdl2 %0.8h,%1.16b,%2.16b" - : "=w"(__result) - : "w"(__a), "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_sabdl2v16qi (__a, __b); } __extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vabdl_high_s16 (int16x8_t __a, int16x8_t __b) { - int32x4_t __result; - __asm__ ("sabdl2 %0.4s,%1.8h,%2.8h" - : "=w"(__result) - : "w"(__a), "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_sabdl2v8hi (__a, __b); } __extension__ extern __inline int64x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vabdl_high_s32 (int32x4_t __a, int32x4_t __b) { - int64x2_t __result; - __asm__ ("sabdl2 %0.2d,%1.4s,%2.4s" - : "=w"(__result) - : "w"(__a), "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_sabdl2v4si (__a, __b); } __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vabdl_high_u8 (uint8x16_t __a, uint8x16_t __b) { - uint16x8_t __result; - __asm__ ("uabdl2 %0.8h,%1.16b,%2.16b" - : "=w"(__result) - : "w"(__a), "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_uabdl2v16qi_uuu (__a, __b); } __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vabdl_high_u16 (uint16x8_t __a, uint16x8_t __b) { - uint32x4_t __result; - __asm__ ("uabdl2 %0.4s,%1.8h,%2.8h" - : "=w"(__result) - : "w"(__a), "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_uabdl2v8hi_uuu (__a, __b); } __extension__ extern __inline uint64x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vabdl_high_u32 (uint32x4_t __a, uint32x4_t __b) { - uint64x2_t __result; - __asm__ ("uabdl2 %0.2d,%1.4s,%2.4s" - : "=w"(__result) - : "w"(__a), "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_uabdl2v4si_uuu (__a, __b); } __extension__ extern __inline int16x8_t