[gcc(refs/users/wschmidt/heads/builtins4)] rs6000: More bug fixes

[William Schmidt <wschmidt@gcc.gnu.org>]

https://gcc.gnu.org/g:f201279ba188c30d47c7c7e4b12e0fb831f89f34

commit f201279ba188c30d47c7c7e4b12e0fb831f89f34
Author: Bill Schmidt <wschmidt@linux.ibm.com>
Date:   Mon Feb 22 14:20:48 2021 -0600

    rs6000: More bug fixes
    
    2021-02-21  Bill Schmidt  <wschmidt@linux.ibm.com>
    
    gcc/
            * config/rs6000/rs6000-builtin-new.def (SE_LXVRBX): Fill in icode.
            (SE_LXVRHX): Likewise.
            (SE_LXVRWX): Likewise.
            (SE_LXVRDX): Likewise.
            (TR_STXVRBX): Likewise.
            (TR_STXVRHX): Likewise.
            (TR_STXVRWX): Likewise.
            (TR_STXVRDX): Likewise.
            * config/rs6000/rs6000-call.c (lxvr_expand_builtin): New function.
            (stv_expand_builtin): Add support for truncating stores.
            (rs6000_expand_new_builtin): Handle bif_is_lxvr.

Diff:
---
 gcc/config/rs6000/rs6000-builtin-new.def | 16 +++---
 gcc/config/rs6000/rs6000-call.c          | 83 +++++++++++++++++++++++++++++++-
 2 files changed, 90 insertions(+), 9 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-builtin-new.def b/gcc/config/rs6000/rs6000-builtin-new.def
index 95dfdf306ab..d325e876308 100644
--- a/gcc/config/rs6000/rs6000-builtin-new.def
+++ b/gcc/config/rs6000/rs6000-builtin-new.def
@@ -3083,28 +3083,28 @@
     MTVSRWM vec_mtvsr_v4si {}
 
   pure vsq __builtin_altivec_se_lxvrbx (signed long long, const signed char *);
-    SE_LXVRBX nothing {lxvr}
+    SE_LXVRBX vsx_lxvrbx {lxvr}
 
   pure vsq __builtin_altivec_se_lxvrhx (signed long long, const signed short *);
-    SE_LXVRHX nothing {lxvr}
+    SE_LXVRHX vsx_lxvrhx {lxvr}
 
   pure vsq __builtin_altivec_se_lxvrwx (signed long long, const signed int *);
-    SE_LXVRWX nothing {lxvr}
+    SE_LXVRWX vsx_lxvrwx {lxvr}
 
   pure vsq __builtin_altivec_se_lxvrdx (signed long long, const signed long long *);
-    SE_LXVRDX nothing {lxvr}
+    SE_LXVRDX vsx_lxvrdx {lxvr}
 
   void __builtin_altivec_tr_stxvrbx (vsq, signed long long, signed char *);
-    TR_STXVRBX nothing {stvec}
+    TR_STXVRBX vsx_stxvrbx {stvec}
 
   void __builtin_altivec_tr_stxvrhx (vsq, signed long long, signed int *);
-    TR_STXVRHX nothing {stvec}
+    TR_STXVRHX vsx_stxvrhx {stvec}
 
   void __builtin_altivec_tr_stxvrwx (vsq, signed long long, signed short *);
-    TR_STXVRWX nothing {stvec}
+    TR_STXVRWX vsx_stxvrwx {stvec}
 
   void __builtin_altivec_tr_stxvrdx (vsq, signed long long, signed long long *);
-    TR_STXVRDX nothing {stvec}
+    TR_STXVRDX vsx_stxvrdx {stvec}
 
   const vull __builtin_altivec_vcfuged (vull, vull);
     VCFUGED vcfuged {}
diff --git a/gcc/config/rs6000/rs6000-call.c b/gcc/config/rs6000/rs6000-call.c
index 8907bc96db5..b3265dd2d81 100644
--- a/gcc/config/rs6000/rs6000-call.c
+++ b/gcc/config/rs6000/rs6000-call.c
@@ -13557,11 +13557,70 @@ ldv_expand_builtin (rtx target, insn_code icode, rtx *op, machine_mode tmode)
   return target;
 }
 
+static rtx
+lxvr_expand_builtin (rtx target, insn_code icode, rtx *op, machine_mode tmode,
+		     machine_mode smode)
+{
+  rtx pat, addr;
+  op[1] = copy_to_mode_reg (Pmode, op[1]);
+
+  if (op[0] == const0_rtx)
+    addr = gen_rtx_MEM (tmode, op[1]);
+  else
+    {
+      op[0] = copy_to_mode_reg (tmode, op[0]);
+      addr = gen_rtx_MEM (smode,
+			  gen_rtx_PLUS (Pmode, op[1], op[0]));
+    }
+
+  if (icode == CODE_FOR_vsx_lxvrbx
+      || icode == CODE_FOR_vsx_lxvrhx
+      || icode == CODE_FOR_vsx_lxvrwx
+      || icode == CODE_FOR_vsx_lxvrdx)
+    {
+      rtx discratch = gen_reg_rtx (DImode);
+      rtx tiscratch = gen_reg_rtx (TImode);
+
+      /* Emit the lxvr*x insn.  */
+      pat = GEN_FCN (icode) (tiscratch, addr);
+      if (!pat)
+	return 0;
+      emit_insn (pat);
+
+      /* Emit a sign extension from QI,HI,WI to double (DI).  */
+      rtx scratch = gen_lowpart (smode, tiscratch);
+      if (icode == CODE_FOR_vsx_lxvrbx)
+	emit_insn (gen_extendqidi2 (discratch, scratch));
+      else if (icode == CODE_FOR_vsx_lxvrhx)
+	emit_insn (gen_extendhidi2 (discratch, scratch));
+      else if (icode == CODE_FOR_vsx_lxvrwx)
+	emit_insn (gen_extendsidi2 (discratch, scratch));
+      /*  Assign discratch directly if scratch is already DI.  */
+      if (icode == CODE_FOR_vsx_lxvrdx)
+	discratch = scratch;
+
+      /* Emit the sign extension from DI (double) to TI (quad).  */
+      emit_insn (gen_extendditi2 (target, discratch));
+
+      return target;
+    }
+  else
+    {
+      /* Zero extend.  */
+      pat = GEN_FCN (icode) (target, addr);
+      if (!pat)
+	return 0;
+      emit_insn (pat);
+      return target;
+    }
+  return 0;
+}
+
 static rtx
 stv_expand_builtin (insn_code icode, rtx *op,
 		    machine_mode tmode, machine_mode smode)
 {
-  rtx pat, addr, rawaddr;
+  rtx pat, addr, rawaddr, truncrtx;
   op[2] = copy_to_mode_reg (Pmode, op[2]);
 
   /* For STVX, express the RTL accurately by ANDing the address with -16.
@@ -13587,6 +13646,25 @@ stv_expand_builtin (insn_code icode, rtx *op,
       op[0] = copy_to_mode_reg (tmode, op[0]);
       emit_insn (gen_rtx_SET (addr, op[0]));
     }
+  else if (icode == CODE_FOR_vsx_stxvrbx
+	   || icode == CODE_FOR_vsx_stxvrhx
+	   || icode == CODE_FOR_vsx_stxvrwx
+	   || icode == CODE_FOR_vsx_stxvrdx)
+    {
+      truncrtx = gen_rtx_TRUNCATE (tmode, op[0]);
+      op[0] = copy_to_mode_reg (E_TImode, truncrtx);
+
+      if (op[1] == const0_rtx)
+	addr = gen_rtx_MEM (Pmode, op[2]);
+      else
+	{
+	  op[1] = copy_to_mode_reg (Pmode, op[1]);
+	  addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op[2], op[1]));
+	}
+      pat = GEN_FCN (icode) (addr, op[0]);
+      if (pat)
+	emit_insn (pat);
+    }
   else
     {
       if (! (*insn_data[icode].operand[1].predicate) (op[0], smode))
@@ -15412,6 +15490,9 @@ rs6000_expand_new_builtin (tree exp, rtx target,
       return ldv_expand_builtin (target, icode, op, mode[0]);
     }
 
+  if (bif_is_lxvr (*bifaddr))
+    return lxvr_expand_builtin (target, icode, op, mode[0], mode[1]);
+
   if (bif_is_mma (*bifaddr))
     return new_mma_expand_builtin (exp, target, icode);