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* [gcc r11-7650] Fix memory constraint bug in SPARC back-end
@ 2021-03-12 17:52 Eric Botcazou
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From: Eric Botcazou @ 2021-03-12 17:52 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:d8b84e2771fc2495493d0c66c3cba714484757d7
commit r11-7650-gd8b84e2771fc2495493d0c66c3cba714484757d7
Author: Eric Botcazou <ebotcazou@adacore.com>
Date: Fri Mar 12 17:07:20 2021 +0100
Fix memory constraint bug in SPARC back-end
It's a bug exposed by the recent LRA changes, whereby the T constraint
fails to behave properly when LRA is enabled (unlike when reload is
enabled). The patch also gets rid of the awkward W constraint, which
is strictly equivalent to m in 64-bit mode and, as a result, renames
the w constraint into W.
gcc/
PR target/99422
* config/sparc/constraints.md (w): Rename to...
(W): ... this and ditch previous implementation.
* config/sparc/sparc.md (*movdi_insn_sp64): Replace W with m.
(*movdf_insn_sp64): Likewise.
(*mov<VM64:mode>_insn_sp64): Likewise.
* config/sparc/sync.md (*atomic_compare_and_swap<mode>_1): Replace
w with W.
(atomic_compare_and_swap_leon3_1): Likewise.
(*atomic_compare_and_swapdi_v8plus): Likewise.
* config/sparc/sparc.c (memory_ok_for_ldd): Remove useless test on
architecture and add missing address validity check during LRA.
Diff:
---
gcc/config/sparc/constraints.md | 9 +--------
gcc/config/sparc/sparc.c | 9 ++++++---
gcc/config/sparc/sparc.md | 12 ++++++------
gcc/config/sparc/sync.md | 6 +++---
4 files changed, 16 insertions(+), 20 deletions(-)
diff --git a/gcc/config/sparc/constraints.md b/gcc/config/sparc/constraints.md
index 82bbba90457..7ddf014596d 100644
--- a/gcc/config/sparc/constraints.md
+++ b/gcc/config/sparc/constraints.md
@@ -19,7 +19,7 @@
;;; Unused letters:
;;; B
-;;; a jkl uv xyz
+;;; a jkl uvwxyz
;; Register constraints
@@ -190,14 +190,7 @@
(match_test "TARGET_ARCH32")
(match_test "register_ok_for_ldd (op)")))
-;; Equivalent to 'T' but in 64-bit mode without alignment requirement
(define_memory_constraint "W"
- "Memory reference for 'e' constraint floating-point register"
- (and (match_code "mem")
- (match_test "TARGET_ARCH64")
- (match_test "memory_ok_for_ldd (op)")))
-
-(define_memory_constraint "w"
"A memory with only a base register"
(match_operand 0 "mem_noofs_operand"))
diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
index f1504172022..42ba415255c 100644
--- a/gcc/config/sparc/sparc.c
+++ b/gcc/config/sparc/sparc.c
@@ -9223,14 +9223,17 @@ register_ok_for_ldd (rtx reg)
int
memory_ok_for_ldd (rtx op)
{
- /* In 64-bit mode, we assume that the address is word-aligned. */
- if (TARGET_ARCH32 && !mem_min_alignment (op, 8))
+ if (!mem_min_alignment (op, 8))
return 0;
- if (! can_create_pseudo_p ()
+ /* We need to perform the job of a memory constraint. */
+ if ((reload_in_progress || reload_completed)
&& !strict_memory_address_p (Pmode, XEXP (op, 0)))
return 0;
+ if (lra_in_progress && !memory_address_p (Pmode, XEXP (op, 0)))
+ return 0;
+
return 1;
}
\f
diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index 02b7c8d2fdd..c5d369626cc 100644
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -1869,8 +1869,8 @@ visl")
(set_attr "lra" "*,*,disabled,disabled,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*")])
(define_insn "*movdi_insn_sp64"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r, m, r,*e,?*e,?*e, W,b,b")
- (match_operand:DI 1 "input_operand" "rI,N,m,rJ,*e, r, *e, W,?*e,J,P"))]
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r, m, r,*e,?*e,?*e, m,b,b")
+ (match_operand:DI 1 "input_operand" "rI,N,m,rJ,*e, r, *e, m,?*e,J,P"))]
"TARGET_ARCH64
&& (register_operand (operands[0], DImode)
|| register_or_zero_or_all_ones_operand (operands[1], DImode))"
@@ -2498,8 +2498,8 @@ visl")
(set_attr "lra" "*,*,*,*,*,*,*,*,*,*,disabled,disabled,*,*,*,*,*")])
(define_insn "*movdf_insn_sp64"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=b,b,e,*r, e, e,W, *r,*r, m,*r")
- (match_operand:DF 1 "input_operand" "G,C,e, e,*r,W#F,e,*rG, m,*rG, F"))]
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=b,b,e,*r, e, e,m, *r,*r, m,*r")
+ (match_operand:DF 1 "input_operand" "G,C,e, e,*r,m#F,e,*rG, m,*rG, F"))]
"TARGET_ARCH64
&& (register_operand (operands[0], DFmode)
|| register_or_zero_or_all_ones_operand (operands[1], DFmode))"
@@ -8467,8 +8467,8 @@ visl")
(set_attr "cpu_feature" "vis,vis,vis,*,*,*,*,*,*,vis3,vis3")])
(define_insn "*mov<VM64:mode>_insn_sp64"
- [(set (match_operand:VM64 0 "nonimmediate_operand" "=e,e,e,e,W,m,*r, m,*r, e,*r")
- (match_operand:VM64 1 "input_operand" "Y,Z,e,W,e,Y, m,*r, e,*r,*r"))]
+ [(set (match_operand:VM64 0 "nonimmediate_operand" "=e,e,e,e,m,m,*r, m,*r, e,*r")
+ (match_operand:VM64 1 "input_operand" "Y,Z,e,m,e,Y, m,*r, e,*r,*r"))]
"TARGET_VIS
&& TARGET_ARCH64
&& (register_operand (operands[0], <VM64:MODE>mode)
diff --git a/gcc/config/sparc/sync.md b/gcc/config/sparc/sync.md
index c578e95811e..c0a20ef8937 100644
--- a/gcc/config/sparc/sync.md
+++ b/gcc/config/sparc/sync.md
@@ -202,7 +202,7 @@
(define_insn "*atomic_compare_and_swap<mode>_1"
[(set (match_operand:I48MODE 0 "register_operand" "=r")
- (match_operand:I48MODE 1 "mem_noofs_operand" "+w"))
+ (match_operand:I48MODE 1 "mem_noofs_operand" "+W"))
(set (match_dup 1)
(unspec_volatile:I48MODE
[(match_operand:I48MODE 2 "register_operand" "r")
@@ -214,7 +214,7 @@
(define_insn "atomic_compare_and_swap_leon3_1"
[(set (match_operand:SI 0 "register_operand" "=r")
- (match_operand:SI 1 "mem_noofs_operand" "+w"))
+ (match_operand:SI 1 "mem_noofs_operand" "+W"))
(set (match_dup 1)
(unspec_volatile:SI
[(match_operand:SI 2 "register_operand" "r")
@@ -235,7 +235,7 @@
(define_insn "*atomic_compare_and_swapdi_v8plus"
[(set (match_operand:DI 0 "register_operand" "=h")
- (match_operand:DI 1 "mem_noofs_operand" "+w"))
+ (match_operand:DI 1 "mem_noofs_operand" "+W"))
(set (match_dup 1)
(unspec_volatile:DI
[(match_operand:DI 2 "register_operand" "h")
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2021-03-12 17:52 [gcc r11-7650] Fix memory constraint bug in SPARC back-end Eric Botcazou
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