From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 9A5B4385801A; Fri, 19 Mar 2021 16:20:48 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 9A5B4385801A Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work042)] Revert patch. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work042 X-Git-Oldrev: 80a1cba0b88a49772c6a22f8d2e0be6b9b0ba822 X-Git-Newrev: b8c0ad2186aba8e2da86766a63c62f7b86802d8e Message-Id: <20210319162048.9A5B4385801A@sourceware.org> Date: Fri, 19 Mar 2021 16:20:48 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 19 Mar 2021 16:20:48 -0000 https://gcc.gnu.org/g:b8c0ad2186aba8e2da86766a63c62f7b86802d8e commit b8c0ad2186aba8e2da86766a63c62f7b86802d8e Author: Michael Meissner Date: Fri Mar 19 12:20:21 2021 -0400 Revert patch. gcc/ 2021-03-19 Michael Meissner Revert patch. * config/rs6000/altivec.md (xxspltiw_v4si): Rewrite to use vec_duplicate. * config/rs6000/predicates.md (easy_vector_constant): Add support for constants we can create with XXSPLTIW. * config/rs6000/rs6000-protos.h (xxspltiw_constant_p): New declaration. * config/rs6000/rs6000.c (xxspltiw_constant_p): New function. (xxspltib_constant_p): If we can generate XXSPLTIW don't return true for generating XXSPLTIB and extend operations. (output_vec_const_move): Add support for generating XXSPLTIW for V4SI moves. (rs6000_expand_vector_init): Add support for generating XXSPLTIW for V4SI moves. Diff: --- gcc/config/rs6000/altivec.md | 17 +++------ gcc/config/rs6000/predicates.md | 4 -- gcc/config/rs6000/rs6000-protos.h | 1 - gcc/config/rs6000/rs6000.c | 78 --------------------------------------- 4 files changed, 6 insertions(+), 94 deletions(-) diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index ec071bbd0a4..e2e17fe90ea 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -820,20 +820,15 @@ "vsdbi %0,%1,%2,%3" [(set_attr "type" "vecsimple")]) -;; Generate VSPLTIW, XXSPLITB, or XXSPLTIW to load up V4SI constants. (define_insn "xxspltiw_v4si" - [(set (match_operand:V4SI 0 "vsx_register_operand" "=wa,wa,v,wa") - (vec_duplicate:V4SI - (match_operand:SI 1 "s32bit_cint_operand" "O,wM,wB,n")))] + [(set (match_operand:V4SI 0 "register_operand" "=wa") + (unspec:V4SI [(match_operand:SI 1 "s32bit_cint_operand" "n")] + UNSPEC_XXSPLTIW))] "TARGET_POWER10" - "@ - xxspltib %x0,0 - xxspltib %x0,255 - vspltisw %0,%1 - xxspltiw %x0,%1" + "xxspltiw %x0,%1" [(set_attr "type" "vecperm") - (set_attr "prefixed" "*,*,*,yes") - (set_attr "prefixed_prepend_p" "*,*,*,no")]) + (set_attr "prefixed" "yes") + (set_attr "prefixed_prepend_p" "no")]) (define_expand "xxspltiw_v4sf" [(set (match_operand:V4SF 0 "register_operand" "=wa") diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index 0c5d7a096f3..859af75dfbd 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -649,14 +649,10 @@ { int value = 256; int num_insns = -1; - rtx constant; if (zero_constant (op, mode) || all_ones_constant (op, mode)) return true; - if (TARGET_POWER10 && xxspltiw_constant_p (op, mode, &constant)) - return true; - if (TARGET_P9_VECTOR && xxspltib_constant_p (op, mode, &num_insns, &value)) return true; diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h index 46a7d7f7de9..52436fc1637 100644 --- a/gcc/config/rs6000/rs6000-protos.h +++ b/gcc/config/rs6000/rs6000-protos.h @@ -32,7 +32,6 @@ extern void init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, int, int, int, extern bool easy_altivec_constant (rtx, machine_mode); extern bool xxspltib_constant_p (rtx, machine_mode, int *, int *); -extern bool xxspltiw_constant_p (rtx, machine_mode, rtx *); extern int vspltis_shifted (rtx); extern HOST_WIDE_INT const_vector_elt_as_int (rtx, unsigned int); extern bool macho_lo_sum_memory_operand (rtx, machine_mode); diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 3600af26133..f3ee3a7ea22 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -6320,51 +6320,6 @@ gen_easy_altivec_constant (rtx op) gcc_unreachable (); } -/* Return true if OP is of the given MODE and can be generated with the ISA 3.1 - XXSPLTIW instruction. Return the SImode/SFmode/DFmode constant via the - pointer CONSTANT_PTR. */ - -bool -xxspltiw_constant_p (rtx op, machine_mode mode, rtx *constant_ptr) -{ - *constant_ptr = NULL_RTX; - - if (!TARGET_POWER10) - return false; - - if (mode == VOIDmode) - mode = GET_MODE (op); - - else if (mode != GET_MODE (op)) - return false; - - if (mode != V4SImode) - return false; - - rtx element; - - /* Handle (vec_duplicate ). */ - if (GET_CODE (op) == VEC_DUPLICATE) - element = XEXP (op, 0); - - /* Handle (const_vector [...]). */ - else if (GET_CODE (op) == CONST_VECTOR) - { - size_t nunits = GET_MODE_NUNITS (mode); - element = CONST_VECTOR_ELT (op, 0); - - for (size_t i = 1; i < nunits; i++) - if (!rtx_equal_p (element, CONST_VECTOR_ELT (op, i))) - return false; - } - - else - return false; - - *constant_ptr = element; - return true; -} - /* Return true if OP is of the given MODE and can be synthesized with ISA 3.0 instructions (xxspltib, vupkhsb/vextsb2w/vextb2d). @@ -6397,12 +6352,6 @@ xxspltib_constant_p (rtx op, else if (mode != GET_MODE (op) && GET_MODE (op) != VOIDmode) return false; - /* If we can handle the constant directly with XXSPLTIW, don't both using - XXSPLTIB and vector extend. */ - rtx constant; - if (xxspltiw_constant_p (op, mode, &constant)) - return false; - /* Handle (vec_duplicate ). */ if (GET_CODE (op) == VEC_DUPLICATE) { @@ -6497,7 +6446,6 @@ output_vec_const_move (rtx *operands) int shift; machine_mode mode; rtx dest, vec; - rtx element; dest = operands[0]; vec = operands[1]; @@ -6536,24 +6484,6 @@ output_vec_const_move (rtx *operands) gcc_unreachable (); } - /* See if we can generate a XXSPLTIW directly. */ - if (TARGET_POWER10 && xxspltiw_constant_p (vec, mode, &element)) - { - int r = reg_or_subregno (dest); - - if (CONST_INT_P (element)) - operands[2] = element; - else - gcc_unreachable (); - - HOST_WIDE_INT value = INTVAL (operands[2]); - if (IN_RANGE (value, -16, 15) && ALTIVEC_REGNO_P (r)) - return "vspltisw %0,%2"; - - else - return "xxspltiw %x0,%2"; - } - if (TARGET_P9_VECTOR && xxspltib_constant_p (vec, mode, &num_insns, &xxspltib_value)) { @@ -6635,14 +6565,6 @@ rs6000_expand_vector_init (rtx target, rtx vals) if (n_var == 0) { - /* Generate XXSPLTIW if we can. */ - if (TARGET_POWER10 && all_same && mode == V4SImode) - { - rtx dup = gen_rtx_VEC_DUPLICATE (mode, XVECEXP (vals, 0, 0)); - emit_insn (gen_rtx_SET (target, dup)); - return; - } - rtx const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)); bool int_vector_p = (GET_MODE_CLASS (mode) == MODE_VECTOR_INT); if ((int_vector_p || TARGET_VSX) && all_const_zero)