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* [gcc r11-7904] aarch64: Prevent use of SIMD fcvtz[su] instruction variant with "nosimd"
@ 2021-03-30 10:43 Richard Sandiford
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From: Richard Sandiford @ 2021-03-30 10:43 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:cc2fda1328ee69b92724d6b3cffb741f07d86047
commit r11-7904-gcc2fda1328ee69b92724d6b3cffb741f07d86047
Author: Mihailo Stojanovic <mihailo.stojanovic@typhoon-hil.com>
Date: Tue Mar 30 11:42:49 2021 +0100
aarch64: Prevent use of SIMD fcvtz[su] instruction variant with "nosimd"
Currently, SF->SI and DF->DI conversions on Aarch64 with the "nosimd"
flag provided sometimes cause the emitting of a vector variant of the
fcvtz[su] instruction (e.g. fcvtzu s0, s0).
This modifies the corresponding pattern to only select the vector
variant of the instruction when generating code with SIMD enabled.
gcc/ChangeLog:
* config/aarch64/aarch64.md
(<optab>_trunc<fcvt_target><GPI:mode>2): Set the "arch"
attribute to disambiguate between SIMD and FP variants of the
instruction.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/fcvt_nosimd.c: New test.
Diff:
---
gcc/config/aarch64/aarch64.md | 3 ++-
gcc/testsuite/gcc.target/aarch64/fcvt_nosimd.c | 23 +++++++++++++++++++++++
2 files changed, 25 insertions(+), 1 deletion(-)
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index b2abb5b5b3c..dd1dc2bd7a8 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -5989,7 +5989,8 @@
"@
fcvtz<su>\t%<s>0, %<s>1
fcvtz<su>\t%<w>0, %<s>1"
- [(set_attr "type" "neon_fp_to_int_s,f_cvtf2i")]
+ [(set_attr "type" "neon_fp_to_int_s,f_cvtf2i")
+ (set_attr "arch" "simd,fp")]
)
;; Convert HF -> SI or DI
diff --git a/gcc/testsuite/gcc.target/aarch64/fcvt_nosimd.c b/gcc/testsuite/gcc.target/aarch64/fcvt_nosimd.c
new file mode 100644
index 00000000000..7b2ab65e307
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/fcvt_nosimd.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-march=armv8-a+nosimd" } */
+
+#include <stdint.h>
+
+uint64_t test_double_to_uint64(double x) {
+ return (uint64_t)x;
+}
+
+int64_t test_double_to_int64(double x) {
+ return (int64_t)x;
+}
+
+uint32_t test_float_to_uint32(float x) {
+ return (uint32_t)x;
+}
+
+int32_t test_float_to_int32(float x) {
+ return (int32_t)x;
+}
+
+/* { dg-final { scan-assembler-not {\tfcvtz[su]\td[0-9]*, d[0-9]*} } } */
+/* { dg-final { scan-assembler-not {\tfcvtz[su]\ts[0-9]*, s[0-9]*} } } */
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