[gcc(refs/users/meissner/heads/work043)] Generate XXSPLTIW for V8HI constants.

[Michael Meissner <meissner@gcc.gnu.org>]

https://gcc.gnu.org/g:729e9739facd6e1f0fb9cb82565c28b84aa54d3f

commit 729e9739facd6e1f0fb9cb82565c28b84aa54d3f
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Wed Mar 31 15:01:35 2021 -0400

    Generate XXSPLTIW for V8HI constants.
    
    This code adds support for using XXSPLTIW to generate vector short
    constants.
    
    gcc/
    2021-03-31  Michael Meissner  <meissner@linux.ibm.com>
    
            * config/rs6000/altivec.md (xxspltiw_v8hi): New insn.
            * config/rs6000/rs6000.c (xxspltiw_constant_p): Add support for
            V8HImode constants.
            (output_vec_const_move): Add support for V8HImode constants.
            (rs6000_expand_vector_init): Use VEC_DUPLICATE for identical
            vector V8HI constants.

Diff:
---
 gcc/config/rs6000/altivec.md | 28 +++++++++++++++++++++++++-
 gcc/config/rs6000/rs6000.c   | 48 +++++++++++++++++++++++++++++++++++---------
 2 files changed, 65 insertions(+), 11 deletions(-)

diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 939ae5d0d84..b108b7a688a 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -817,7 +817,33 @@
   "vs<SLDB_lr>dbi %0,%1,%2,%3"
   [(set_attr "type" "vecsimple")])
 
-;; Generate VSPLTIW, XXSPLITB, or XXSPLTIW to load up V4SI constants.
+;; Generate VSPLTIW, XXSPLITB, or XXSPLTIW to load up V4SI/V8HI/V4SF constants.
+(define_insn "*xxspltiw_v8hi"
+  [(set (match_operand:V8HI 0 "vsx_register_operand" "=wa,wa,v,wa")
+	(vec_duplicate:V8HI
+	 (match_operand 1 "short_cint_operand" "O,wM,wB,n")))]
+ "TARGET_POWER10"
+{
+  int value = INTVAL (operands[1]);
+
+  if (value == 0)
+    return "xxspltib %x0,0";
+
+  else if (value == -1)
+    return "xxspltib %x0,255";
+
+  int r = reg_or_subregno (operands[0]);
+  if (IN_RANGE (value, -16, 15) && ALTIVEC_REGNO_P (r))
+    return "vspltish %0,%1";
+
+  int tmp = value & 0xffff;
+  operands[2] = GEN_INT ((tmp << 16) | tmp);
+  return "xxspltiw %x0,%2";
+}
+ [(set_attr "type" "vecperm")
+  (set_attr "prefixed" "*,*,*,yes")
+  (set_attr "prefixed_prepend_p" "*,*,*,no")])
+
 (define_insn "xxspltiw_v4si"
   [(set (match_operand:V4SI 0 "vsx_register_operand" "=wa,wa,v,wa")
        (vec_duplicate:V4SI
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index eb7356a871a..a076c4e67dc 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -6408,7 +6408,7 @@ xxspltiw_constant_p (rtx op, machine_mode mode, rtx *constant_ptr)
   else if (mode != GET_MODE (op))
     return false;
 
-  if (mode != V4SImode && mode != V4SFmode)
+  if (mode != V4SImode && mode != V4SFmode && mode != V8HImode)
     return false;
 
   rtx element;
@@ -6606,22 +6606,49 @@ output_vec_const_move (rtx *operands)
 	    gcc_unreachable ();
 	}
 
-      /* See if we can generate a XXSPLTIW directly.  */
+      /* See if we can use the ISA 3.1 XXSPLTIW instruction.  Generate the
+	 shorter VSPLTISH/VSPLTISW if possible.  */
       if (TARGET_POWER10 && xxspltiw_constant_p (vec, mode, &element))
 	{
+	  HOST_WIDE_INT value, tmp;
+
 	  if (CONST_INT_P (element))
-	    operands[2] = element;
+	    value = INTVAL (element);
 	  else if (CONST_DOUBLE_P (element))
-	    operands[2] = GEN_INT (rs6000_const_f32_to_i32 (element));
+	    value = rs6000_const_f32_to_i32 (element);
 	  else
 	    gcc_unreachable ();
 
-	  HOST_WIDE_INT value = INTVAL (operands[2]);
-	  if (IN_RANGE (value, -16, 15) && dest_vmx_p && mode == V4SImode)
-	    return "vspltisw %0,%2";
+	  switch (mode)
+	    {
+	    case E_V8HImode:
+	      if (IN_RANGE (value, -16, 15) && dest_vmx_p)
+		{
+		  operands[2] = GEN_INT (value);
+		  return "vspltish %0,%2";
+		}
 
-	  else
-	    return "xxspltiw %x0,%2";
+	      tmp = value & 0xffff;
+	      operands[2] = GEN_INT ((tmp << 16) | tmp);
+	      return "xxspltiw %x0,%2";
+
+	    case E_V4SImode:
+	      if (IN_RANGE (value, -16, 15) && dest_vmx_p)
+		{
+		  operands[2] = GEN_INT (value);
+		  return "vspltisw %0,%2";
+		}
+
+	      operands[2] = GEN_INT (value & 0xffffffff);
+	      return "xxspltiw %x0,%2";
+
+	    case E_V4SFmode:
+	      operands[2] = GEN_INT (value & 0xffffffff);
+	      return "xxspltiw %x0,%2";
+
+	    default:
+	      break;
+	    }
 	}
 
       if (TARGET_P9_VECTOR
@@ -6706,7 +6733,8 @@ rs6000_expand_vector_init (rtx target, rtx vals)
   if (n_var == 0)
     {
       /* Generate XXSPLTIW if we can.  */
-      if (TARGET_POWER10 && all_same && (mode == V4SImode || mode == V4SFmode))
+      if (TARGET_POWER10 && all_same
+	  && (mode == V4SImode || mode == V4SFmode || mode == V8HImode))
 	{
 	  rtx dup = gen_rtx_VEC_DUPLICATE (mode, XVECEXP (vals, 0, 0));
 	  emit_insn (gen_rtx_SET (target, dup));