[gcc(refs/users/meissner/heads/work044)] Revert patch.

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* [gcc(refs/users/meissner/heads/work044)] Revert patch.
@ 2021-04-02 19:53 Michael Meissner
  0 siblings, 0 replies; 6+ messages in thread
From: Michael Meissner @ 2021-04-02 19:53 UTC (permalink / raw)
  To: gcc-cvs

https://gcc.gnu.org/g:5f5234fa3431144ace6635a65cfedaf735e605be

commit 5f5234fa3431144ace6635a65cfedaf735e605be
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Apr 2 15:52:46 2021 -0400

    Revert patch.
    
    gcc/testsuite/
    2021-04-02  Michael Meissner  <meissner@linux.ibm.com>
    
            Revert patch
            * gcc.target/powerpc/vec-splati-runnable.c: Update insn count.

Diff:
---
 gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c b/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
index 8edabe97cb0..f65a336b69c 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
@@ -160,6 +160,8 @@ main (int argc, char *argv [])
   return 0;
 }
 
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mxxspltiw\M} 2 } } */
 /* { dg-final { scan-assembler-times {\mxxspltidp\M} 2 } } */
 /* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 3 } } */
+
+


^ permalink raw reply	[flat|nested] 6+ messages in thread

* [gcc(refs/users/meissner/heads/work044)] Revert patch.
@ 2021-04-05 21:47 Michael Meissner
  0 siblings, 0 replies; 6+ messages in thread
From: Michael Meissner @ 2021-04-05 21:47 UTC (permalink / raw)
  To: gcc-cvs

https://gcc.gnu.org/g:ac244c7244f2be73073250e881475052f62156c2

commit ac244c7244f2be73073250e881475052f62156c2
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Mon Apr 5 17:46:42 2021 -0400

    Revert patch.
    
    gcc/
    2021-04-05  Michael Meissner  <meissner@linux.ibm.com>
    
            Revert patch.
            * config/rs6000/altivec.md (UNSPEC_XXSPLTI{D,32DX}): Move to
            rs6000.md.
            * config/rs6000/rs6000.md (UNSPEC_XXSPLTI{D,32DX}): Move from
            altivec.md.

Diff:
---
 gcc/config/rs6000/altivec.md | 2 ++
 gcc/config/rs6000/rs6000.md  | 2 --
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index eeb68dfd793..b3de51b6dd5 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -176,6 +176,8 @@
    UNSPEC_VSTRIL
    UNSPEC_SLDB
    UNSPEC_SRDB
+   UNSPEC_XXSPLTID
+   UNSPEC_XXSPLTI32DX
    UNSPEC_XXBLEND
    UNSPEC_XXPERMX
 ])
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index bebd7b11141..ca4a4d01f05 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -154,8 +154,6 @@
    UNSPEC_CNTTZDM
    UNSPEC_PDEPD
    UNSPEC_PEXTD
-   UNSPEC_XXSPLTID
-   UNSPEC_XXSPLTI32DX
   ])
 
 ;;


^ permalink raw reply	[flat|nested] 6+ messages in thread

* [gcc(refs/users/meissner/heads/work044)] Revert patch.
@ 2021-04-03  2:09 Michael Meissner
  0 siblings, 0 replies; 6+ messages in thread
From: Michael Meissner @ 2021-04-03  2:09 UTC (permalink / raw)
  To: gcc-cvs

https://gcc.gnu.org/g:7e82de323617ab7b4079bc85438fc33556807444

commit 7e82de323617ab7b4079bc85438fc33556807444
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Apr 2 22:09:01 2021 -0400

    Revert patch.
    
    gcc/
    2021-04-02  Michael Meissner  <meissner@linux.ibm.com>
    
            Revert patch.
            * config/rs6000/altivec.md (UNSPEC_XXSPLTIW): Delete.
            (xxspltiw_v4si): Rewrite to load a vector constant.
            (xxspltiw_v4sf): Rewrite to load a vector constant.
            (xxspltiw_v4sf_inst): Delete.
    
    gcc/testsuite/
    2021-04-02  Michael Meissner  <meissner@linux.ibm.com>
    
            Revert patch.
            * gcc.target/powerpc/vec-splati-runnable.c: Update insn count.

Diff:
---
 gcc/config/rs6000/altivec.md                       | 38 +++++++++++++---------
 .../gcc.target/powerpc/vec-splati-runnable.c       |  2 +-
 2 files changed, 23 insertions(+), 17 deletions(-)

diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index b3de51b6dd5..1351dafbc41 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -176,6 +176,7 @@
    UNSPEC_VSTRIL
    UNSPEC_SLDB
    UNSPEC_SRDB
+   UNSPEC_XXSPLTIW
    UNSPEC_XXSPLTID
    UNSPEC_XXSPLTI32DX
    UNSPEC_XXBLEND
@@ -819,30 +820,35 @@
   "vs<SLDB_lr>dbi %0,%1,%2,%3"
   [(set_attr "type" "vecsimple")])
 
-(define_expand "xxspltiw_v4si"
-  [(use (match_operand:V4SI 0 "register_operand"))
-   (use (match_operand:SI 1 "s32bit_cint_operand"))]
+(define_insn "xxspltiw_v4si"
+  [(set (match_operand:V4SI 0 "register_operand" "=wa")
+	(unspec:V4SI [(match_operand:SI 1 "s32bit_cint_operand" "n")]
+		     UNSPEC_XXSPLTIW))]
  "TARGET_POWER10"
-{
-  rtx op1 = operands[1];
-  rtvec rv = gen_rtvec (4, op1, op1, op1, op1, op1);
-  rtx cv = gen_rtx_CONST_VECTOR (V4SImode, rv);
-  emit_move_insn (operands[0], cv);
-  DONE;
-})
+ "xxspltiw %x0,%1"
+ [(set_attr "type" "vecsimple")
+  (set_attr "prefixed" "yes")])
 
 (define_expand "xxspltiw_v4sf"
-  [(use (match_operand:V4SF 0 "register_operand"))
-   (use (match_operand:SF 1 "const_double_operand"))]
+  [(set (match_operand:V4SF 0 "register_operand" "=wa")
+	(unspec:V4SF [(match_operand:SF 1 "const_double_operand" "n")]
+		     UNSPEC_XXSPLTIW))]
  "TARGET_POWER10"
 {
-  rtx op1 = operands[1];
-  rtvec rv = gen_rtvec (4, op1, op1, op1, op1, op1);
-  rtx cv = gen_rtx_CONST_VECTOR (V4SFmode, rv);
-  emit_move_insn (operands[0], cv);
+  long long value = rs6000_const_f32_to_i32 (operands[1]);
+  emit_insn (gen_xxspltiw_v4sf_inst (operands[0], GEN_INT (value)));
   DONE;
 })
 
+(define_insn "xxspltiw_v4sf_inst"
+  [(set (match_operand:V4SF 0 "register_operand" "=wa")
+	(unspec:V4SF [(match_operand:SI 1 "c32bit_cint_operand" "n")]
+		     UNSPEC_XXSPLTIW))]
+ "TARGET_POWER10"
+ "xxspltiw %x0,%1"
+ [(set_attr "type" "vecsimple")
+  (set_attr "prefixed" "yes")])
+
 (define_expand "xxspltidp_v2df"
   [(set (match_operand:V2DF 0 "register_operand" )
 	(unspec:V2DF [(match_operand:SF 1 "const_double_operand")]
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c b/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
index a39ddcfee41..8edabe97cb0 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
@@ -162,4 +162,4 @@ main (int argc, char *argv [])
 
 /* { dg-final { scan-assembler-times {\mxxspltiw\M} 3 } } */
 /* { dg-final { scan-assembler-times {\mxxspltidp\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 3 } } */


^ permalink raw reply	[flat|nested] 6+ messages in thread

* [gcc(refs/users/meissner/heads/work044)] Revert patch.
@ 2021-04-02 19:51 Michael Meissner
  0 siblings, 0 replies; 6+ messages in thread
From: Michael Meissner @ 2021-04-02 19:51 UTC (permalink / raw)
  To: gcc-cvs

https://gcc.gnu.org/g:dc947f6c16c039867f01237df26e94da62a7c29d

commit dc947f6c16c039867f01237df26e94da62a7c29d
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Apr 2 15:51:06 2021 -0400

    Revert patch.
    
    Switch power10 XXSPLTIW built-ins to use VEC_DUPLICATE.
    
    This patch switches the power10 vec_splati and vec_splatid built-in
    functions to use the XXSPLTIB support instead of using UNSPECs.
    
    gcc/
    2021-04-02  Michael Meissner  <meissner@linux.ibm.com>
    
            Revert patch.
            * config/rs6000/altivec.md (UNSPEC_XXSPLTIW): Delete.
            (xxspltiw_v4si): Rewrite to use VEC_DUPLICATE.
            (xxspltiw_v4sf): Rewrite to use VEC_DUPLICATE.
            (xxspltiw_v4sf_inst): Delete.

Diff:
---
 gcc/config/rs6000/altivec.md                       | 48 ++++++++++++----------
 .../gcc.target/powerpc/vec-splati-runnable.c       |  4 +-
 2 files changed, 27 insertions(+), 25 deletions(-)

diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 65148b0986c..1351dafbc41 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -176,6 +176,7 @@
    UNSPEC_VSTRIL
    UNSPEC_SLDB
    UNSPEC_SRDB
+   UNSPEC_XXSPLTIW
    UNSPEC_XXSPLTID
    UNSPEC_XXSPLTI32DX
    UNSPEC_XXBLEND
@@ -820,31 +821,34 @@
   [(set_attr "type" "vecsimple")])
 
 (define_insn "xxspltiw_v4si"
-  [(set (match_operand:V4SI 0 "register_operand" "=wa,wa,v,wa")
-	(vec_duplicate:V4SI
-	 (match_operand 1 "s32bit_cint_operand" "O,wM,wB,n")))]
- "TARGET_XXSPLTIW"
- "@
-  xxspltisb %x0,0
-  xxspltisb %x0,255
-  vspltisw %0,%1
-  xxspltiw %x0,%1"
- [(set_attr "type" "vecperm")
-  (set_attr "prefixed" "*,*,*,yes")])
-
-(define_insn "xxspltiw_v4sf"
-  [(set (match_operand:V4SF 0 "register_operand" "=wa,wa")
-	(vec_duplicate:V4SF
-	 (match_operand:SF 1 "const_double_operand" "F,F")))]
-  "TARGET_XXSPLTIW"
-{
-  if (operands[1] == CONST0_RTX (SFmode))
-    return "xxspltib %x0,0";
+  [(set (match_operand:V4SI 0 "register_operand" "=wa")
+	(unspec:V4SI [(match_operand:SI 1 "s32bit_cint_operand" "n")]
+		     UNSPEC_XXSPLTIW))]
+ "TARGET_POWER10"
+ "xxspltiw %x0,%1"
+ [(set_attr "type" "vecsimple")
+  (set_attr "prefixed" "yes")])
 
-  operands[2] = GEN_INT (rs6000_const_f32_to_i32 (operands[1]));
-  return "xxspltiw %x0,%2";
+(define_expand "xxspltiw_v4sf"
+  [(set (match_operand:V4SF 0 "register_operand" "=wa")
+	(unspec:V4SF [(match_operand:SF 1 "const_double_operand" "n")]
+		     UNSPEC_XXSPLTIW))]
+ "TARGET_POWER10"
+{
+  long long value = rs6000_const_f32_to_i32 (operands[1]);
+  emit_insn (gen_xxspltiw_v4sf_inst (operands[0], GEN_INT (value)));
+  DONE;
 })
 
+(define_insn "xxspltiw_v4sf_inst"
+  [(set (match_operand:V4SF 0 "register_operand" "=wa")
+	(unspec:V4SF [(match_operand:SI 1 "c32bit_cint_operand" "n")]
+		     UNSPEC_XXSPLTIW))]
+ "TARGET_POWER10"
+ "xxspltiw %x0,%1"
+ [(set_attr "type" "vecsimple")
+  (set_attr "prefixed" "yes")])
+
 (define_expand "xxspltidp_v2df"
   [(set (match_operand:V2DF 0 "register_operand" )
 	(unspec:V2DF [(match_operand:SF 1 "const_double_operand")]
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c b/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
index f65a336b69c..8edabe97cb0 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
@@ -160,8 +160,6 @@ main (int argc, char *argv [])
   return 0;
 }
 
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mxxspltiw\M} 3 } } */
 /* { dg-final { scan-assembler-times {\mxxspltidp\M} 2 } } */
 /* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 3 } } */
-
-


^ permalink raw reply	[flat|nested] 6+ messages in thread

* [gcc(refs/users/meissner/heads/work044)] Revert patch.
@ 2021-04-02 16:46 Michael Meissner
  0 siblings, 0 replies; 6+ messages in thread
From: Michael Meissner @ 2021-04-02 16:46 UTC (permalink / raw)
  To: gcc-cvs

https://gcc.gnu.org/g:dc9fc6a1f0058a2f10a2b2971077063c67594b0c

commit dc9fc6a1f0058a2f10a2b2971077063c67594b0c
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Apr 2 12:46:23 2021 -0400

    Revert patch.
    
    gcc/
    2021-04-02  Michael Meissner  <meissner@linux.ibm.com>
    
            Revert patch.
            * config/rs6000/predicates.md (xxspltiw_operand): New predicate.
            (easy_vector_constant): Add XXSPLTIW support.
            * config/rs6000/rs6000-cpus.def (ISA_3_1_MASKS_SERVER): Add
            -mxxspltiw.
            (POWERPC_MASKS): Add -mxxspltiw.
            * config/rs6000/rs6000-protos.h (xxspltiw_constant_p): New
            declaration.
            * config/rs6000/rs6000.c (rs6000_option_override_internal): Set up
            -mxxspltiw.
            (xxspltib_constant_p): Don't return true if we could use XXSPLTIW
            instead of a 2 instruction sequence.
            (xxspltiw_constant_p): New function.
            * config/rs6000/rs6000.opt (-mxxspltiw): New option.
            * config/rs6000/vsx.md (xxspltiwv4si): New insn.

Diff:
---
 gcc/config/rs6000/predicates.md   | 17 -------------
 gcc/config/rs6000/rs6000-cpus.def |  7 +++---
 gcc/config/rs6000/rs6000-protos.h |  1 -
 gcc/config/rs6000/rs6000.c        | 51 ---------------------------------------
 gcc/config/rs6000/rs6000.opt      |  4 ---
 gcc/config/rs6000/vsx.md          | 17 -------------
 6 files changed, 3 insertions(+), 94 deletions(-)

diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index aaf8697ead0..e21bc745f72 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -640,20 +640,6 @@
   return num_insns == 1;
 })
 
-;; Return 1 if the operand is a CONST_VECTOR and can be loaded into a vector
-;; using the ISA 3.1 XXSPLTIW instruction.  Do not return 1 if the value can be
-;; loaded with a smaller XXSPLTIB or VSPLTISW instruction.
-(define_predicate "xxspltiw_operand"
-  (match_code "vec_duplicate,const_vector")
-{
-  long value = 0;
-
-  if (!xxspltiw_constant_p (op, mode, &value))
-    return false;
-
-  return !EASY_VECTOR_15 (value);
-})
-
 ;; Return 1 if the operand is a CONST_VECTOR and can be loaded into a
 ;; vector register without using memory.
 (define_predicate "easy_vector_constant"
@@ -667,9 +653,6 @@
       if (zero_constant (op, mode) || all_ones_constant (op, mode))
 	return true;
 
-      if (xxspltiw_operand (op, mode))
-	return true;
-
       if (TARGET_P9_VECTOR
           && xxspltib_constant_p (op, mode, &num_insns, &value))
 	return true;
diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def
index a21a95bc7aa..cbbb42c1b3a 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -85,8 +85,7 @@
 				 | OTHER_POWER10_MASKS			\
 				 | OPTION_MASK_P10_FUSION		\
 				 | OPTION_MASK_P10_FUSION_LD_CMPI	\
-				 | OPTION_MASK_P10_FUSION_2LOGICAL	\
-				 | OPTION_MASK_XXSPLTIW)
+				 | OPTION_MASK_P10_FUSION_2LOGICAL)
 
 /* Flags that need to be turned off if -mno-power9-vector.  */
 #define OTHER_P9_VECTOR_MASKS	(OPTION_MASK_FLOAT128_HW		\
@@ -161,8 +160,8 @@
 				 | OPTION_MASK_RECIP_PRECISION		\
 				 | OPTION_MASK_SOFT_FLOAT		\
 				 | OPTION_MASK_STRICT_ALIGN_OPTIONAL	\
-				 | OPTION_MASK_VSX			\
-				 | OPTION_MASK_XXSPLTIW)
+				 | OPTION_MASK_VSX)
+
 #endif
 
 /* This table occasionally claims that a processor does not support a
diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h
index a754e84a68b..8ac30905013 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -32,7 +32,6 @@ extern void init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, int, int, int,
 
 extern bool easy_altivec_constant (rtx, machine_mode);
 extern bool xxspltib_constant_p (rtx, machine_mode, int *, int *);
-extern bool xxspltiw_constant_p (rtx, machine_mode, long *);
 extern int vspltis_shifted (rtx);
 extern HOST_WIDE_INT const_vector_elt_as_int (rtx, unsigned int);
 extern bool macho_lo_sum_memory_operand (rtx, machine_mode);
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 1c01baa590e..5d8775a3510 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -4472,10 +4472,6 @@ rs6000_option_override_internal (bool global_init_p)
       rs6000_isa_flags &= ~OPTION_MASK_MMA;
     }
 
-  if (TARGET_POWER10 && TARGET_VSX
-      && (rs6000_isa_flags_explicit & OPTION_MASK_XXSPLTIW) == 0)
-    rs6000_isa_flags |= OPTION_MASK_XXSPLTIW;
-
   if (!TARGET_PCREL && TARGET_PCREL_OPT)
     rs6000_isa_flags &= ~OPTION_MASK_PCREL_OPT;
 
@@ -6460,11 +6456,6 @@ xxspltib_constant_p (rtx op,
   else if (IN_RANGE (value, -1, 0))
     *num_insns_ptr = 1;
 
-  /* If XXSPLTIW is available, don't return true if we can use that
-     instruction instead of doing 2 instructions. */
-  else if (TARGET_XXSPLTIW && mode == V4SImode)
-    return false;
-
   else
     *num_insns_ptr = 2;
 
@@ -6472,48 +6463,6 @@ xxspltib_constant_p (rtx op,
   return true;
 }
 
-/* Return true if OP is of the given MODE and can be synthesized with ISA 3.1
-   XXSPLTIW instruction, possibly with an sign extension.
-
-   Return the constant that is being split via CONSTANT_PTR.  */
-
-bool
-xxspltiw_constant_p (rtx op,
-		     machine_mode mode,
-		     long *constant_ptr)
-{
-  *constant_ptr = 0;
-
-  if (!TARGET_XXSPLTIW)
-    return false;
-
-  if (mode != SImode && mode != V4SImode)
-    return false;
-
-  rtx element = op;
-  if (GET_CODE (op) == VEC_DUPLICATE)
-    element = op;
-
-  else if (GET_CODE (op) == CONST_VECTOR)
-    {
-      size_t nunits = GET_MODE_NUNITS (mode);
-      element = CONST_VECTOR_ELT (op, 0);
-
-      for (size_t i = 1; i < nunits; i++)
-	if (!rtx_equal_p (element, CONST_VECTOR_ELT (op, i)))
-	  return false;
-    }
-
-  if (!CONST_INT_P (element))
-    return false;
-
-  if (!SIGNED_INTEGER_NBIT_P (INTVAL (element), 32))
-    return false;
-
-  *constant_ptr = INTVAL (element);
-  return true;
-}
-
 const char *
 output_vec_const_move (rtx *operands)
 {
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 9c0ecf75a6d..0dbdf753673 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -619,7 +619,3 @@ Generate (do not generate) MMA instructions.
 
 mrelative-jumptables
 Target Undocumented Var(rs6000_relative_jumptables) Init(1) Save
-
-mxxspltiw
-Target Undocumented Mask(XXSPLTIW) Var(rs6000_isa_flags)
-Generate (do not generate) the XXSPLTIW instruction.
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index a630eee2cb5..bcb92be2f5c 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -1159,23 +1159,6 @@
    (set_attr "length" "8")])
 
 
-;; XXSPLTIW support.
-(define_insn "*xxspltiwv4si"
-  [(set (match_operand:V4SI 0 "vsx_register_operand" "=wa")
-	(match_operand:V4SI 1 "xxspltiw_operand"))]
-  "TARGET_XXSPLTIW"
-{
-  long value = 0;
-
-  if (!xxspltiw_constant_p (operands[1], V4SImode, &value))
-    gcc_unreachable ();
-
-  operands[2] = GEN_INT (value);
-  return "xxspltiw %x0,%2";
-}
- [(set_attr "type" "vecperm")
-  (set_attr "prefixed" "yes")])
-
 ;; Prefer using vector registers over GPRs.  Prefer using ISA 3.0's XXSPLTISB
 ;; or Altivec VSPLITW 0/-1 over XXLXOR/XXLORC to set a register to all 0's or
 ;; all 1's, since the machine does not have to wait for the previous


^ permalink raw reply	[flat|nested] 6+ messages in thread

* [gcc(refs/users/meissner/heads/work044)] Revert patch.
@ 2021-04-02  4:49 Michael Meissner
  0 siblings, 0 replies; 6+ messages in thread
From: Michael Meissner @ 2021-04-02  4:49 UTC (permalink / raw)
  To: gcc-cvs

https://gcc.gnu.org/g:529450ac63cfdfdf038b8e2f16aadac76a0c0940

commit 529450ac63cfdfdf038b8e2f16aadac76a0c0940
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Apr 2 00:48:45 2021 -0400

    Revert patch.
    
    gcc/
    2021-04-01  Michael Meissner  <meissner@linux.ibm.com>
    
            Revert patch
            PR fortran/96983
            * config/rs6000/rs6000.c (rs6000_debug_reg_global): Add more
            debugging for __float128, __ibm128 support.
            (rs6000_option_override_internal): Do not enable __float128 and
            __ibm128 support for Fortran.  On Fortran, make the default long
            double precision to be 128.  Add error messages if the user tries
            to change the long double type between IBM/IEEE on Fortran.
            (rs6000_init_libfuncs): Do not enable __ibm128 support if it is
            disabled.
            * config/rs6000/rs6000.h (FLOAT128_IBM_P): Do not return true if
            __ibm128 was disabled for IFmode/ICmode.
            * config/rs6000/rs6000.md (FP iterator): Do not enable IF mode if
            __ibm128 is disabled.
            (FLOAT128 iterator): Likewise.
            * config/rs6000/rs6000.opt (x_TARGET_IBM128): New variables to
            record whether __ibm128 is supported or not.
            (TARGET_IBM128): Likewise.

Diff:
---
 gcc/ChangeLog.meissner       | 21 ----------
 gcc/config/rs6000/rs6000.c   | 92 +++++++++++---------------------------------
 gcc/config/rs6000/rs6000.h   |  3 +-
 gcc/config/rs6000/rs6000.md  |  4 +-
 gcc/config/rs6000/rs6000.opt |  7 ----
 5 files changed, 25 insertions(+), 102 deletions(-)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index e2c67d802e4..d88f96b67fe 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -6,27 +6,6 @@ work044.patch011:
 	* config/rs6000/rs6000.c (rs6000_const_f32_to_i32): Change return
 	type to long.
 
-work044.patch010:
-2021-04-01  Michael Meissner  <meissner@linux.ibm.com>
-
-	PR fortran/96983
-	* config/rs6000/rs6000.c (rs6000_debug_reg_global): Add more
-	debugging for __float128, __ibm128 support.
-	(rs6000_option_override_internal): Do not enable __float128 and
-	__ibm128 support for Fortran.  On Fortran, make the default long
-	double precision to be 128.  Add error messages if the user tries
-	to change the long double type between IBM/IEEE on Fortran.
-	(rs6000_init_libfuncs): Do not enable __ibm128 support if it is
-	disabled.
-	* config/rs6000/rs6000.h (FLOAT128_IBM_P): Do not return true if
-	__ibm128 was disabled for IFmode/ICmode.
-	* config/rs6000/rs6000.md (FP iterator): Do not enable IF mode if
-	__ibm128 is disabled.
-	(FLOAT128 iterator): Likewise.
-	* config/rs6000/rs6000.opt (x_TARGET_IBM128): New variables to
-	record whether __ibm128 is supported or not.
-	(TARGET_IBM128): Likewise.
-
 work044.patch009:
 2021-04-01  Michael Meissner  <meissner@linux.ibm.com>
 
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 1c7cf451419..5d8775a3510 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -2571,11 +2571,6 @@ rs6000_debug_reg_global (void)
 	       TARGET_IEEEQUAD ? "IEEE" : "IBM");
       fprintf (stderr, DEBUG_FMT_S, "default long double type",
 	       TARGET_IEEEQUAD_DEFAULT ? "IEEE" : "IBM");
-      if (TARGET_FLOAT128_TYPE)
-	fprintf (stderr, DEBUG_FMT_S, "IEEE 128-bit support",
-		 TARGET_FLOAT128_KEYWORD ? "keyword" : "type");
-      if (TARGET_IBM128)
-	fprintf (stderr, DEBUG_FMT_S, "__ibm128 keyword", "true");
     }
   fprintf (stderr, DEBUG_FMT_D, "sched_restricted_insns_priority",
 	   (int)rs6000_sched_restricted_insns_priority);
@@ -4161,20 +4156,12 @@ rs6000_option_override_internal (bool global_init_p)
 	rs6000_isa_flags &= ~OPTION_MASK_BLOCK_OPS_VECTOR_PAIR;
     }
 
-  /* Use long double size to select the appropriate long double.
-
-     On C/C++, We use TYPE_PRECISION to differentiate the 3 different long
-     double types.  We map 128 into the precision used for TFmode.
-
-     Fortran does not have support for the types __float128 and __ibm128, just
-     the default long double type.  For Fortran, we use the precision 128 for
-     the long double type.  */
-  bool is_fortran = lang_GNU_Fortran ();
+  /* Use long double size to select the appropriate long double.  We use
+     TYPE_PRECISION to differentiate the 3 different long double types.  We map
+     128 into the precision used for TFmode.  */
   int default_long_double_size = (RS6000_DEFAULT_LONG_DOUBLE_SIZE == 64
 				  ? 64
-				  : (is_fortran
-				     ? 128
-				     : FLOAT_PRECISION_TFmode));
+				  : FLOAT_PRECISION_TFmode);
 
   /* Set long double size before the IEEE 128-bit tests.  */
   if (!global_options_set.x_rs6000_long_double_type_size)
@@ -4186,7 +4173,7 @@ rs6000_option_override_internal (bool global_init_p)
       else
 	rs6000_long_double_type_size = default_long_double_size;
     }
-  else if (rs6000_long_double_type_size == 128 && !is_fortran)
+  else if (rs6000_long_double_type_size == 128)
     rs6000_long_double_type_size = FLOAT_PRECISION_TFmode;
   else if (global_options_set.x_rs6000_ieeequad)
     {
@@ -4217,25 +4204,17 @@ rs6000_option_override_internal (bool global_init_p)
 	     2.32 or newer.  Only issue one warning.  */
 	  static bool warned_change_long_double;
 
-	  if (!warned_change_long_double)
+	  if (!warned_change_long_double
+	      && (!glibc_supports_ieee_128bit ()
+		  || (!lang_GNU_C () && !lang_GNU_CXX ())))
 	    {
 	      warned_change_long_double = true;
-	      if (is_fortran)
-		error ("Fortran does not support %qs to change the default "
-		       "long double type",
-		       (TARGET_IEEEQUAD
-			? "-mabi=ieeelongdouble"
-			: "-mabi=ibmlongdouble"));
-
-	      else if (!glibc_supports_ieee_128bit ())
-		{
-		  if (TARGET_IEEEQUAD)
-		    warning (OPT_Wpsabi, "Using IEEE extended precision "
-			     "%<long double%>");
-		  else
-		    warning (OPT_Wpsabi, "Using IBM extended precision "
-			     "%<long double%>");
-		}
+	      if (TARGET_IEEEQUAD)
+		warning (OPT_Wpsabi, "Using IEEE extended precision "
+			 "%<long double%>");
+	      else
+		warning (OPT_Wpsabi, "Using IBM extended precision "
+			 "%<long double%>");
 	    }
 	}
     }
@@ -4244,13 +4223,8 @@ rs6000_option_override_internal (bool global_init_p)
      sytems.  In GCC 7, we would enable the IEEE 128-bit floating point
      infrastructure (-mfloat128-type) but not enable the actual __float128 type
      unless the user used the explicit -mfloat128.  In GCC 8, we enable both
-     the keyword as well as the type.
-
-     Fortran does not support separate 128-bit floating point types other than
-     long double, we only enable TARGET_FLOAT128_TYPE if the default long double
-     for Fortran is IEEE-128 bit.  */
-  TARGET_FLOAT128_TYPE = (TARGET_FLOAT128_ENABLE_TYPE && TARGET_VSX
-			  && (!is_fortran || TARGET_IEEEQUAD));
+     the keyword as well as the type.  */
+  TARGET_FLOAT128_TYPE = TARGET_FLOAT128_ENABLE_TYPE && TARGET_VSX;
 
   /* IEEE 128-bit floating point requires VSX support.  */
   if (TARGET_FLOAT128_KEYWORD)
@@ -4264,13 +4238,6 @@ rs6000_option_override_internal (bool global_init_p)
 	  rs6000_isa_flags &= ~(OPTION_MASK_FLOAT128_KEYWORD
 				| OPTION_MASK_FLOAT128_HW);
 	}
-      else if (is_fortran)
-	{
-	  if ((rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_KEYWORD) != 0)
-	    error ("Fortran does not support %qs", "-mfloat128");
-
-	  rs6000_isa_flags &= ~OPTION_MASK_FLOAT128_KEYWORD;
-	}
       else if (!TARGET_FLOAT128_TYPE)
 	{
 	  TARGET_FLOAT128_TYPE = 1;
@@ -4278,22 +4245,8 @@ rs6000_option_override_internal (bool global_init_p)
 	}
     }
 
-  /* Whether the '__ibm128' keywork is enabled.  We enable __ibm128 either if the
-   IEEE 128-bit floating point support is enabled or if the long double support
-   uses the 128-bit IBM extended double format.
-
-   However, we don't enable __ibm128 if the language is Fortran.  Fortran
-   doesn't have the notion of separate types for __ibm128 and __float128, and it
-   wants the precision for the 16 byte floating point type to be 128.  With the
-   3 128-bit types enabled, we use the precision field to identify the separate
-   types.  */
-  TARGET_IBM128 = (!is_fortran
-		   && (TARGET_FLOAT128_TYPE
-		       || (!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128)));
-
-
-  /* Enable the __float128 keyword under Linux by default for C/C++.  */
-  if (TARGET_FLOAT128_TYPE && !TARGET_FLOAT128_KEYWORD && !is_fortran
+  /* Enable the __float128 keyword under Linux by default.  */
+  if (TARGET_FLOAT128_TYPE && !TARGET_FLOAT128_KEYWORD
       && (rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_KEYWORD) == 0)
     rs6000_isa_flags |= OPTION_MASK_FLOAT128_KEYWORD;
 
@@ -11105,11 +11058,10 @@ rs6000_init_libfuncs (void)
 {
   /* __float128 support.  */
   if (TARGET_FLOAT128_TYPE)
-    init_float128_ieee (KFmode);
-
-  /* __ibm128 support.  */
-  if (TARGET_IBM128)
-    init_float128_ibm (IFmode);
+    {
+      init_float128_ibm (IFmode);
+      init_float128_ieee (KFmode);
+    }
 
   /* AIX/Darwin/64-bit Linux quad floating point routines.  */
   if (TARGET_LONG_DOUBLE_128)
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 42489e99ace..e3fb0798622 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -334,8 +334,7 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
 #define FLOAT128_IBM_P(MODE)						\
   ((!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128				\
     && ((MODE) == TFmode || (MODE) == TCmode))				\
-   || (TARGET_HARD_FLOAT && TARGET_IBM128				\
-       && ((MODE) == IFmode || (MODE) == ICmode)))
+   || (TARGET_HARD_FLOAT && ((MODE) == IFmode || (MODE) == ICmode)))
 
 /* Helper macros to say whether a 128-bit floating point type can go in a
    single vector register, or whether it needs paired scalar values.  */
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 6291534a4da..ca4a4d01f05 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -481,7 +481,7 @@
   (SF "TARGET_HARD_FLOAT")
   (DF "TARGET_HARD_FLOAT")
   (TF "TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128")
-  (IF "TARGET_HARD_FLOAT && TARGET_IBM128")
+  (IF "TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128")
   (KF "TARGET_FLOAT128_TYPE")
   (DD "TARGET_DFP")
   (TD "TARGET_DFP")])
@@ -605,7 +605,7 @@
 
 ; Iterator for 128-bit floating point
 (define_mode_iterator FLOAT128 [(KF "TARGET_FLOAT128_TYPE")
-				(IF "TARGET_IBM128")
+				(IF "TARGET_FLOAT128_TYPE")
 				(TF "TARGET_LONG_DOUBLE_128")])
 
 ; Iterator for signbit on 64-bit machines with direct move
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 1fb2c35c1b3..0dbdf753673 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -112,13 +112,6 @@ unsigned char x_TARGET_FLOAT128_TYPE
 Variable
 unsigned char TARGET_FLOAT128_TYPE
 
-;; Whether to enable the __ibm128 support
-TargetSave
-unsigned char x_TARGET_IBM128
-
-Variable
-unsigned char TARGET_IBM128
-
 ;; This option existed in the past, but now is always on.
 mpowerpc
 Target RejectNegative Undocumented Ignore


^ permalink raw reply	[flat|nested] 6+ messages in thread

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