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* [gcc(refs/users/meissner/heads/work044)] Convert XXSPLTIW built-in functions to use VEC_DUPLICATE.
@ 2021-04-03 2:10 Michael Meissner
0 siblings, 0 replies; 2+ messages in thread
From: Michael Meissner @ 2021-04-03 2:10 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:9f16629a853615eaf778ded2ac1e7567af659467
commit 9f16629a853615eaf778ded2ac1e7567af659467
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Apr 2 22:10:13 2021 -0400
Convert XXSPLTIW built-in functions to use VEC_DUPLICATE.
This patch changes the vec_spliti and vec_splitid built-in functions that
generate the XXSPLTIW instruction to use the native code generation
for loading vector constants instead of generating an UNSPEC. These
constants now generate XXSPLTIW directly.
gcc/
2021-04-02 Michael Meissner <meissner@linux.ibm.com>
* config/rs6000/altivec.md (UNSPEC_XXSPLTIW): Delete.
(xxspltiw_v4si): Rewrite to load a vector constant.
(xxspltiw_v4sf): Rewrite to load a vector constant.
(xxspltiw_v4sf_inst): Delete.
gcc/testsuite/
2021-04-02 Michael Meissner <meissner@linux.ibm.com>
* gcc.target/powerpc/vec-splati-runnable.c: Update insn count.
Diff:
---
gcc/config/rs6000/altivec.md | 38 +++++++++-------------
.../gcc.target/powerpc/vec-splati-runnable.c | 2 +-
2 files changed, 17 insertions(+), 23 deletions(-)
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 1351dafbc41..b3de51b6dd5 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -176,7 +176,6 @@
UNSPEC_VSTRIL
UNSPEC_SLDB
UNSPEC_SRDB
- UNSPEC_XXSPLTIW
UNSPEC_XXSPLTID
UNSPEC_XXSPLTI32DX
UNSPEC_XXBLEND
@@ -820,35 +819,30 @@
"vs<SLDB_lr>dbi %0,%1,%2,%3"
[(set_attr "type" "vecsimple")])
-(define_insn "xxspltiw_v4si"
- [(set (match_operand:V4SI 0 "register_operand" "=wa")
- (unspec:V4SI [(match_operand:SI 1 "s32bit_cint_operand" "n")]
- UNSPEC_XXSPLTIW))]
+(define_expand "xxspltiw_v4si"
+ [(use (match_operand:V4SI 0 "register_operand"))
+ (use (match_operand:SI 1 "s32bit_cint_operand"))]
"TARGET_POWER10"
- "xxspltiw %x0,%1"
- [(set_attr "type" "vecsimple")
- (set_attr "prefixed" "yes")])
+{
+ rtx op1 = operands[1];
+ rtvec rv = gen_rtvec (4, op1, op1, op1, op1, op1);
+ rtx cv = gen_rtx_CONST_VECTOR (V4SImode, rv);
+ emit_move_insn (operands[0], cv);
+ DONE;
+})
(define_expand "xxspltiw_v4sf"
- [(set (match_operand:V4SF 0 "register_operand" "=wa")
- (unspec:V4SF [(match_operand:SF 1 "const_double_operand" "n")]
- UNSPEC_XXSPLTIW))]
+ [(use (match_operand:V4SF 0 "register_operand"))
+ (use (match_operand:SF 1 "const_double_operand"))]
"TARGET_POWER10"
{
- long long value = rs6000_const_f32_to_i32 (operands[1]);
- emit_insn (gen_xxspltiw_v4sf_inst (operands[0], GEN_INT (value)));
+ rtx op1 = operands[1];
+ rtvec rv = gen_rtvec (4, op1, op1, op1, op1, op1);
+ rtx cv = gen_rtx_CONST_VECTOR (V4SFmode, rv);
+ emit_move_insn (operands[0], cv);
DONE;
})
-(define_insn "xxspltiw_v4sf_inst"
- [(set (match_operand:V4SF 0 "register_operand" "=wa")
- (unspec:V4SF [(match_operand:SI 1 "c32bit_cint_operand" "n")]
- UNSPEC_XXSPLTIW))]
- "TARGET_POWER10"
- "xxspltiw %x0,%1"
- [(set_attr "type" "vecsimple")
- (set_attr "prefixed" "yes")])
-
(define_expand "xxspltidp_v2df"
[(set (match_operand:V2DF 0 "register_operand" )
(unspec:V2DF [(match_operand:SF 1 "const_double_operand")]
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c b/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
index 8edabe97cb0..58b959b4406 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
@@ -160,6 +160,6 @@ main (int argc, char *argv [])
return 0;
}
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mxxspltiw\M} 1 } } */
/* { dg-final { scan-assembler-times {\mxxspltidp\M} 2 } } */
/* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 3 } } */
^ permalink raw reply [flat|nested] 2+ messages in thread
* [gcc(refs/users/meissner/heads/work044)] Convert XXSPLTIW built-in functions to use VEC_DUPLICATE.
@ 2021-04-03 1:11 Michael Meissner
0 siblings, 0 replies; 2+ messages in thread
From: Michael Meissner @ 2021-04-03 1:11 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:bf295d2781c4afdd7137235af73e8aa42ed4b62a
commit bf295d2781c4afdd7137235af73e8aa42ed4b62a
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Apr 2 21:11:06 2021 -0400
Convert XXSPLTIW built-in functions to use VEC_DUPLICATE.
This patch changes the vec_spliti and vec_splitid built-in functions that
generate the XXSPLTIW instruction to use the native code generation
for loading vector constants instead of generating an UNSPEC. These
constants now generate XXSPLTIW directly.
gcc/
2021-04-02 Michael Meissner <meissner@linux.ibm.com>
* config/rs6000/altivec.md (UNSPEC_XXSPLTIW): Delete.
(xxspltiw_v4si): Rewrite to load a vector constant.
(xxspltiw_v4sf): Rewrite to load a vector constant.
(xxspltiw_v4sf_inst): Delete.
gcc/testsuite/
2021-04-02 Michael Meissner <meissner@linux.ibm.com>
* gcc.target/powerpc/vec-splati-runnable.c: Update insn count.
Diff:
---
gcc/config/rs6000/altivec.md | 38 +++++++++-------------
.../gcc.target/powerpc/vec-splati-runnable.c | 2 +-
2 files changed, 17 insertions(+), 23 deletions(-)
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 1351dafbc41..b3de51b6dd5 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -176,7 +176,6 @@
UNSPEC_VSTRIL
UNSPEC_SLDB
UNSPEC_SRDB
- UNSPEC_XXSPLTIW
UNSPEC_XXSPLTID
UNSPEC_XXSPLTI32DX
UNSPEC_XXBLEND
@@ -820,35 +819,30 @@
"vs<SLDB_lr>dbi %0,%1,%2,%3"
[(set_attr "type" "vecsimple")])
-(define_insn "xxspltiw_v4si"
- [(set (match_operand:V4SI 0 "register_operand" "=wa")
- (unspec:V4SI [(match_operand:SI 1 "s32bit_cint_operand" "n")]
- UNSPEC_XXSPLTIW))]
+(define_expand "xxspltiw_v4si"
+ [(use (match_operand:V4SI 0 "register_operand"))
+ (use (match_operand:SI 1 "s32bit_cint_operand"))]
"TARGET_POWER10"
- "xxspltiw %x0,%1"
- [(set_attr "type" "vecsimple")
- (set_attr "prefixed" "yes")])
+{
+ rtx op1 = operands[1];
+ rtvec rv = gen_rtvec (4, op1, op1, op1, op1, op1);
+ rtx cv = gen_rtx_CONST_VECTOR (V4SImode, rv);
+ emit_move_insn (operands[0], cv);
+ DONE;
+})
(define_expand "xxspltiw_v4sf"
- [(set (match_operand:V4SF 0 "register_operand" "=wa")
- (unspec:V4SF [(match_operand:SF 1 "const_double_operand" "n")]
- UNSPEC_XXSPLTIW))]
+ [(use (match_operand:V4SF 0 "register_operand"))
+ (use (match_operand:SF 1 "const_double_operand"))]
"TARGET_POWER10"
{
- long long value = rs6000_const_f32_to_i32 (operands[1]);
- emit_insn (gen_xxspltiw_v4sf_inst (operands[0], GEN_INT (value)));
+ rtx op1 = operands[1];
+ rtvec rv = gen_rtvec (4, op1, op1, op1, op1, op1);
+ rtx cv = gen_rtx_CONST_VECTOR (V4SFmode, rv);
+ emit_move_insn (operands[0], cv);
DONE;
})
-(define_insn "xxspltiw_v4sf_inst"
- [(set (match_operand:V4SF 0 "register_operand" "=wa")
- (unspec:V4SF [(match_operand:SI 1 "c32bit_cint_operand" "n")]
- UNSPEC_XXSPLTIW))]
- "TARGET_POWER10"
- "xxspltiw %x0,%1"
- [(set_attr "type" "vecsimple")
- (set_attr "prefixed" "yes")])
-
(define_expand "xxspltidp_v2df"
[(set (match_operand:V2DF 0 "register_operand" )
(unspec:V2DF [(match_operand:SF 1 "const_double_operand")]
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c b/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
index 8edabe97cb0..a39ddcfee41 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
@@ -162,4 +162,4 @@ main (int argc, char *argv [])
/* { dg-final { scan-assembler-times {\mxxspltiw\M} 3 } } */
/* { dg-final { scan-assembler-times {\mxxspltidp\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 1 } } */
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