From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 5369A3858012; Tue, 6 Apr 2021 22:41:39 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 5369A3858012 Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work045)] Move XXSPLTIW built-in insns from altivec.md to vsx.md. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work045 X-Git-Oldrev: e135144abf20e077835a1b4b6244daaba572af36 X-Git-Newrev: 1aac46936764be32631642dd4424e9aa665e014f Message-Id: <20210406224139.5369A3858012@sourceware.org> Date: Tue, 6 Apr 2021 22:41:39 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 06 Apr 2021 22:41:39 -0000 https://gcc.gnu.org/g:1aac46936764be32631642dd4424e9aa665e014f commit 1aac46936764be32631642dd4424e9aa665e014f Author: Michael Meissner Date: Tue Apr 6 18:41:19 2021 -0400 Move XXSPLTIW built-in insns from altivec.md to vsx.md. The built-in support for XXSPLTIW was put into the altivec.md file. It is more properly should go in vsx.md, since it can deal with all VSX registers. gcc/ 2021-04-06 Michael Meissner * config/rs6000/altivec.md (UNSPEC_XXSPLTIW): Move to vsx.md. (xxspltiw_v4si): Move to vsx.md. (xxspltiw_v4sf): Move to vsx.md. (xxspltiw_v4sf_inst): Move to vsx.md. * config/rs6000/vsx.md (UNSPEC_XXSPLTIW): Move from altivec.md. (xxspltiw_v4si): Move from altivec.md. (xxspltiw_v4sf): Move from altivec.md. (xxspltiw_v4sf_inst): Move from altivec.md. Diff: --- gcc/config/rs6000/altivec.md | 30 ------------------------------ gcc/config/rs6000/vsx.md | 31 +++++++++++++++++++++++++++++++ 2 files changed, 31 insertions(+), 30 deletions(-) diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index 1351dafbc41..708296cb14d 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -176,7 +176,6 @@ UNSPEC_VSTRIL UNSPEC_SLDB UNSPEC_SRDB - UNSPEC_XXSPLTIW UNSPEC_XXSPLTID UNSPEC_XXSPLTI32DX UNSPEC_XXBLEND @@ -820,35 +819,6 @@ "vsdbi %0,%1,%2,%3" [(set_attr "type" "vecsimple")]) -(define_insn "xxspltiw_v4si" - [(set (match_operand:V4SI 0 "register_operand" "=wa") - (unspec:V4SI [(match_operand:SI 1 "s32bit_cint_operand" "n")] - UNSPEC_XXSPLTIW))] - "TARGET_POWER10" - "xxspltiw %x0,%1" - [(set_attr "type" "vecsimple") - (set_attr "prefixed" "yes")]) - -(define_expand "xxspltiw_v4sf" - [(set (match_operand:V4SF 0 "register_operand" "=wa") - (unspec:V4SF [(match_operand:SF 1 "const_double_operand" "n")] - UNSPEC_XXSPLTIW))] - "TARGET_POWER10" -{ - long long value = rs6000_const_f32_to_i32 (operands[1]); - emit_insn (gen_xxspltiw_v4sf_inst (operands[0], GEN_INT (value))); - DONE; -}) - -(define_insn "xxspltiw_v4sf_inst" - [(set (match_operand:V4SF 0 "register_operand" "=wa") - (unspec:V4SF [(match_operand:SI 1 "c32bit_cint_operand" "n")] - UNSPEC_XXSPLTIW))] - "TARGET_POWER10" - "xxspltiw %x0,%1" - [(set_attr "type" "vecsimple") - (set_attr "prefixed" "yes")]) - (define_expand "xxspltidp_v2df" [(set (match_operand:V2DF 0 "register_operand" ) (unspec:V2DF [(match_operand:SF 1 "const_double_operand")] diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index bcb92be2f5c..bd800c4ce0c 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -369,6 +369,7 @@ UNSPEC_REPLACE_UN UNSPEC_VDIVES UNSPEC_VDIVEU + UNSPEC_XXSPLTIW ]) (define_int_iterator XVCVBF16 [UNSPEC_VSX_XVCVSPBF16 @@ -6216,3 +6217,33 @@ "TARGET_POWER10" "vmulld %0,%1,%2" [(set_attr "type" "veccomplex")]) + + +(define_insn "xxspltiw_v4si" + [(set (match_operand:V4SI 0 "register_operand" "=wa") + (unspec:V4SI [(match_operand:SI 1 "s32bit_cint_operand" "n")] + UNSPEC_XXSPLTIW))] + "TARGET_POWER10" + "xxspltiw %x0,%1" + [(set_attr "type" "vecsimple") + (set_attr "prefixed" "yes")]) + +(define_expand "xxspltiw_v4sf" + [(set (match_operand:V4SF 0 "register_operand" "=wa") + (unspec:V4SF [(match_operand:SF 1 "const_double_operand" "n")] + UNSPEC_XXSPLTIW))] + "TARGET_POWER10" +{ + long long value = rs6000_const_f32_to_i32 (operands[1]); + emit_insn (gen_xxspltiw_v4sf_inst (operands[0], GEN_INT (value))); + DONE; +}) + +(define_insn "xxspltiw_v4sf_inst" + [(set (match_operand:V4SF 0 "register_operand" "=wa") + (unspec:V4SF [(match_operand:SI 1 "c32bit_cint_operand" "n")] + UNSPEC_XXSPLTIW))] + "TARGET_POWER10" + "xxspltiw %x0,%1" + [(set_attr "type" "vecsimple") + (set_attr "prefixed" "yes")])