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* [gcc(refs/users/meissner/heads/work046)] Revert patches.
@ 2021-04-07 18:45 Michael Meissner
0 siblings, 0 replies; 2+ messages in thread
From: Michael Meissner @ 2021-04-07 18:45 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:598fbbd77731e4d077216378b7dc253073895e40
commit 598fbbd77731e4d077216378b7dc253073895e40
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Apr 7 14:44:35 2021 -0400
Revert patches.
gcc/
2021-04-07 Michael Meissner <meissner@linux.ibm.com>
Revert patches.
* config/rs6000/altivec.md (UNSPEC_XXSPLTID): Move to vsx.md and
rename to UNSPEC_XXSPLTID.
(xxspltidp_v2df): Move to vsx.md and re-implement.
(xxspltidp_v2df_inst): Move to vsx.md and re-implement.
* config/rs6000/constraints.md (eF): New constraint.
* config/rs6000/predicates.md (easy_fp_constant): If we load the
scalar constant with XXSPLTIDP, return true.
(xxspltidp_operand): New predicate.
(easy_vector_constant): If we can generate XXSPLTIDP, mark the
vector constant as easy.
* config/rs6000/rs6000-cpus.def (OTHER_POWER10_MASKS): Add
-mxxspltidp support.
(POWERPC_MASKS): Add -mxxspltidp support.
* config/rs6000/rs6000-protos.h (xxspltidp_constant_p): New
declaration.
* config/rs6000/rs6000.c (rs6000_option_override_internal): Add
-mxxspltidp support.
(xxspltidp_constant_p): New function.
(output_vec_const_move): Add support for XXSPLTIDP.
(rs6000_opt_masks): Add -mxxspltidp support.
(rs6000_emit_xxspltidp_v2df): Change function to implement the
XXSPLTIDP instruction.
* config/rs6000/rs6000.md (movsf_hardfloat): Add XXSPLTIDP
support.
(mov<mode>_hardfloat32, FMOVE64 iterator): Add XXSPLTIDP support.
(mov<mode>_hardfloat64, FMOVE64 iterator): Add XXSPLTIDP support.
* config/rs6000/rs6000.opt (-mxxspltidp): New switch.
* config/rs6000/vsx.md (UNSPEC_XXSPLTIDP): Move here from
altivec.md. Rename it to UNSPEC_XXSPLTIDP to match the
instruction.
(vsx_mov<mode>_64bit): Add XXSPLTIDP support.
(vsx_mov<mode>_32bit): Add XXSPLTIDP support.
(XXSPLTIDP): New mode iterator.
(xxspltidp_<mode>_internal1): New define_insn_and_split.
(xxspltidp_<mode>_internal2): New define_insn.
(xxspltidp_v2df): Move to vsx.md from altivec.md. Re-implement to
use the new constant format.
gcc/testsuite/
2021-04-07 Michael Meissner <meissner@linux.ibm.com>
Revert patches.
* gcc.target/powerpc/vec-splati-runnable.c: Set optimization level
to -O2. Add missing abort call. Update insn counts.
* gcc.target/powerpc/xxspltiw-v4sf.c: New test.
* gcc.target/powerpc/xxspltiw-v4si.c: New test.
* gcc.target/powerpc/xxspltiw-v8hi.c: New test.
gcc/
2021-04-07 Michael Meissner <meissner@linux.ibm.com>
Revert patches.
* config/rs6000/altivec.md (UNSPEC_XXSPLTIW): Move to vsx.md.
(xxspltiw_v4si): Move to vsx.md and re-implement.
(xxspltiw_v4sf): Move to vsx.md and re-implement.
(xxspltiw_v4sf_inst): Delete.
* config/rs6000/constraints.md (eW): New constraint.
* config/rs6000/predicates.md (xxspltiw_operand): New predicate.
(easy_vector_constant): If we can generate XXSPLTIW, mark the
vector constant as easy.
* config/rs6000/rs6000-cpus.def (OTHER_POWER10_MASKS): Add
-mxxspltiw support.
(POWERPC_MASKS): Add -mxxspltiw support.
* config/rs6000/rs6000-protos.h (xxspltiw_constant_p): New
declaration.
* config/rs6000/rs6000.c (rs6000_option_override_internal): Add
-mxxspltiw support.
(xxspltib_constant_p): If we can generate XXSPLTIW, don't generate
XXSPLTIB and a vector extend instruction.
(xxspltiw_constant_p): New function.
(output_vec_const_move): Add support for XXSPLTIW.
(rs6000_opt_masks): Add -mxxspltiw support.
* config/rs6000/rs6000.opt (-mxxspltiw): New switch.
* config/rs6000/vsx.md (UNSPEC_XXSPLTIW): Move here from
altivec.md.
(vsx_mov<mode>_64bit): Add XXSPLTIW support.
(vsx_mov<mode>_32bit): Add XXSPLTIW support.
(XXSPLTIW): New mode iterator.
(xxspltiw_<mode>_internal1): New define_insn_and_split.
(xxspltiw_<mode>_internal2): New define_insn.
(xxspltiw_v4si): Move to vsx.md from altivec.md. Re-implement to
use the new constant format.
(xxspltiw_v4sf): Move to vsx.md from altivec.md. Re-implement to
use the new constant format.
Diff:
---
gcc/config/rs6000/altivec.md | 51 +++++++
gcc/config/rs6000/constraints.md | 10 --
gcc/config/rs6000/predicates.md | 43 ------
gcc/config/rs6000/rs6000-cpus.def | 8 +-
gcc/config/rs6000/rs6000-protos.h | 2 -
gcc/config/rs6000/rs6000.c | 170 +--------------------
gcc/config/rs6000/rs6000.md | 34 ++---
gcc/config/rs6000/rs6000.opt | 8 -
gcc/config/rs6000/vsx.md | 138 ++---------------
.../gcc.target/powerpc/vec-splati-runnable.c | 8 +-
gcc/testsuite/gcc.target/powerpc/xxspltiw-v4sf.c | 66 --------
gcc/testsuite/gcc.target/powerpc/xxspltiw-v4si.c | 51 -------
gcc/testsuite/gcc.target/powerpc/xxspltiw-v8hi.c | 53 -------
13 files changed, 85 insertions(+), 557 deletions(-)
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index ad6ead04cfa..1351dafbc41 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -176,6 +176,8 @@
UNSPEC_VSTRIL
UNSPEC_SLDB
UNSPEC_SRDB
+ UNSPEC_XXSPLTIW
+ UNSPEC_XXSPLTID
UNSPEC_XXSPLTI32DX
UNSPEC_XXBLEND
UNSPEC_XXPERMX
@@ -818,6 +820,55 @@
"vs<SLDB_lr>dbi %0,%1,%2,%3"
[(set_attr "type" "vecsimple")])
+(define_insn "xxspltiw_v4si"
+ [(set (match_operand:V4SI 0 "register_operand" "=wa")
+ (unspec:V4SI [(match_operand:SI 1 "s32bit_cint_operand" "n")]
+ UNSPEC_XXSPLTIW))]
+ "TARGET_POWER10"
+ "xxspltiw %x0,%1"
+ [(set_attr "type" "vecsimple")
+ (set_attr "prefixed" "yes")])
+
+(define_expand "xxspltiw_v4sf"
+ [(set (match_operand:V4SF 0 "register_operand" "=wa")
+ (unspec:V4SF [(match_operand:SF 1 "const_double_operand" "n")]
+ UNSPEC_XXSPLTIW))]
+ "TARGET_POWER10"
+{
+ long long value = rs6000_const_f32_to_i32 (operands[1]);
+ emit_insn (gen_xxspltiw_v4sf_inst (operands[0], GEN_INT (value)));
+ DONE;
+})
+
+(define_insn "xxspltiw_v4sf_inst"
+ [(set (match_operand:V4SF 0 "register_operand" "=wa")
+ (unspec:V4SF [(match_operand:SI 1 "c32bit_cint_operand" "n")]
+ UNSPEC_XXSPLTIW))]
+ "TARGET_POWER10"
+ "xxspltiw %x0,%1"
+ [(set_attr "type" "vecsimple")
+ (set_attr "prefixed" "yes")])
+
+(define_expand "xxspltidp_v2df"
+ [(set (match_operand:V2DF 0 "register_operand" )
+ (unspec:V2DF [(match_operand:SF 1 "const_double_operand")]
+ UNSPEC_XXSPLTID))]
+ "TARGET_POWER10"
+{
+ long value = rs6000_const_f32_to_i32 (operands[1]);
+ rs6000_emit_xxspltidp_v2df (operands[0], value);
+ DONE;
+})
+
+(define_insn "xxspltidp_v2df_inst"
+ [(set (match_operand:V2DF 0 "register_operand" "=wa")
+ (unspec:V2DF [(match_operand:SI 1 "c32bit_cint_operand" "n")]
+ UNSPEC_XXSPLTID))]
+ "TARGET_POWER10"
+ "xxspltidp %x0,%1"
+ [(set_attr "type" "vecsimple")
+ (set_attr "prefixed" "yes")])
+
(define_expand "xxsplti32dx_v4si"
[(set (match_operand:V4SI 0 "register_operand" "=wa")
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0")
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index 70b1eb01770..561ce9797af 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -208,21 +208,11 @@
(and (match_code "const_int")
(match_test "((- (unsigned HOST_WIDE_INT) ival) + 0x8000) < 0x10000")))
-;; SF/DF/V2DF scalar or vector constant that can be loaded with XXSPLTIDP
-(define_constraint "eF"
- "A vector constant that can be loaded with the XXSPLTIDP instruction."
- (match_operand 0 "xxspltidp_operand"))
-
;; 34-bit signed integer constant
(define_constraint "eI"
"A signed 34-bit integer constant if prefixed instructions are supported."
(match_operand 0 "cint34_operand"))
-;; V4SI/V4SF/V8HI vector constant that can be loaded with XXSPLTIW
-(define_constraint "eW"
- "A vector constant that can be loaded with the XXSPLTIW instruction."
- (match_operand 0 "xxspltiw_operand"))
-
;; Floating-point constraints. These two are defined so that insn
;; length attributes can be calculated exactly.
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 48d9c5509a2..e21bc745f72 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -601,11 +601,6 @@
if (TARGET_VSX && op == CONST0_RTX (mode))
return 1;
- /* If we have the ISA 3.1 XXSPLTIDP instruction, see if the constant can
- be loaded with that instruction. */
- if (xxspltidp_operand (op, mode))
- return 1;
-
/* Otherwise consider floating point constants hard, so that the
constant gets pushed to memory during the early RTL phases. This
has the advantage that double precision constants that can be
@@ -645,38 +640,6 @@
return num_insns == 1;
})
-;; Return 1 if the operand is a CONST_VECTOR and can be loaded into a vector
-;; using the ISA 3.1 XXSPLTIW instruction. Do not return 1 if the value can be
-;; loaded with a smaller XXSPLTIB or VSPLTISW instruction.
-(define_predicate "xxspltiw_operand"
- (match_code "vec_duplicate,const_vector")
-{
- HOST_WIDE_INT value = 0;
-
- if (!xxspltiw_constant_p (op, mode, &value))
- return false;
-
- /* xxspltiw_constant_p returns V8HI as (element | (element << 16)). Undo
- this to see if the value is in the range -16..15. */
- if (mode == V8HImode)
- value = ((value & 0xffff) ^ 0x8000) - 0x8000;
-
- return !EASY_VECTOR_15 (value);
-})
-
-;; Return 1 if operand is a SF/DF CONST_DOUBLE or V2DF CONST_VECTOR that can be
-;; loaded via the ISA 3.1 XXSPLTIDP instruction. Do not return true if the
-;; value is 0.0, since that is easy to generate without using XXSPLTIDP.
-(define_predicate "xxspltidp_operand"
- (match_code "const_double,const_vector,vec_duplicate")
-{
- if (op == CONST0_RTX (mode))
- return false;
-
- HOST_WIDE_INT value = 0;
- return xxspltidp_constant_p (op, mode, &value);
-})
-
;; Return 1 if the operand is a CONST_VECTOR and can be loaded into a
;; vector register without using memory.
(define_predicate "easy_vector_constant"
@@ -690,12 +653,6 @@
if (zero_constant (op, mode) || all_ones_constant (op, mode))
return true;
- if (xxspltiw_operand (op, mode))
- return true;
-
- if (xxspltidp_operand (op, mode))
- return true;
-
if (TARGET_P9_VECTOR
&& xxspltib_constant_p (op, mode, &num_insns, &value))
return true;
diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def
index cf4044831f7..cbbb42c1b3a 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -78,9 +78,7 @@
#define OTHER_POWER10_MASKS (OPTION_MASK_MMA \
| OPTION_MASK_PCREL \
| OPTION_MASK_PCREL_OPT \
- | OPTION_MASK_PREFIXED \
- | OPTION_MASK_XXSPLTIDP \
- | OPTION_MASK_XXSPLTIW)
+ | OPTION_MASK_PREFIXED)
#define ISA_3_1_MASKS_SERVER (ISA_3_0_MASKS_SERVER \
| OPTION_MASK_POWER10 \
@@ -162,9 +160,7 @@
| OPTION_MASK_RECIP_PRECISION \
| OPTION_MASK_SOFT_FLOAT \
| OPTION_MASK_STRICT_ALIGN_OPTIONAL \
- | OPTION_MASK_VSX \
- | OPTION_MASK_XXSPLTIDP \
- | OPTION_MASK_XXSPLTIW)
+ | OPTION_MASK_VSX)
#endif
diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h
index 0fe1c176236..8ac30905013 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -32,8 +32,6 @@ extern void init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, int, int, int,
extern bool easy_altivec_constant (rtx, machine_mode);
extern bool xxspltib_constant_p (rtx, machine_mode, int *, int *);
-extern bool xxspltiw_constant_p (rtx, machine_mode, HOST_WIDE_INT *);
-extern bool xxspltidp_constant_p (rtx, machine_mode, HOST_WIDE_INT *);
extern int vspltis_shifted (rtx);
extern HOST_WIDE_INT const_vector_elt_as_int (rtx, unsigned int);
extern bool macho_lo_sum_memory_operand (rtx, machine_mode);
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index f023747a578..dc38c093c53 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -4476,14 +4476,6 @@ rs6000_option_override_internal (bool global_init_p)
rs6000_isa_flags &= ~OPTION_MASK_MMA;
}
- if (TARGET_POWER10 && TARGET_VSX
- && (rs6000_isa_flags_explicit & OPTION_MASK_XXSPLTIW) == 0)
- rs6000_isa_flags |= OPTION_MASK_XXSPLTIW;
-
- if (TARGET_POWER10 && TARGET_VSX
- && (rs6000_isa_flags_explicit & OPTION_MASK_XXSPLTIDP) == 0)
- rs6000_isa_flags |= OPTION_MASK_XXSPLTIDP;
-
if (!TARGET_PCREL && TARGET_PCREL_OPT)
rs6000_isa_flags &= ~OPTION_MASK_PCREL_OPT;
@@ -6468,12 +6460,6 @@ xxspltib_constant_p (rtx op,
else if (IN_RANGE (value, -1, 0))
*num_insns_ptr = 1;
- /* If XXSPLTIW is available, don't return true if we can use that
- instruction instead of doing 2 instructions. */
- else if (TARGET_XXSPLTIW
- && (mode == V4SImode || mode == V8HImode))
- return false;
-
else
*num_insns_ptr = 2;
@@ -6481,129 +6467,6 @@ xxspltib_constant_p (rtx op,
return true;
}
-/* Return true if OP is of the given MODE and can be synthesized with ISA 3.1
- XXSPLTIW instruction, possibly with an sign extension.
-
- Return the constant that is being split via CONSTANT_PTR. */
-
-bool
-xxspltiw_constant_p (rtx op,
- machine_mode mode,
- HOST_WIDE_INT *constant_ptr)
-{
- *constant_ptr = 0;
-
- if (!TARGET_XXSPLTIW)
- return false;
-
- if (mode == VOIDmode)
- mode = GET_MODE (op);
-
- if (mode != V8HImode && mode != V4SImode && mode != V4SFmode)
- return false;
-
- rtx element = op;
- if (GET_CODE (op) == VEC_DUPLICATE)
- element = op;
-
- else if (GET_CODE (op) == CONST_VECTOR)
- {
- size_t nunits = GET_MODE_NUNITS (mode);
- element = CONST_VECTOR_ELT (op, 0);
-
- for (size_t i = 1; i < nunits; i++)
- if (!rtx_equal_p (element, CONST_VECTOR_ELT (op, i)))
- return false;
- }
-
- HOST_WIDE_INT value;
- if (CONST_INT_P (element))
- {
- value = INTVAL (element);
- if (!SIGNED_INTEGER_NBIT_P (value, 32))
- return false;
-
- /* For V8HImode, return the value setting 2 elements of the constant. */
- if (mode == V8HImode)
- {
- value &= 0xffff;
- value |= value << 16;
- }
- }
-
- else if (CONST_DOUBLE_P (element))
- value = rs6000_const_f32_to_i32 (element);
-
- else
- return false;
-
- *constant_ptr = value;
- return true;
-}
-
-/* Return true if OP is of the given MODE and can be synthesized with ISA 3.1
- XXSPLTIDP instruction.
-
- Return the constant that is being split via CONSTANT_PTR to use in the
- XXSPLTIDP instruction. */
-
-bool
-xxspltidp_constant_p (rtx op,
- machine_mode mode,
- HOST_WIDE_INT *constant_ptr)
-{
- *constant_ptr = 0;
-
- rtx element = op;
- if (mode == V2DFmode)
- {
- /* Handle VEC_DUPLICATE and CONST_VECTOR. */
- if (GET_CODE (op) == VEC_DUPLICATE)
- element = XEXP (op, 0);
-
- else if (GET_CODE (op) == CONST_VECTOR)
- {
- element = CONST_VECTOR_ELT (op, 0);
- if (!rtx_equal_p (element, CONST_VECTOR_ELT (op, 1)))
- return false;
- }
-
- else
- return false;
-
- mode = DFmode;
- }
-
- if (mode != SFmode && mode != DFmode)
- return false;
-
- if (GET_MODE (element) != mode)
- return false;
-
- if (!CONST_DOUBLE_P (element))
- return false;
-
- /* Don't return true for 0.0 since that is easy to create without
- XXSPLTIDP. */
- if (element == CONST0_RTX (mode))
- return false;
-
- /* If the value doesn't fit in a SFmode, exactly, we can't use XXSPLTIDP. */
- const struct real_value *rv = CONST_DOUBLE_REAL_VALUE (element);
- if (!exact_real_truncate (SFmode, rv))
- return 0;
-
- long value;
- REAL_VALUE_TO_TARGET_SINGLE (*rv, value);
-
- /* Test for SFmode denormal (exponent is 0, mantissa field is non-zero). */
- if (((value & 0x7F800000) == 0) && ((value & 0x7FFFFF) != 0))
- return false;
-
- *constant_ptr = value;
- return true;
-}
-
const char *
output_vec_const_move (rtx *operands)
{
@@ -6648,35 +6511,6 @@ output_vec_const_move (rtx *operands)
gcc_unreachable ();
}
- HOST_WIDE_INT xxspltiw_value = 0;
- if (xxspltiw_constant_p (vec, mode, &xxspltiw_value))
- {
- /* Generate the smaller VSPLTIS{H,W} if we can. */
- if (dest_vmx_p && mode == V8HImode)
- {
- long hi_value = ((xxspltiw_value & 0xffff) ^ 0x8000) - 0x8000;
- if (IN_RANGE (hi_value, -16, 15))
- {
- operands[2] = GEN_INT (hi_value);
- return "vspltish %0,%2";
- }
- }
-
- operands[2] = GEN_INT (xxspltiw_value);
- if (dest_vmx_p && mode == V4SImode
- && IN_RANGE (xxspltiw_value, -16, 15))
- return "vspltisw %0,%2";
-
- return "xxspltiw %x0,%2";
- }
-
- HOST_WIDE_INT xxspltidp_value = 0;
- if (xxspltidp_constant_p (vec, mode, &xxspltidp_value))
- {
- operands[2] = GEN_INT (xxspltidp_value);
- return "xxspltidp %x0,%2";
- }
-
if (TARGET_P9_VECTOR
&& xxspltib_constant_p (vec, mode, &num_insns, &xxspltib_value))
{
@@ -24174,8 +24008,6 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
{ "string", 0, false, true },
{ "update", OPTION_MASK_NO_UPDATE, true , true },
{ "vsx", OPTION_MASK_VSX, false, true },
- { "xxspltiw", OPTION_MASK_XXSPLTIW, false, true },
- { "xxspltidp", OPTION_MASK_XXSPLTIDP, false, true },
#ifdef OPTION_MASK_64BIT
#if TARGET_AIX_OS
{ "aix64", OPTION_MASK_64BIT, false, false },
@@ -28001,7 +27833,7 @@ rs6000_emit_xxspltidp_v2df (rtx dst, long value)
inform (input_location,
"the result for the xxspltidp instruction "
"is undefined for subnormal input values");
- emit_insn( gen_xxspltidp_v2df_internal2 (dst, GEN_INT (value)));
+ emit_insn( gen_xxspltidp_v2df_inst (dst, GEN_INT (value)));
}
/* Implement TARGET_ASM_GENERATE_PIC_ADDR_DIFF_VEC. */
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 5569e0591e6..ca4a4d01f05 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -7564,17 +7564,17 @@
;;
;; LWZ LFS LXSSP LXSSPX STFS STXSSP
;; STXSSPX STW XXLXOR LI FMR XSCPSGNDP
-;; MR MT<x> MF<x> NOP XXSPLTIDP
+;; MR MT<x> MF<x> NOP
(define_insn "movsf_hardfloat"
[(set (match_operand:SF 0 "nonimmediate_operand"
"=!r, f, v, wa, m, wY,
Z, m, wa, !r, f, wa,
- !r, *c*l, !r, *h, wa")
+ !r, *c*l, !r, *h")
(match_operand:SF 1 "input_operand"
"m, m, wY, Z, f, v,
wa, r, j, j, f, wa,
- r, r, *h, 0, eF"))]
+ r, r, *h, 0"))]
"(register_operand (operands[0], SFmode)
|| register_operand (operands[1], SFmode))
&& TARGET_HARD_FLOAT
@@ -7596,20 +7596,15 @@
mr %0,%1
mt%0 %1
mf%1 %0
- nop
- #"
+ nop"
[(set_attr "type"
"load, fpload, fpload, fpload, fpstore, fpstore,
fpstore, store, veclogical, integer, fpsimple, fpsimple,
- *, mtjmpr, mfjmpr, *, vecperm")
+ *, mtjmpr, mfjmpr, *")
(set_attr "isa"
"*, *, p9v, p8v, *, p9v,
p8v, *, *, *, *, *,
- *, *, *, *, p10")
- (set_attr "prefixed"
- "*, *, *, *, *, *,
- *, *, *, *, *, *,
- *, *, *, *, yes")])
+ *, *, *, *")])
;; LWZ LFIWZX STW STFIWX MTVSRWZ MFVSRWZ
;; FMR MR MT%0 MF%1 NOP
@@ -7869,18 +7864,18 @@
;; STFD LFD FMR LXSD STXSD
;; LXSD STXSD XXLOR XXLXOR GPR<-0
-;; LWZ STW MR XXSPLTIDP
+;; LWZ STW MR
(define_insn "*mov<mode>_hardfloat32"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand"
"=m, d, d, <f64_p9>, wY,
<f64_av>, Z, <f64_vsx>, <f64_vsx>, !r,
- Y, r, !r, wa")
+ Y, r, !r")
(match_operand:FMOVE64 1 "input_operand"
"d, m, d, wY, <f64_p9>,
Z, <f64_av>, <f64_vsx>, <zero_fp>, <zero_fp>,
- r, Y, r, eF"))]
+ r, Y, r"))]
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
@@ -7897,25 +7892,20 @@
#
#
#
- #
#"
[(set_attr "type"
"fpstore, fpload, fpsimple, fpload, fpstore,
fpload, fpstore, veclogical, veclogical, two,
- store, load, two, vecperm")
+ store, load, two")
(set_attr "size" "64")
(set_attr "length"
"*, *, *, *, *,
*, *, *, *, 8,
- 8, 8, 8, *")
+ 8, 8, 8")
(set_attr "isa"
"*, *, *, p9v, p9v,
p7v, p7v, *, *, *,
- *, *, *, p10")
- (set_attr "prefixed"
- "*, *, *, *, *,
- *, *, *, *, *,
- *, *, *, yes")])
+ *, *, *")])
;; STW LWZ MR G-const H-const F-const
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 6620cdb7716..0dbdf753673 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -619,11 +619,3 @@ Generate (do not generate) MMA instructions.
mrelative-jumptables
Target Undocumented Var(rs6000_relative_jumptables) Init(1) Save
-
-mxxspltiw
-Target Undocumented Mask(XXSPLTIW) Var(rs6000_isa_flags)
-Generate (do not generate) the XXSPLTIW instruction.
-
-mxxspltidp
-Target Undocumented Mask(XXSPLTIDP) Var(rs6000_isa_flags)
-Generate (do not generate) the XXSPLTIDP instruction.
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 88574faf08a..bcb92be2f5c 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -369,8 +369,6 @@
UNSPEC_REPLACE_UN
UNSPEC_VDIVES
UNSPEC_VDIVEU
- UNSPEC_XXSPLTIW
- UNSPEC_XXSPLTIDP
])
(define_int_iterator XVCVBF16 [UNSPEC_VSX_XVCVSPBF16
@@ -1169,17 +1167,17 @@
;; VSX store VSX load VSX move VSX->GPR GPR->VSX LQ (GPR)
;; STQ (GPR) GPR load GPR store GPR move XXSPLTIB VSPLTISW
-;; VSX 0/-1 VMX const GPR const LVX (VMX) STVX (VMX) XXSPLTI*
+;; VSX 0/-1 VMX const GPR const LVX (VMX) STVX (VMX)
(define_insn "vsx_mov<mode>_64bit"
[(set (match_operand:VSX_M 0 "nonimmediate_operand"
"=ZwO, wa, wa, r, we, ?wQ,
?&r, ??r, ??Y, <??r>, wa, v,
- ?wa, v, <??r>, wZ, v, wa")
+ ?wa, v, <??r>, wZ, v")
(match_operand:VSX_M 1 "input_operand"
"wa, ZwO, wa, we, r, r,
wQ, Y, r, r, wE, jwM,
- ?jwM, W, <nW>, v, wZ, eWeF"))]
+ ?jwM, W, <nW>, v, wZ"))]
"TARGET_POWERPC64 && VECTOR_MEM_VSX_P (<MODE>mode)
&& (register_operand (operands[0], <MODE>mode)
@@ -1190,40 +1188,36 @@
[(set_attr "type"
"vecstore, vecload, vecsimple, mtvsr, mfvsr, load,
store, load, store, *, vecsimple, vecsimple,
- vecsimple, *, *, vecstore, vecload, vecperm")
+ vecsimple, *, *, vecstore, vecload")
(set_attr "num_insns"
"*, *, *, 2, *, 2,
2, 2, 2, 2, *, *,
- *, 5, 2, *, *, *")
+ *, 5, 2, *, *")
(set_attr "max_prefixed_insns"
"*, *, *, *, *, 2,
2, 2, 2, 2, *, *,
- *, *, *, *, *, *")
+ *, *, *, *, *")
(set_attr "length"
"*, *, *, 8, *, 8,
8, 8, 8, 8, *, *,
- *, 20, 8, *, *, *")
+ *, 20, 8, *, *")
(set_attr "isa"
"<VSisa>, <VSisa>, <VSisa>, *, *, *,
*, *, *, *, p9v, *,
- <VSisa>, *, *, *, *, p10")
- (set_attr "prefixed"
- "*, *, *, *, *, *,
- *, *, *, *, *, *,
- *, *, *, *, *, yes")])
+ <VSisa>, *, *, *, *")])
;; VSX store VSX load VSX move GPR load GPR store GPR move
-;; XXSPLTIB VSPLTISW VSX 0/-1 VMX const GPR const XXSPLTI*
+;; XXSPLTIB VSPLTISW VSX 0/-1 VMX const GPR const
;; LVX (VMX) STVX (VMX)
(define_insn "*vsx_mov<mode>_32bit"
[(set (match_operand:VSX_M 0 "nonimmediate_operand"
"=ZwO, wa, wa, ??r, ??Y, <??r>,
- wa, v, ?wa, v, <??r>, wa,
+ wa, v, ?wa, v, <??r>,
wZ, v")
(match_operand:VSX_M 1 "input_operand"
"wa, ZwO, wa, Y, r, r,
- wE, jwM, ?jwM, W, <nW>, eWeF,
+ wE, jwM, ?jwM, W, <nW>,
v, wZ"))]
"!TARGET_POWERPC64 && VECTOR_MEM_VSX_P (<MODE>mode)
@@ -1234,19 +1228,15 @@
}
[(set_attr "type"
"vecstore, vecload, vecsimple, load, store, *,
- vecsimple, vecsimple, vecsimple, *, *, vecperm,
+ vecsimple, vecsimple, vecsimple, *, *,
vecstore, vecload")
(set_attr "length"
"*, *, *, 16, 16, 16,
- *, *, *, 20, 16, *,
+ *, *, *, 20, 16,
*, *")
(set_attr "isa"
"<VSisa>, <VSisa>, <VSisa>, *, *, *,
- p9v, *, <VSisa>, *, *, p10,
- *, *")
- (set_attr "prefixed"
- "*, *, *, *, *, *,
- *, *, *, *, *, yes,
+ p9v, *, <VSisa>, *, *,
*, *")])
;; Explicit load/store expanders for the builtin functions
@@ -6226,103 +6216,3 @@
"TARGET_POWER10"
"vmulld %0,%1,%2"
[(set_attr "type" "veccomplex")])
-
-\f
-;; XXSPLTIW support.
-(define_mode_iterator XXSPLTIW [V8HI V4SI V4SF])
-
-(define_insn_and_split "*xxspltiw_<mode>_internal1"
- [(set (match_operand:XXSPLTIW 0 "vsx_register_operand" "=wa")
- (match_operand:XXSPLTIW 1 "xxspltiw_operand"))]
- "TARGET_XXSPLTIW"
- "#"
- "&& 1"
- [(set (match_operand:XXSPLTIW 0 "vsx_register_operand")
- (unspec:XXSPLTIW [(match_dup 2)] UNSPEC_XXSPLTIW))]
-{
- HOST_WIDE_INT value = 0;
-
- if (!xxspltiw_constant_p (operands[1], <MODE>mode, &value))
- gcc_unreachable ();
-
- operands[2] = GEN_INT (value);
-}
- [(set_attr "type" "vecsimple")
- (set_attr "prefixed" "yes")])
-
-(define_insn "*xxspltiw_<mode>_internal2"
- [(set (match_operand:XXSPLTIW 0 "vsx_register_operand" "=wa")
- (unspec:XXSPLTIW [(match_operand 1 "const_int_operand" "n")]
- UNSPEC_XXSPLTIW))]
- "TARGET_XXSPLTIW"
- "xxspltiw %x0,%1"
- [(set_attr "type" "vecsimple")
- (set_attr "prefixed" "yes")])
-
-;; Implement XXSPLTIW built-in functions as just loading up the appropriate
-;; constant vector. The normal optimizations will generate XXSPLTIW.
-(define_expand "xxspltiw_v4si"
- [(use (match_operand:V4SI 0 "register_operand"))
- (use (match_operand:SI 1 "s32bit_cint_operand"))]
- "TARGET_POWER10"
-{
- rtx op1 = operands[1];
- rtvec rv = gen_rtvec (4, op1, op1, op1, op1, op1);
- rtx cv = gen_rtx_CONST_VECTOR (V4SImode, rv);
- emit_move_insn (operands[0], cv);
- DONE;
-})
-
-(define_expand "xxspltiw_v4sf"
- [(use (match_operand:V4SF 0 "register_operand"))
- (use (match_operand:SF 1 "const_double_operand"))]
- "TARGET_POWER10"
-{
- rtx op1 = operands[1];
- rtvec rv = gen_rtvec (4, op1, op1, op1, op1, op1);
- rtx cv = gen_rtx_CONST_VECTOR (V4SFmode, rv);
- emit_move_insn (operands[0], cv);
- DONE;
-})
-
-;; XXSPLTIDP support.
-(define_mode_iterator XXSPLTIDP [SF DF V2DF])
-
-(define_insn_and_split "*xxspltidp_<mode>_internal1"
- [(set (match_operand:XXSPLTIDP 0 "vsx_register_operand" "=wa")
- (match_operand:XXSPLTIDP 1 "xxspltidp_operand"))]
- "TARGET_XXSPLTIDP"
- "#"
- "&& 1"
- [(set (match_operand:XXSPLTIDP 0 "vsx_register_operand")
- (unspec:XXSPLTIDP [(match_dup 2)] UNSPEC_XXSPLTIDP))]
-{
- HOST_WIDE_INT value = 0;
-
- if (!xxspltidp_constant_p (operands[1], <MODE>mode, &value))
- gcc_unreachable ();
-
- operands[2] = GEN_INT (value);
-}
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "yes")])
-
-(define_insn "xxspltidp_<mode>_internal2"
- [(set (match_operand:XXSPLTIDP 0 "vsx_register_operand" "=wa")
- (unspec:XXSPLTIDP [(match_operand 1 "const_int_operand" "n")]
- UNSPEC_XXSPLTIDP))]
- "TARGET_XXSPLTIDP"
- "xxspltidp %x0,%1"
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "yes")])
-
-;; XXSPLTIDP built-in function support.
-(define_expand "xxspltidp_v2df"
- [(use (match_operand:V2DF 0 "register_operand" ))
- (use (match_operand:SF 1 "const_double_operand"))]
- "TARGET_POWER10"
-{
- long value = rs6000_const_f32_to_i32 (operands[1]);
- rs6000_emit_xxspltidp_v2df (operands[0], value);
- DONE;
-})
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c b/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
index 06a8289d09b..e84ce77a21d 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { power10_hw } } } */
/* { dg-do link { target { ! power10_hw } } } */
/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-O2 -mdejagnu-cpu=power10 -save-temps" } */
+/* { dg-options "-mdejagnu-cpu=power10 -save-temps" } */
#include <altivec.h>
#define DEBUG 0
@@ -101,7 +101,7 @@ main (int argc, char *argv [])
printf(" vresult_d[%i] = %e, expected_vresult_d[%i] = %e\n",
i, vresult_d[i], i, expected_vresult_d[i]);
#else
- abort();
+ ;
#endif
}
@@ -160,6 +160,8 @@ main (int argc, char *argv [])
return 0;
}
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mxxspltiw\M} 2 } } */
/* { dg-final { scan-assembler-times {\mxxspltidp\M} 2 } } */
/* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 3 } } */
+
+
diff --git a/gcc/testsuite/gcc.target/powerpc/xxspltiw-v4sf.c b/gcc/testsuite/gcc.target/powerpc/xxspltiw-v4sf.c
deleted file mode 100644
index 031f6fc4e30..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/xxspltiw-v4sf.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -save-temps" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V4SF vector constants. */
-
-vector float
-v4sf_const_1 (void)
-{
- return (vector float) { 1.0f, 1.0f, 1.0f, 1.0f }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_nan (void)
-{
- return (vector float) { __builtin_nanf (""),
- __builtin_nanf (""),
- __builtin_nanf (""),
- __builtin_nanf ("") }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_inf (void)
-{
- return (vector float) { __builtin_inff (),
- __builtin_inff (),
- __builtin_inff (),
- __builtin_inff () }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_m0 (void)
-{
- return (vector float) { -0.0f, -0.0f, -0.0f, -0.0f }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_splats_1 (void)
-{
- return vec_splats (1.0f); /* XXSPLTIW. */
-}
-
-vector float
-v4sf_splats_nan (void)
-{
- return vec_splats (__builtin_nanf ("")); /* XXSPLTIW. */
-}
-
-vector float
-v4sf_splats_inf (void)
-{
- return vec_splats (__builtin_inff ()); /* XXSPLTIW. */
-}
-
-vector float
-v8hi_splats_m0 (void)
-{
- return vec_splats (-0.0f); /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 8 } } */
-/* { dg-final { scan-assembler-not {\mxxspltib\M} } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/xxspltiw-v4si.c b/gcc/testsuite/gcc.target/powerpc/xxspltiw-v4si.c
deleted file mode 100644
index dd027715ad5..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/xxspltiw-v4si.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -save-temps" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V4SI vector constants. We make sure
- the power9 support (XXSPLTIB/VEXTSB2W) is not done. */
-
-vector int
-v4si_const_1 (void)
-{
- return (vector int) { 1, 1, 1, 1 }; /* VSLTPISW. */
-}
-
-vector int
-v4si_const_126 (void)
-{
- return (vector int) { 126, 126, 126, 126 }; /* XXSPLTIW. */
-}
-
-vector int
-v4si_const_1023 (void)
-{
- return (vector int) { 1023, 1023, 1023, 1023 }; /* XXSPLTIW. */
-}
-
-vector int
-v4si_splats_1 (void)
-{
- return vec_splats (1); /* VSLTPISW. */
-}
-
-vector int
-v4si_splats_126 (void)
-{
- return vec_splats (126); /* XXSPLTIW. */
-}
-
-vector int
-v8hi_splats_1023 (void)
-{
- return vec_splats (1023); /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mvspltisw\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mxxspltib\M} } } */
-/* { dg-final { scan-assembler-not {\mvextsb2w\M} } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/xxspltiw-v8hi.c b/gcc/testsuite/gcc.target/powerpc/xxspltiw-v8hi.c
deleted file mode 100644
index 62aab135f98..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/xxspltiw-v8hi.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -save-temps" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V8HI vector constants. We make sure
- the power9 support (XXSPLTIB/VUPKLSB) is not done. */
-
-vector short
-v8hi_const_1 (void)
-{
- return (vector short) { 1, 1, 1, 1, 1, 1, 1, 1 }; /* VSLTPISH. */
-}
-
-vector short
-v8hi_const_126 (void)
-{
- return (vector short) { 126, 126, 126, 126,
- 126, 126, 126, 126 }; /* XXSPLTIW. */
-}
-
-vector short
-v8hi_const_1023 (void)
-{
- return (vector short) { 1023, 1023, 1023, 1023,
- 1023, 1023, 1023, 1023 }; /* XXSPLTIW. */
-}
-
-vector short
-v8hi_splats_1 (void)
-{
- return vec_splats ((short)1); /* VSLTPISH. */
-}
-
-vector short
-v8hi_splats_126 (void)
-{
- return vec_splats ((short)126); /* XXSPLTIW. */
-}
-
-vector short
-v8hi_splats_1023 (void)
-{
- return vec_splats ((short)1023); /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mvspltish\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mxxspltib\M} } } */
-/* { dg-final { scan-assembler-not {\mvupklsb\M} } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
^ permalink raw reply [flat|nested] 2+ messages in thread
* [gcc(refs/users/meissner/heads/work046)] Revert patches.
@ 2021-04-07 14:32 Michael Meissner
0 siblings, 0 replies; 2+ messages in thread
From: Michael Meissner @ 2021-04-07 14:32 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:8cce00903a54d7616503f458b281eec5b748afac
commit 8cce00903a54d7616503f458b281eec5b748afac
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Apr 7 10:31:16 2021 -0400
Revert patches.
gcc/
2021-04-07 Michael Meissner <meissner@linux.ibm.com>
Revert.
* config/rs6000/rs6000.c (have_compare_and_set_mask): Add IEEE
128-bit floating point types.
* config/rs6000/rs6000.md (FPMASK): New iterator.
(FPMASK2): New iterator.
(Fv mode attribute): Add KFmode and TFmode.
(mov<FPMASK:mode><FPMASK2:mode>cc_fpmask): Replace
mov<SFDF:mode><SFDF2:mode>cc_p9. Add IEEE 128-bit fp support.
(mov<FPMASK:mode><FPMASK2:mode>cc_invert_fpmask): Replace
mov<SFDF:mode><SFDF2:mode>cc_invert_p9. Add IEEE 128-bit fp
support.
(fpmask<mode>): Add IEEE 128-bit fp support. Enable generator to
build te RTL.
(xxsel<mode>): Add IEEE 128-bit fp support. Enable generator to
build te RTL.
gcc/testsuite/
2021-04-07 Michael Meissner <meissner@linux.ibm.com>
Revert.
* gcc.target/powerpc/float128-cmove.c: New test.
* gcc.target/powerpc/float128-minmax-3.c: New test.
gcc/
2021-04-07 Michael Meissner <meissner@linux.ibm.com>
Revert.
* config/rs6000/rs6000.c (rs6000_emit_minmax): Add support for ISA
3.1 IEEE 128-bit floating point xsmaxcqp and xsmincqp instructions.
* config/rs6000/rs60000.h (FLOAT128_MIN_MAX_FPMASK_P): New macro.
* config/rs6000/rs6000.md (s<minmax><mode>3): Add support for the
ISA 3.1 IEEE 128-bit minimum and maximum instructions.
gcc/testsuite/
2021-04-07 Michael Meissner <meissner@linux.ibm.com>
Revert.
* gcc.target/powerpc/float128-minmax-2.c: New test.
Diff:
---
gcc/config/rs6000/rs6000.c | 11 +-
gcc/config/rs6000/rs6000.h | 5 -
gcc/config/rs6000/rs6000.md | 197 +++++++--------------
.../gcc.target/powerpc/float128-minmax-2.c | 15 --
4 files changed, 67 insertions(+), 161 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index ad0d83f6d3f..35f5c332c41 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -15706,8 +15706,8 @@ rs6000_emit_vector_cond_expr (rtx dest, rtx op_true, rtx op_false,
return 1;
}
-/* Possibly emit the xsmaxc{dp,qp} and xsminc{dp,qp} instructions to emit a
- maximum or minimum with "C" semantics.
+/* Possibly emit the xsmaxcdp and xsmincdp instructions to emit a maximum or
+ minimum with "C" semantics.
Unless you use -ffast-math, you can't use these instructions to replace
conditions that implicitly reverse the condition because the comparison
@@ -15843,10 +15843,6 @@ have_compare_and_set_mask (machine_mode mode)
case E_DFmode:
return TARGET_P9_MINMAX;
- case E_KFmode:
- case E_TFmode:
- return FLOAT128_MIN_MAX_FPMASK_P (mode);
-
default:
break;
}
@@ -16115,8 +16111,7 @@ rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
/* VSX/altivec have direct min/max insns. */
if ((code == SMAX || code == SMIN)
&& (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)
- || (mode == SFmode && VECTOR_UNIT_VSX_P (DFmode))
- || FLOAT128_MIN_MAX_FPMASK_P (mode)))
+ || (mode == SFmode && VECTOR_UNIT_VSX_P (DFmode))))
{
emit_insn (gen_rtx_SET (dest, gen_rtx_fmt_ee (code, mode, op0, op1)));
return;
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index e3fb0798622..233a92baf3c 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -345,11 +345,6 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
|| ((MODE) == TDmode) \
|| (!TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (MODE)))
-/* Macro whether the float128 minimum, maximum, and set compare mask
- instructions are enabled. */
-#define FLOAT128_MIN_MAX_FPMASK_P(MODE) \
- (TARGET_POWER10 && TARGET_FLOAT128_HW && FLOAT128_IEEE_P (MODE))
-
/* Return true for floating point that does not use a vector register. */
#define SCALAR_FLOAT_MODE_NOT_VECTOR_P(MODE) \
(SCALAR_FLOAT_MODE_P (MODE) && !FLOAT128_VECTOR_P (MODE))
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index ca4a4d01f05..c8cdc42533c 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -575,19 +575,6 @@
; And again, for when we need two FP modes in a pattern.
(define_mode_iterator SFDF2 [SF DF])
-; Floating scalars that supports the set compare mask instruction.
-(define_mode_iterator FPMASK [SF
- DF
- (KF "FLOAT128_MIN_MAX_FPMASK_P (KFmode)")
- (TF "FLOAT128_MIN_MAX_FPMASK_P (TFmode)")])
-
-; And again, for patterns that need two (potentially) different floating point
-; scalars that support the set compare mask instruction.
-(define_mode_iterator FPMASK2 [SF
- DF
- (KF "FLOAT128_MIN_MAX_FPMASK_P (KFmode)")
- (TF "FLOAT128_MIN_MAX_FPMASK_P (TFmode)")])
-
; A generic s/d attribute, for sp/dp for example.
(define_mode_attr sd [(SF "s") (DF "d")
(V4SF "s") (V2DF "d")])
@@ -621,13 +608,8 @@
; SF/DF constraint for arithmetic on VSX registers using instructions added in
; ISA 2.06 (power7). This includes instructions that normally target DF mode,
; but are used on SFmode, since internally SFmode values are kept in the DFmode
-; format. Also include IEEE 128-bit instructions which are restricted to the
-; Altivec registers.
-(define_mode_attr Fv [(SF "wa")
- (DF "wa")
- (DI "wa")
- (KF "v")
- (TF "v")])
+; format.
+(define_mode_attr Fv [(SF "wa") (DF "wa") (DI "wa")])
; Which isa is needed for those float instructions?
(define_mode_attr Fisa [(SF "p8v") (DF "*") (DI "*")])
@@ -5212,17 +5194,6 @@
}
[(set_attr "type" "fp")])
-;; Min/max for ISA 3.1 IEEE 128-bit floating point
-(define_insn "s<minmax><mode>3"
- [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
- (fp_minmax:IEEE128
- (match_operand:IEEE128 1 "altivec_register_operand" "v")
- (match_operand:IEEE128 2 "altivec_register_operand" "v")))]
- "TARGET_POWER10"
- "xs<minmax>cqp %0,%1,%2"
- [(set_attr "type" "vecfloat")
- (set_attr "size" "128")])
-
;; The conditional move instructions allow us to perform max and min operations
;; even when we don't have the appropriate max/min instruction using the FSEL
;; instruction.
@@ -5334,10 +5305,10 @@
;; Floating point conditional move
(define_expand "mov<mode>cc"
- [(set (match_operand:FPMASK 0 "gpc_reg_operand")
- (if_then_else:FPMASK (match_operand 1 "comparison_operator")
- (match_operand:FPMASK 2 "gpc_reg_operand")
- (match_operand:FPMASK 3 "gpc_reg_operand")))]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand")
+ (if_then_else:SFDF (match_operand 1 "comparison_operator")
+ (match_operand:SFDF 2 "gpc_reg_operand")
+ (match_operand:SFDF 3 "gpc_reg_operand")))]
"TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT"
{
if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
@@ -5357,132 +5328,92 @@
"fsel %0,%1,%2,%3"
[(set_attr "type" "fp")])
-(define_insn_and_split "*mov<FPMASK:mode><FPMASK2:mode>cc_fpmask"
- [(set (match_operand:FPMASK 0 "vsx_register_operand" "=<FPMASK:Fv>")
- (if_then_else:FPMASK
+(define_insn_and_split "*mov<SFDF:mode><SFDF2:mode>cc_p9"
+ [(set (match_operand:SFDF 0 "vsx_register_operand" "=&<SFDF:Fv>,<SFDF:Fv>")
+ (if_then_else:SFDF
(match_operator:CCFP 1 "fpmask_comparison_operator"
- [(match_operand:FPMASK2 2 "vsx_register_operand" "<FPMASK2:Fv>")
- (match_operand:FPMASK2 3 "vsx_register_operand" "<FPMASK2:Fv>")])
- (match_operand:FPMASK 4 "vsx_register_operand" "<FPMASK:Fv>")
- (match_operand:FPMASK 5 "vsx_register_operand" "<FPMASK:Fv>")))
- (clobber (match_scratch:V2DI 6 "=&<FPMASK2:Fv>"))]
+ [(match_operand:SFDF2 2 "vsx_register_operand" "<SFDF2:Fv>,<SFDF2:Fv>")
+ (match_operand:SFDF2 3 "vsx_register_operand" "<SFDF2:Fv>,<SFDF2:Fv>")])
+ (match_operand:SFDF 4 "vsx_register_operand" "<SFDF:Fv>,<SFDF:Fv>")
+ (match_operand:SFDF 5 "vsx_register_operand" "<SFDF:Fv>,<SFDF:Fv>")))
+ (clobber (match_scratch:V2DI 6 "=0,&wa"))]
"TARGET_P9_MINMAX"
"#"
"&& 1"
- [(pc)]
+ [(set (match_dup 6)
+ (if_then_else:V2DI (match_dup 1)
+ (match_dup 7)
+ (match_dup 8)))
+ (set (match_dup 0)
+ (if_then_else:SFDF (ne (match_dup 6)
+ (match_dup 8))
+ (match_dup 4)
+ (match_dup 5)))]
{
- rtx dest = operands[0];
- rtx cmp = operands[1];
- rtx cmp_op1 = operands[2];
- rtx cmp_op2 = operands[3];
- rtx move_t = operands[4];
- rtx move_f = operands[5];
- rtx mask_reg = operands[6];
- rtx mask_m1 = CONSTM1_RTX (V2DImode);
- rtx mask_0 = CONST0_RTX (V2DImode);
- machine_mode move_mode = <FPMASK:MODE>mode;
- machine_mode compare_mode = <FPMASK2:MODE>mode;
-
- if (GET_CODE (mask_reg) == SCRATCH)
- mask_reg = gen_reg_rtx (V2DImode);
-
- /* Emit the compare and set mask instruction. */
- emit_insn (gen_fpmask<FPMASK2:mode> (mask_reg, cmp, cmp_op1, cmp_op2,
- mask_m1, mask_0));
-
- /* If we have a 64-bit comparison, but an 128-bit move, we need to extend the
- mask. Because we are using the splat builtin to extend the V2DImode, we
- need to use element 1 on little endian systems. */
- if (!FLOAT128_IEEE_P (compare_mode) && FLOAT128_IEEE_P (move_mode))
- {
- rtx element = WORDS_BIG_ENDIAN ? const0_rtx : const1_rtx;
- emit_insn (gen_vsx_xxspltd_v2di (mask_reg, mask_reg, element));
- }
+ if (GET_CODE (operands[6]) == SCRATCH)
+ operands[6] = gen_reg_rtx (V2DImode);
- /* Now emit the XXSEL insn. */
- emit_insn (gen_xxsel<FPMASK:mode> (dest, mask_reg, mask_0, move_t, move_f));
- DONE;
+ operands[7] = CONSTM1_RTX (V2DImode);
+ operands[8] = CONST0_RTX (V2DImode);
}
- ;; length is 12 in case we need to add XXPERMDI
- [(set_attr "length" "12")
+ [(set_attr "length" "8")
(set_attr "type" "vecperm")])
;; Handle inverting the fpmask comparisons.
-(define_insn_and_split "*mov<FPMASK:mode><FPMASK2:mode>cc_invert_fpmask"
- [(set (match_operand:FPMASK 0 "vsx_register_operand" "=<FPMASK:Fv>")
- (if_then_else:FPMASK
+(define_insn_and_split "*mov<SFDF:mode><SFDF2:mode>cc_invert_p9"
+ [(set (match_operand:SFDF 0 "vsx_register_operand" "=&<SFDF:Fv>,<SFDF:Fv>")
+ (if_then_else:SFDF
(match_operator:CCFP 1 "invert_fpmask_comparison_operator"
- [(match_operand:FPMASK2 2 "vsx_register_operand" "<FPMASK2:Fv>")
- (match_operand:FPMASK2 3 "vsx_register_operand" "<FPMASK2:Fv>")])
- (match_operand:FPMASK 4 "vsx_register_operand" "<FPMASK:Fv>")
- (match_operand:FPMASK 5 "vsx_register_operand" "<FPMASK:Fv>")))
- (clobber (match_scratch:V2DI 6 "=&<FPMASK2:Fv>"))]
+ [(match_operand:SFDF2 2 "vsx_register_operand" "<SFDF2:Fv>,<SFDF2:Fv>")
+ (match_operand:SFDF2 3 "vsx_register_operand" "<SFDF2:Fv>,<SFDF2:Fv>")])
+ (match_operand:SFDF 4 "vsx_register_operand" "<SFDF:Fv>,<SFDF:Fv>")
+ (match_operand:SFDF 5 "vsx_register_operand" "<SFDF:Fv>,<SFDF:Fv>")))
+ (clobber (match_scratch:V2DI 6 "=0,&wa"))]
"TARGET_P9_MINMAX"
"#"
"&& 1"
- [(pc)]
+ [(set (match_dup 6)
+ (if_then_else:V2DI (match_dup 9)
+ (match_dup 7)
+ (match_dup 8)))
+ (set (match_dup 0)
+ (if_then_else:SFDF (ne (match_dup 6)
+ (match_dup 8))
+ (match_dup 5)
+ (match_dup 4)))]
{
- rtx dest = operands[0];
- rtx old_cmp = operands[1];
- rtx cmp_op1 = operands[2];
- rtx cmp_op2 = operands[3];
- enum rtx_code cond = reverse_condition_maybe_unordered (GET_CODE (old_cmp));
- rtx cmp_rev = gen_rtx_fmt_ee (cond, CCFPmode, cmp_op1, cmp_op2);
- rtx move_f = operands[4];
- rtx move_t = operands[5];
- rtx mask_reg = operands[6];
- rtx mask_m1 = CONSTM1_RTX (V2DImode);
- rtx mask_0 = CONST0_RTX (V2DImode);
- machine_mode move_mode = <FPMASK:MODE>mode;
- machine_mode compare_mode = <FPMASK2:MODE>mode;
-
- if (GET_CODE (mask_reg) == SCRATCH)
- mask_reg = gen_reg_rtx (V2DImode);
+ rtx op1 = operands[1];
+ enum rtx_code cond = reverse_condition_maybe_unordered (GET_CODE (op1));
- /* Emit the compare and set mask instruction. */
- emit_insn (gen_fpmask<FPMASK2:mode> (mask_reg, cmp_rev, cmp_op1, cmp_op2,
- mask_m1, mask_0));
+ if (GET_CODE (operands[6]) == SCRATCH)
+ operands[6] = gen_reg_rtx (V2DImode);
- /* If we have a 64-bit comparison, but an 128-bit move, we need to extend the
- mask. Because we are using the splat builtin to extend the V2DImode, we
- need to use element 1 on little endian systems. */
- if (!FLOAT128_IEEE_P (compare_mode) && FLOAT128_IEEE_P (move_mode))
- {
- rtx element = WORDS_BIG_ENDIAN ? const0_rtx : const1_rtx;
- emit_insn (gen_vsx_xxspltd_v2di (mask_reg, mask_reg, element));
- }
+ operands[7] = CONSTM1_RTX (V2DImode);
+ operands[8] = CONST0_RTX (V2DImode);
- /* Now emit the XXSEL insn. */
- emit_insn (gen_xxsel<FPMASK:mode> (dest, mask_reg, mask_0, move_t, move_f));
- DONE;
+ operands[9] = gen_rtx_fmt_ee (cond, CCFPmode, operands[2], operands[3]);
}
- ;; length is 12 in case we need to add XXPERMDI
- [(set_attr "length" "12")
+ [(set_attr "length" "8")
(set_attr "type" "vecperm")])
-(define_insn "fpmask<mode>"
- [(set (match_operand:V2DI 0 "vsx_register_operand" "=<Fv>")
+(define_insn "*fpmask<mode>"
+ [(set (match_operand:V2DI 0 "vsx_register_operand" "=wa")
(if_then_else:V2DI
(match_operator:CCFP 1 "fpmask_comparison_operator"
- [(match_operand:FPMASK 2 "vsx_register_operand" "<Fv>")
- (match_operand:FPMASK 3 "vsx_register_operand" "<Fv>")])
+ [(match_operand:SFDF 2 "vsx_register_operand" "<Fv>")
+ (match_operand:SFDF 3 "vsx_register_operand" "<Fv>")])
(match_operand:V2DI 4 "all_ones_constant" "")
(match_operand:V2DI 5 "zero_constant" "")))]
"TARGET_P9_MINMAX"
-{
- return (FLOAT128_IEEE_P (<MODE>mode)
- ? "xscmp%V1qp %0,%2,%3"
- : "xscmp%V1dp %x0,%x2,%x3");
-}
+ "xscmp%V1dp %x0,%x2,%x3"
[(set_attr "type" "fpcompare")])
-(define_insn "xxsel<mode>"
- [(set (match_operand:FPMASK 0 "vsx_register_operand" "=wa")
- (if_then_else:FPMASK
- (ne (match_operand:V2DI 1 "vsx_register_operand" "wa")
- (match_operand:V2DI 2 "zero_constant" ""))
- (match_operand:FPMASK 3 "vsx_register_operand" "wa")
- (match_operand:FPMASK 4 "vsx_register_operand" "wa")))]
+(define_insn "*xxsel<mode>"
+ [(set (match_operand:SFDF 0 "vsx_register_operand" "=<Fv>")
+ (if_then_else:SFDF (ne (match_operand:V2DI 1 "vsx_register_operand" "wa")
+ (match_operand:V2DI 2 "zero_constant" ""))
+ (match_operand:SFDF 3 "vsx_register_operand" "<Fv>")
+ (match_operand:SFDF 4 "vsx_register_operand" "<Fv>")))]
"TARGET_P9_MINMAX"
"xxsel %x0,%x4,%x3,%x1"
[(set_attr "type" "vecmove")])
diff --git a/gcc/testsuite/gcc.target/powerpc/float128-minmax-2.c b/gcc/testsuite/gcc.target/powerpc/float128-minmax-2.c
deleted file mode 100644
index c71ba08c9f8..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/float128-minmax-2.c
+++ /dev/null
@@ -1,15 +0,0 @@
-/* { dg-require-effective-target ppc_float128_hw } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -ffast-math" } */
-
-#ifndef TYPE
-#define TYPE _Float128
-#endif
-
-/* Test that the fminf128/fmaxf128 functions generate if/then/else and not a
- call. */
-TYPE f128_min (TYPE a, TYPE b) { return __builtin_fminf128 (a, b); }
-TYPE f128_max (TYPE a, TYPE b) { return __builtin_fmaxf128 (a, b); }
-
-/* { dg-final { scan-assembler {\mxsmaxcqp\M} } } */
-/* { dg-final { scan-assembler {\mxsmincqp\M} } } */
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