public inbox for gcc-cvs@sourceware.org
help / color / mirror / Atom feed
From: Michael Meissner <meissner@gcc.gnu.org>
To: gcc-cvs@gcc.gnu.org
Subject: [gcc(refs/users/meissner/heads/work046)] Revert patch.
Date: Wed, 7 Apr 2021 20:17:02 +0000 (GMT) [thread overview]
Message-ID: <20210407201702.EAF45385801D@sourceware.org> (raw)
https://gcc.gnu.org/g:ee2b70ed35187ff214a82cd7ab573a5a3523ac54
commit ee2b70ed35187ff214a82cd7ab573a5a3523ac54
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Apr 7 16:16:35 2021 -0400
Revert patch.
gcc/
2021-04-07 Michael Meissner <meissner@linux.ibm.com>
Revert patch.
* config/rs6000/altivec.md (UNSPEC_XXSPLTID): Move to vsx.md and
rename to UNSPEC_XXSPLTID.
(xxspltidp_v2df): Move to vsx.md and re-implement.
(xxspltidp_v2df_inst): Move to vsx.md and re-implement.
* config/rs6000/constraints.md (eF): New constraint.
* config/rs6000/predicates.md (easy_fp_constant): If we load the
scalar constant with XXSPLTIDP, return true.
(xxspltidp_operand): New predicate.
(easy_vector_constant): If we can generate XXSPLTIDP, mark the
vector constant as easy.
* config/rs6000/rs6000-cpus.def (OTHER_POWER10_MASKS): Add
-mxxspltidp support.
(POWERPC_MASKS): Add -mxxspltidp support.
* config/rs6000/rs6000-protos.h (xxspltidp_constant_p): New
declaration.
* config/rs6000/rs6000.c (rs6000_option_override_internal): Add
-mxxspltidp support.
(xxspltidp_constant_p): New function.
(output_vec_const_move): Add support for XXSPLTIDP.
(rs6000_opt_masks): Add -mxxspltidp support.
(rs6000_emit_xxspltidp_v2df): Change function to implement the
XXSPLTIDP instruction.
* config/rs6000/rs6000.md (movsf_hardfloat): Add XXSPLTIDP
support.
(mov<mode>_hardfloat32, FMOVE64 iterator): Add XXSPLTIDP support.
(mov<mode>_hardfloat64, FMOVE64 iterator): Add XXSPLTIDP support.
* config/rs6000/rs6000.opt (-mxxspltidp): New switch.
* config/rs6000/vsx.md (UNSPEC_XXSPLTIDP): Move here from
altivec.md. Rename it to UNSPEC_XXSPLTIDP to match the
instruction.
(vsx_mov<mode>_64bit): Add XXSPLTIDP support.
(vsx_mov<mode>_32bit): Add XXSPLTIDP support.
(XXSPLTIDP): New mode iterator.
(xxspltidp_<mode>_internal1): New define_insn_and_split.
(xxspltidp_<mode>_internal2): New define_insn.
(xxspltidp_v2df): Move to vsx.md from altivec.md. Re-implement to
use the new constant format.
Diff:
---
gcc/config/rs6000/altivec.md | 21 +++++++++++
gcc/config/rs6000/constraints.md | 5 ---
gcc/config/rs6000/predicates.md | 21 -----------
gcc/config/rs6000/rs6000-cpus.def | 2 -
gcc/config/rs6000/rs6000-protos.h | 1 -
gcc/config/rs6000/rs6000.c | 77 +--------------------------------------
gcc/config/rs6000/rs6000.md | 34 ++++++-----------
gcc/config/rs6000/rs6000.opt | 5 ---
gcc/config/rs6000/vsx.md | 47 +-----------------------
9 files changed, 36 insertions(+), 177 deletions(-)
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index ad6ead04cfa..708296cb14d 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -176,6 +176,7 @@
UNSPEC_VSTRIL
UNSPEC_SLDB
UNSPEC_SRDB
+ UNSPEC_XXSPLTID
UNSPEC_XXSPLTI32DX
UNSPEC_XXBLEND
UNSPEC_XXPERMX
@@ -818,6 +819,26 @@
"vs<SLDB_lr>dbi %0,%1,%2,%3"
[(set_attr "type" "vecsimple")])
+(define_expand "xxspltidp_v2df"
+ [(set (match_operand:V2DF 0 "register_operand" )
+ (unspec:V2DF [(match_operand:SF 1 "const_double_operand")]
+ UNSPEC_XXSPLTID))]
+ "TARGET_POWER10"
+{
+ long value = rs6000_const_f32_to_i32 (operands[1]);
+ rs6000_emit_xxspltidp_v2df (operands[0], value);
+ DONE;
+})
+
+(define_insn "xxspltidp_v2df_inst"
+ [(set (match_operand:V2DF 0 "register_operand" "=wa")
+ (unspec:V2DF [(match_operand:SI 1 "c32bit_cint_operand" "n")]
+ UNSPEC_XXSPLTID))]
+ "TARGET_POWER10"
+ "xxspltidp %x0,%1"
+ [(set_attr "type" "vecsimple")
+ (set_attr "prefixed" "yes")])
+
(define_expand "xxsplti32dx_v4si"
[(set (match_operand:V4SI 0 "register_operand" "=wa")
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0")
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index 70b1eb01770..b3e36fbcfdf 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -208,11 +208,6 @@
(and (match_code "const_int")
(match_test "((- (unsigned HOST_WIDE_INT) ival) + 0x8000) < 0x10000")))
-;; SF/DF/V2DF scalar or vector constant that can be loaded with XXSPLTIDP
-(define_constraint "eF"
- "A vector constant that can be loaded with the XXSPLTIDP instruction."
- (match_operand 0 "xxspltidp_operand"))
-
;; 34-bit signed integer constant
(define_constraint "eI"
"A signed 34-bit integer constant if prefixed instructions are supported."
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 48d9c5509a2..dc23f62a3af 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -601,11 +601,6 @@
if (TARGET_VSX && op == CONST0_RTX (mode))
return 1;
- /* If we have the ISA 3.1 XXSPLTIDP instruction, see if the constant can
- be loaded with that instruction. */
- if (xxspltidp_operand (op, mode))
- return 1;
-
/* Otherwise consider floating point constants hard, so that the
constant gets pushed to memory during the early RTL phases. This
has the advantage that double precision constants that can be
@@ -664,19 +659,6 @@
return !EASY_VECTOR_15 (value);
})
-;; Return 1 if operand is a SF/DF CONST_DOUBLE or V2DF CONST_VECTOR that can be
-;; loaded via the ISA 3.1 XXSPLTIDP instruction. Do not return true if the
-;; value is 0.0, since that is easy to generate without using XXSPLTIDP.
-(define_predicate "xxspltidp_operand"
- (match_code "const_double,const_vector,vec_duplicate")
-{
- if (op == CONST0_RTX (mode))
- return false;
-
- HOST_WIDE_INT value = 0;
- return xxspltidp_constant_p (op, mode, &value);
-})
-
;; Return 1 if the operand is a CONST_VECTOR and can be loaded into a
;; vector register without using memory.
(define_predicate "easy_vector_constant"
@@ -693,9 +675,6 @@
if (xxspltiw_operand (op, mode))
return true;
- if (xxspltidp_operand (op, mode))
- return true;
-
if (TARGET_P9_VECTOR
&& xxspltib_constant_p (op, mode, &num_insns, &value))
return true;
diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def
index cf4044831f7..f7743374f26 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -79,7 +79,6 @@
| OPTION_MASK_PCREL \
| OPTION_MASK_PCREL_OPT \
| OPTION_MASK_PREFIXED \
- | OPTION_MASK_XXSPLTIDP \
| OPTION_MASK_XXSPLTIW)
#define ISA_3_1_MASKS_SERVER (ISA_3_0_MASKS_SERVER \
@@ -163,7 +162,6 @@
| OPTION_MASK_SOFT_FLOAT \
| OPTION_MASK_STRICT_ALIGN_OPTIONAL \
| OPTION_MASK_VSX \
- | OPTION_MASK_XXSPLTIDP \
| OPTION_MASK_XXSPLTIW)
#endif
diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h
index 0fe1c176236..eff72af8814 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -33,7 +33,6 @@ extern void init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, int, int, int,
extern bool easy_altivec_constant (rtx, machine_mode);
extern bool xxspltib_constant_p (rtx, machine_mode, int *, int *);
extern bool xxspltiw_constant_p (rtx, machine_mode, HOST_WIDE_INT *);
-extern bool xxspltidp_constant_p (rtx, machine_mode, HOST_WIDE_INT *);
extern int vspltis_shifted (rtx);
extern HOST_WIDE_INT const_vector_elt_as_int (rtx, unsigned int);
extern bool macho_lo_sum_memory_operand (rtx, machine_mode);
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index f023747a578..54c338d73a5 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -4480,10 +4480,6 @@ rs6000_option_override_internal (bool global_init_p)
&& (rs6000_isa_flags_explicit & OPTION_MASK_XXSPLTIW) == 0)
rs6000_isa_flags |= OPTION_MASK_XXSPLTIW;
- if (TARGET_POWER10 && TARGET_VSX
- && (rs6000_isa_flags_explicit & OPTION_MASK_XXSPLTIDP) == 0)
- rs6000_isa_flags |= OPTION_MASK_XXSPLTIDP;
-
if (!TARGET_PCREL && TARGET_PCREL_OPT)
rs6000_isa_flags &= ~OPTION_MASK_PCREL_OPT;
@@ -6541,69 +6537,6 @@ xxspltiw_constant_p (rtx op,
return true;
}
-/* Return true if OP is of the given MODE and can be synthesized with ISA 3.1
- XXSPLTIDP instruction.
-
- Return the constant that is being split via CONSTANT_PTR to use in the
- XXSPLTIDP instruction. */
-
-bool
-xxspltidp_constant_p (rtx op,
- machine_mode mode,
- HOST_WIDE_INT *constant_ptr)
-{
- *constant_ptr = 0;
-
- rtx element = op;
- if (mode == V2DFmode)
- {
- /* Handle VEC_DUPLICATE and CONST_VECTOR. */
- if (GET_CODE (op) == VEC_DUPLICATE)
- element = XEXP (op, 0);
-
- else if (GET_CODE (op) == CONST_VECTOR)
- {
- element = CONST_VECTOR_ELT (op, 0);
- if (!rtx_equal_p (element, CONST_VECTOR_ELT (op, 1)))
- return false;
- }
-
- else
- return false;
-
- mode = DFmode;
- }
-
- if (mode != SFmode && mode != DFmode)
- return false;
-
- if (GET_MODE (element) != mode)
- return false;
-
- if (!CONST_DOUBLE_P (element))
- return false;
-
- /* Don't return true for 0.0 since that is easy to create without
- XXSPLTIDP. */
- if (element == CONST0_RTX (mode))
- return false;
-
- /* If the value doesn't fit in a SFmode, exactly, we can't use XXSPLTIDP. */
- const struct real_value *rv = CONST_DOUBLE_REAL_VALUE (element);
- if (!exact_real_truncate (SFmode, rv))
- return 0;
-
- long value;
- REAL_VALUE_TO_TARGET_SINGLE (*rv, value);
-
- /* Test for SFmode denormal (exponent is 0, mantissa field is non-zero). */
- if (((value & 0x7F800000) == 0) && ((value & 0x7FFFFF) != 0))
- return false;
-
- *constant_ptr = value;
- return true;
-}
-
const char *
output_vec_const_move (rtx *operands)
{
@@ -6670,13 +6603,6 @@ output_vec_const_move (rtx *operands)
return "xxspltiw %x0,%2";
}
- HOST_WIDE_INT xxspltidp_value = 0;
- if (xxspltidp_constant_p (vec, mode, &xxspltidp_value))
- {
- operands[2] = GEN_INT (xxspltidp_value);
- return "xxspltidp %x0,%2";
- }
-
if (TARGET_P9_VECTOR
&& xxspltib_constant_p (vec, mode, &num_insns, &xxspltib_value))
{
@@ -24175,7 +24101,6 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
{ "update", OPTION_MASK_NO_UPDATE, true , true },
{ "vsx", OPTION_MASK_VSX, false, true },
{ "xxspltiw", OPTION_MASK_XXSPLTIW, false, true },
- { "xxspltidp", OPTION_MASK_XXSPLTIDP, false, true },
#ifdef OPTION_MASK_64BIT
#if TARGET_AIX_OS
{ "aix64", OPTION_MASK_64BIT, false, false },
@@ -28001,7 +27926,7 @@ rs6000_emit_xxspltidp_v2df (rtx dst, long value)
inform (input_location,
"the result for the xxspltidp instruction "
"is undefined for subnormal input values");
- emit_insn( gen_xxspltidp_v2df_internal2 (dst, GEN_INT (value)));
+ emit_insn( gen_xxspltidp_v2df_inst (dst, GEN_INT (value)));
}
/* Implement TARGET_ASM_GENERATE_PIC_ADDR_DIFF_VEC. */
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 5569e0591e6..ca4a4d01f05 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -7564,17 +7564,17 @@
;;
;; LWZ LFS LXSSP LXSSPX STFS STXSSP
;; STXSSPX STW XXLXOR LI FMR XSCPSGNDP
-;; MR MT<x> MF<x> NOP XXSPLTIDP
+;; MR MT<x> MF<x> NOP
(define_insn "movsf_hardfloat"
[(set (match_operand:SF 0 "nonimmediate_operand"
"=!r, f, v, wa, m, wY,
Z, m, wa, !r, f, wa,
- !r, *c*l, !r, *h, wa")
+ !r, *c*l, !r, *h")
(match_operand:SF 1 "input_operand"
"m, m, wY, Z, f, v,
wa, r, j, j, f, wa,
- r, r, *h, 0, eF"))]
+ r, r, *h, 0"))]
"(register_operand (operands[0], SFmode)
|| register_operand (operands[1], SFmode))
&& TARGET_HARD_FLOAT
@@ -7596,20 +7596,15 @@
mr %0,%1
mt%0 %1
mf%1 %0
- nop
- #"
+ nop"
[(set_attr "type"
"load, fpload, fpload, fpload, fpstore, fpstore,
fpstore, store, veclogical, integer, fpsimple, fpsimple,
- *, mtjmpr, mfjmpr, *, vecperm")
+ *, mtjmpr, mfjmpr, *")
(set_attr "isa"
"*, *, p9v, p8v, *, p9v,
p8v, *, *, *, *, *,
- *, *, *, *, p10")
- (set_attr "prefixed"
- "*, *, *, *, *, *,
- *, *, *, *, *, *,
- *, *, *, *, yes")])
+ *, *, *, *")])
;; LWZ LFIWZX STW STFIWX MTVSRWZ MFVSRWZ
;; FMR MR MT%0 MF%1 NOP
@@ -7869,18 +7864,18 @@
;; STFD LFD FMR LXSD STXSD
;; LXSD STXSD XXLOR XXLXOR GPR<-0
-;; LWZ STW MR XXSPLTIDP
+;; LWZ STW MR
(define_insn "*mov<mode>_hardfloat32"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand"
"=m, d, d, <f64_p9>, wY,
<f64_av>, Z, <f64_vsx>, <f64_vsx>, !r,
- Y, r, !r, wa")
+ Y, r, !r")
(match_operand:FMOVE64 1 "input_operand"
"d, m, d, wY, <f64_p9>,
Z, <f64_av>, <f64_vsx>, <zero_fp>, <zero_fp>,
- r, Y, r, eF"))]
+ r, Y, r"))]
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
@@ -7897,25 +7892,20 @@
#
#
#
- #
#"
[(set_attr "type"
"fpstore, fpload, fpsimple, fpload, fpstore,
fpload, fpstore, veclogical, veclogical, two,
- store, load, two, vecperm")
+ store, load, two")
(set_attr "size" "64")
(set_attr "length"
"*, *, *, *, *,
*, *, *, *, 8,
- 8, 8, 8, *")
+ 8, 8, 8")
(set_attr "isa"
"*, *, *, p9v, p9v,
p7v, p7v, *, *, *,
- *, *, *, p10")
- (set_attr "prefixed"
- "*, *, *, *, *,
- *, *, *, *, *,
- *, *, *, yes")])
+ *, *, *")])
;; STW LWZ MR G-const H-const F-const
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 6620cdb7716..06e7cdbbced 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -622,8 +622,3 @@ Target Undocumented Var(rs6000_relative_jumptables) Init(1) Save
mxxspltiw
Target Undocumented Mask(XXSPLTIW) Var(rs6000_isa_flags)
-Generate (do not generate) the XXSPLTIW instruction.
-
-mxxspltidp
-Target Undocumented Mask(XXSPLTIDP) Var(rs6000_isa_flags)
-Generate (do not generate) the XXSPLTIDP instruction.
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 270996c5e09..e5c5e157d1d 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -370,7 +370,6 @@
UNSPEC_VDIVES
UNSPEC_VDIVEU
UNSPEC_XXSPLTIW
- UNSPEC_XXSPLTIDP
])
(define_int_iterator XVCVBF16 [UNSPEC_VSX_XVCVSPBF16
@@ -1179,7 +1178,7 @@
(match_operand:VSX_M 1 "input_operand"
"wa, ZwO, wa, we, r, r,
wQ, Y, r, r, wE, jwM,
- ?jwM, W, <nW>, v, wZ, eWeF"))]
+ ?jwM, W, <nW>, v, wZ, eW"))]
"TARGET_POWERPC64 && VECTOR_MEM_VSX_P (<MODE>mode)
&& (register_operand (operands[0], <MODE>mode)
@@ -1223,7 +1222,7 @@
(match_operand:VSX_M 1 "input_operand"
"wa, ZwO, wa, Y, r, r,
- wE, jwM, ?jwM, W, <nW>, eWeF,
+ wE, jwM, ?jwM, W, <nW>, eW,
v, wZ"))]
"!TARGET_POWERPC64 && VECTOR_MEM_VSX_P (<MODE>mode)
@@ -6284,45 +6283,3 @@
emit_move_insn (operands[0], cv);
DONE;
})
-
-;; XXSPLTIDP support.
-(define_mode_iterator XXSPLTIDP [SF DF V2DF])
-
-(define_insn_and_split "*xxspltidp_<mode>_internal1"
- [(set (match_operand:XXSPLTIDP 0 "vsx_register_operand" "=wa")
- (match_operand:XXSPLTIDP 1 "xxspltidp_operand"))]
- "TARGET_XXSPLTIDP"
- "#"
- "&& 1"
- [(set (match_operand:XXSPLTIDP 0 "vsx_register_operand")
- (unspec:XXSPLTIDP [(match_dup 2)] UNSPEC_XXSPLTIDP))]
-{
- HOST_WIDE_INT value = 0;
-
- if (!xxspltidp_constant_p (operands[1], <MODE>mode, &value))
- gcc_unreachable ();
-
- operands[2] = GEN_INT (value);
-}
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "yes")])
-
-(define_insn "xxspltidp_<mode>_internal2"
- [(set (match_operand:XXSPLTIDP 0 "vsx_register_operand" "=wa")
- (unspec:XXSPLTIDP [(match_operand 1 "const_int_operand" "n")]
- UNSPEC_XXSPLTIDP))]
- "TARGET_XXSPLTIDP"
- "xxspltidp %x0,%1"
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "yes")])
-
-;; XXSPLTIDP built-in function support.
-(define_expand "xxspltidp_v2df"
- [(use (match_operand:V2DF 0 "register_operand" ))
- (use (match_operand:SF 1 "const_double_operand"))]
- "TARGET_POWER10"
-{
- long value = rs6000_const_f32_to_i32 (operands[1]);
- rs6000_emit_xxspltidp_v2df (operands[0], value);
- DONE;
-})
next reply other threads:[~2021-04-07 20:17 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-07 20:17 Michael Meissner [this message]
-- strict thread matches above, loose matches on Subject: below --
2021-04-12 17:07 Michael Meissner
2021-04-10 3:02 Michael Meissner
2021-04-08 19:44 Michael Meissner
2021-04-07 21:38 Michael Meissner
2021-04-07 19:17 Michael Meissner
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210407201702.EAF45385801D@sourceware.org \
--to=meissner@gcc.gnu.org \
--cc=gcc-cvs@gcc.gnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).