From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id B3499385E001; Thu, 8 Apr 2021 19:44:32 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org B3499385E001 Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work046)] Revert patch. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work046 X-Git-Oldrev: 9ff5a86e339b99139d72284a5f2ab01dafd3f479 X-Git-Newrev: befbd49b5bed1f3ed52cb2555e7cb2b10c56b603 Message-Id: <20210408194432.B3499385E001@sourceware.org> Date: Thu, 8 Apr 2021 19:44:32 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 08 Apr 2021 19:44:32 -0000 https://gcc.gnu.org/g:befbd49b5bed1f3ed52cb2555e7cb2b10c56b603 commit befbd49b5bed1f3ed52cb2555e7cb2b10c56b603 Author: Michael Meissner Date: Thu Apr 8 15:43:47 2021 -0400 Revert patch. gcc/ 2021-04-08 Michael Meissner Revert patch. * config/rs6000/contraints.md (eD): New constraint. * config/rs6000/predicates.md (easy_fp_constant): If we can load the constant with a pair of XXSPLTI32DX instructions, it is easy. (xxsplti32dx_operand): New predicate. (easy_vector_constant): If we can load the constant with a pair of XXSPLTI32DX instructions, it is easy. * config/rs6000/rs6000-cpus.def (OTHER_POWER10_MASKS): Add -mxxsplti32dx. (POWERPC_MASKS): Add -mxxsplti32dx. * config/rs6000/rs6000-protos.h (xxsplti32dx_constant_p): New declaration. * config/rs6000/rs6000.c (rs6000_option_override_internal): Add -mxxsplti32dx support. (xxsplti32dx_constant_p): New helper function. (output_vec_const_move): Split constants that need XXSPLTI32DX. (rs6000_opt_masks): Add -mxxsplti32dx. * config/rs6000/rs6000.md (movsf_hardfloat): Add support for loading constants with XXSPLTI32DX. (mov_hardfloat32, FMOVE64 iterator): Add support for loading constants with XXSPLTI32DX. (mov_hardfloat64, FMOVE64 iterator): Add support for loading constants with XXSPLTI32DX. * config/rs6000/rs6000.opt (-mxxsplti32dx): New switch. * config/rs6000/vsx.md (UNSPEC_XXSPLTI32DX_CONST): New unspec. (vsx_mov_64bit): Add support for loading constants with XXSPLTI32DX. (vsx_mov_32bit): Add support for loading constants with XXSPLTI32DX. (XXSPLTI32DX): New mode iterator. (xxsplti32dx_): New insn and splits. (xxsplti32dx__first): New insns. (xxsplti32dx__second): New insns. gcc/testsuite/ 2021-04-08 Michael Meissner Revert patch. * gcc.target/powerpc/vec-splati-runnable.c: Update insn count. Diff: --- gcc/config/rs6000/constraints.md | 6 - gcc/config/rs6000/predicates.md | 22 ---- gcc/config/rs6000/rs6000-cpus.def | 2 - gcc/config/rs6000/rs6000-protos.h | 1 - gcc/config/rs6000/rs6000.c | 94 ---------------- gcc/config/rs6000/rs6000.md | 44 +++----- gcc/config/rs6000/rs6000.opt | 4 - gcc/config/rs6000/vsx.md | 121 +++------------------ .../gcc.target/powerpc/vec-splati-runnable.c | 2 +- 9 files changed, 29 insertions(+), 267 deletions(-) diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md index c7137337f4c..70b1eb01770 100644 --- a/gcc/config/rs6000/constraints.md +++ b/gcc/config/rs6000/constraints.md @@ -208,12 +208,6 @@ (and (match_code "const_int") (match_test "((- (unsigned HOST_WIDE_INT) ival) + 0x8000) < 0x10000"))) -;; SF/DF/V2DF/DI/V2DI scalar or vector constant that can be loaded with a pair -;; of XXSPLTI32DX instructions. -(define_constraint "eD" - "A vector constant that can be loaded with XXSPLTI32DX instructions." - (match_operand 0 "xxsplti32dx_operand")) - ;; SF/DF/V2DF scalar or vector constant that can be loaded with XXSPLTIDP (define_constraint "eF" "A vector constant that can be loaded with the XXSPLTIDP instruction." diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index 281c6e835b9..48d9c5509a2 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -606,11 +606,6 @@ if (xxspltidp_operand (op, mode)) return 1; - /* If we have the ISA 3.1 XXSPLTI32DX instruction, see if the constant can - be loaded with a pair of those instructions. */ - if (xxsplti32dx_operand (op, mode)) - return 1; - /* Otherwise consider floating point constants hard, so that the constant gets pushed to memory during the early RTL phases. This has the advantage that double precision constants that can be @@ -682,20 +677,6 @@ return xxspltidp_constant_p (op, mode, &value); }) -;; Return 1 if operand is a SF/DF CONST_DOUBLE or V2DF CONST_VECTOR that can be -;; loaded via a pair f ISA 3.1 XXSPLTI32DX instructions. Do not return true if -;; the value is 0.0 or it can be loaded with XXSPLTIDP, since that is easy to -;; generate without using XXSPLTI32DX. -(define_predicate "xxsplti32dx_operand" - (match_code "const_double,const_int,const_vector,vec_duplicate") -{ - if (op == CONST0_RTX (mode)) - return false; - - HOST_WIDE_INT value = 0; - return xxsplti32dx_constant_p (op, mode, &value); -}) - ;; Return 1 if the operand is a CONST_VECTOR and can be loaded into a ;; vector register without using memory. (define_predicate "easy_vector_constant" @@ -715,9 +696,6 @@ if (xxspltidp_operand (op, mode)) return true; - if (xxsplti32dx_operand (op, mode)) - return true; - if (TARGET_P9_VECTOR && xxspltib_constant_p (op, mode, &num_insns, &value)) return true; diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def index 5a14191cc6c..cf4044831f7 100644 --- a/gcc/config/rs6000/rs6000-cpus.def +++ b/gcc/config/rs6000/rs6000-cpus.def @@ -79,7 +79,6 @@ | OPTION_MASK_PCREL \ | OPTION_MASK_PCREL_OPT \ | OPTION_MASK_PREFIXED \ - | OPTION_MASK_XXSPLTI32DX \ | OPTION_MASK_XXSPLTIDP \ | OPTION_MASK_XXSPLTIW) @@ -164,7 +163,6 @@ | OPTION_MASK_SOFT_FLOAT \ | OPTION_MASK_STRICT_ALIGN_OPTIONAL \ | OPTION_MASK_VSX \ - | OPTION_MASK_XXSPLTI32DX \ | OPTION_MASK_XXSPLTIDP \ | OPTION_MASK_XXSPLTIW) diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h index 12bf60b043d..0fe1c176236 100644 --- a/gcc/config/rs6000/rs6000-protos.h +++ b/gcc/config/rs6000/rs6000-protos.h @@ -34,7 +34,6 @@ extern bool easy_altivec_constant (rtx, machine_mode); extern bool xxspltib_constant_p (rtx, machine_mode, int *, int *); extern bool xxspltiw_constant_p (rtx, machine_mode, HOST_WIDE_INT *); extern bool xxspltidp_constant_p (rtx, machine_mode, HOST_WIDE_INT *); -extern bool xxsplti32dx_constant_p (rtx, machine_mode, HOST_WIDE_INT *); extern int vspltis_shifted (rtx); extern HOST_WIDE_INT const_vector_elt_as_int (rtx, unsigned int); extern bool macho_lo_sum_memory_operand (rtx, machine_mode); diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 659eb301c87..08a853f2e8f 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -4484,10 +4484,6 @@ rs6000_option_override_internal (bool global_init_p) && (rs6000_isa_flags_explicit & OPTION_MASK_XXSPLTIDP) == 0) rs6000_isa_flags |= OPTION_MASK_XXSPLTIDP; - if (TARGET_POWER10 && TARGET_VSX - && (rs6000_isa_flags_explicit & OPTION_MASK_XXSPLTI32DX) == 0) - rs6000_isa_flags |= OPTION_MASK_XXSPLTI32DX; - if (!TARGET_PCREL && TARGET_PCREL_OPT) rs6000_isa_flags &= ~OPTION_MASK_PCREL_OPT; @@ -6614,92 +6610,6 @@ xxspltidp_constant_p (rtx op, return true; } -/* Return true if OP is of the given MODE and can be synthesized with ISA 3.1 - XXSPLTI32DX instruction. If the instruction can be synthesized with - XXSPLTIDP or is 0/-1, return false; - - Return the 64-bit constant to use in the two XXSPLTI32DX instructions via - CONSTANT_PTR. */ - -bool -xxsplti32dx_constant_p (rtx op, - machine_mode mode, - HOST_WIDE_INT *constant_ptr) -{ - *constant_ptr = 0; - - if (!TARGET_XXSPLTI32DX) - return false; - - if (mode == VOIDmode) - mode = GET_MODE (op); - - if (op == CONST0_RTX (mode)) - return false; - - rtx element = op; - if (mode == V2DFmode || mode == V2DImode) - { - /* Handle VEC_DUPLICATE and CONST_VECTOR. */ - if (GET_CODE (op) == VEC_DUPLICATE) - element = XEXP (op, 0); - - else if (GET_CODE (op) == CONST_VECTOR) - { - element = CONST_VECTOR_ELT (op, 0); - if (!rtx_equal_p (element, CONST_VECTOR_ELT (op, 1))) - return false; - } - - else - return false; - - mode = GET_MODE_INNER (mode); - } - - if (GET_MODE (element) != mode) - return false; - - /* Handle floating point constants. */ - if (mode == SFmode || mode == DFmode) - { - HOST_WIDE_INT xxspltidp_value = 0; - - if (!CONST_DOUBLE_P (element)) - return false; - - if (xxspltidp_constant_p (element, mode, &xxspltidp_value)) - return false; - - long high_low[2]; - const struct real_value *rv = CONST_DOUBLE_REAL_VALUE (element); - REAL_VALUE_TO_TARGET_DOUBLE (*rv, high_low); - - if (!BYTES_BIG_ENDIAN) - std::swap (high_low[0], high_low[1]); - - *constant_ptr = (high_low[0] << 32) | (high_low[1] & 0xffffffff); - return true; - } - - /* Handle integer constants. */ - else if (mode == DImode) - { - if (!CONST_INT_P (element)) - return false; - - HOST_WIDE_INT value = INTVAL (element); - if (value == -1) - return false; - - *constant_ptr = value; - return true; - } - - else - return false; -} - const char * output_vec_const_move (rtx *operands) { @@ -6773,9 +6683,6 @@ output_vec_const_move (rtx *operands) return "xxspltidp %x0,%2"; } - if (xxsplti32dx_operand (vec, mode)) - return "#"; - if (TARGET_P9_VECTOR && xxspltib_constant_p (vec, mode, &num_insns, &xxspltib_value)) { @@ -24275,7 +24182,6 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] = { "vsx", OPTION_MASK_VSX, false, true }, { "xxspltiw", OPTION_MASK_XXSPLTIW, false, true }, { "xxspltidp", OPTION_MASK_XXSPLTIDP, false, true }, - { "xxsplti32dx", OPTION_MASK_XXSPLTI32DX, false, true }, #ifdef OPTION_MASK_64BIT #if TARGET_AIX_OS { "aix64", OPTION_MASK_64BIT, false, false }, diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index b5886d3ccf4..5569e0591e6 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -7564,17 +7564,17 @@ ;; ;; LWZ LFS LXSSP LXSSPX STFS STXSSP ;; STXSSPX STW XXLXOR LI FMR XSCPSGNDP -;; MR MT MF NOP XXSPLTIDP XXSPLTI32DX +;; MR MT MF NOP XXSPLTIDP (define_insn "movsf_hardfloat" [(set (match_operand:SF 0 "nonimmediate_operand" "=!r, f, v, wa, m, wY, Z, m, wa, !r, f, wa, - !r, *c*l, !r, *h, wa, wa") + !r, *c*l, !r, *h, wa") (match_operand:SF 1 "input_operand" "m, m, wY, Z, f, v, wa, r, j, j, f, wa, - r, r, *h, 0, eF, eD"))] + r, r, *h, 0, eF"))] "(register_operand (operands[0], SFmode) || register_operand (operands[1], SFmode)) && TARGET_HARD_FLOAT @@ -7597,28 +7597,19 @@ mt%0 %1 mf%1 %0 nop - # #" [(set_attr "type" "load, fpload, fpload, fpload, fpstore, fpstore, fpstore, store, veclogical, integer, fpsimple, fpsimple, - *, mtjmpr, mfjmpr, *, vecperm, vecperm") + *, mtjmpr, mfjmpr, *, vecperm") (set_attr "isa" "*, *, p9v, p8v, *, p9v, p8v, *, *, *, *, *, - *, *, *, *, p10, p10") + *, *, *, *, p10") (set_attr "prefixed" "*, *, *, *, *, *, *, *, *, *, *, *, - *, *, *, *, yes, yes") - (set_attr "max_prefixed_insns" - "*, *, *, *, *, *, - *, *, *, *, *, *, - *, *, *, *, *, 2") - (set_attr "num_insns" - "*, *, *, *, *, *, - *, *, *, *, *, *, - *, *, *, *, *, 2")]) + *, *, *, *, yes")]) ;; LWZ LFIWZX STW STFIWX MTVSRWZ MFVSRWZ ;; FMR MR MT%0 MF%1 NOP @@ -7878,18 +7869,18 @@ ;; STFD LFD FMR LXSD STXSD ;; LXSD STXSD XXLOR XXLXOR GPR<-0 -;; LWZ STW MR XXSPLTIDP XXSPLTI32DX +;; LWZ STW MR XXSPLTIDP (define_insn "*mov_hardfloat32" [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m, d, d, , wY, , Z, , , !r, - Y, r, !r, wa, wa") + Y, r, !r, wa") (match_operand:FMOVE64 1 "input_operand" "d, m, d, wY, , Z, , , , , - r, Y, r, eF, eD"))] + r, Y, r, eF"))] "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && (gpc_reg_operand (operands[0], mode) || gpc_reg_operand (operands[1], mode))" @@ -7907,33 +7898,24 @@ # # # - # #" [(set_attr "type" "fpstore, fpload, fpsimple, fpload, fpstore, fpload, fpstore, veclogical, veclogical, two, - store, load, two, vecperm, vecperm") + store, load, two, vecperm") (set_attr "size" "64") (set_attr "length" "*, *, *, *, *, *, *, *, *, 8, - 8, 8, 8, *, *") + 8, 8, 8, *") (set_attr "isa" "*, *, *, p9v, p9v, p7v, p7v, *, *, *, - *, *, *, p10, p10") + *, *, *, p10") (set_attr "prefixed" "*, *, *, *, *, *, *, *, *, *, - *, *, *, yes, yes") - (set_attr "max_prefixed_insns" - "*, *, *, *, *, - *, *, *, *, *, - *, *, *, *, 2") - (set_attr "num_insns" - "*, *, *, *, *, - *, *, *, *, *, - *, *, *, *, 2")]) + *, *, *, yes")]) ;; STW LWZ MR G-const H-const F-const diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index bd269369ca0..6620cdb7716 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -627,7 +627,3 @@ Generate (do not generate) the XXSPLTIW instruction. mxxspltidp Target Undocumented Mask(XXSPLTIDP) Var(rs6000_isa_flags) Generate (do not generate) the XXSPLTIDP instruction. - -mxxsplti32dx -Target Undocumented Mask(XXSPLTI32DX) Var(rs6000_isa_flags) -Generate (do not generate) the XXSPLTI32DX instruction. diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 877f1cdca39..4b0307d447e 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -372,7 +372,6 @@ UNSPEC_XXSPLTIW UNSPEC_XXSPLTIDP UNSPEC_XXSPLTI32DX - UNSPEC_XXSPLTI32DX_CONST UNSPEC_XXPERMX UNSPEC_XXEVAL ]) @@ -1174,19 +1173,16 @@ ;; VSX store VSX load VSX move VSX->GPR GPR->VSX LQ (GPR) ;; STQ (GPR) GPR load GPR store GPR move XXSPLTIB VSPLTISW ;; VSX 0/-1 VMX const GPR const LVX (VMX) STVX (VMX) XXSPLTI* -;; XXSPLTI32DX (define_insn "vsx_mov_64bit" [(set (match_operand:VSX_M 0 "nonimmediate_operand" "=ZwO, wa, wa, r, we, ?wQ, ?&r, ??r, ??Y, , wa, v, - ?wa, v, , wZ, v, wa, - wa") + ?wa, v, , wZ, v, wa") (match_operand:VSX_M 1 "input_operand" "wa, ZwO, wa, we, r, r, wQ, Y, r, r, wE, jwM, - ?jwM, W, , v, wZ, eWeF, - eD"))] + ?jwM, W, , v, wZ, eWeF"))] "TARGET_POWERPC64 && VECTOR_MEM_VSX_P (mode) && (register_operand (operands[0], mode) @@ -1197,47 +1193,41 @@ [(set_attr "type" "vecstore, vecload, vecsimple, mtvsr, mfvsr, load, store, load, store, *, vecsimple, vecsimple, - vecsimple, *, *, vecstore, vecload, vecperm, - vecperm") + vecsimple, *, *, vecstore, vecload, vecperm") (set_attr "num_insns" "*, *, *, 2, *, 2, 2, 2, 2, 2, *, *, - *, 5, 2, *, *, *, - 2") + *, 5, 2, *, *, *") (set_attr "max_prefixed_insns" "*, *, *, *, *, 2, 2, 2, 2, 2, *, *, - *, *, *, *, *, *, - 2") + *, *, *, *, *, *") (set_attr "length" "*, *, *, 8, *, 8, 8, 8, 8, 8, *, *, - *, 20, 8, *, *, *, - *") + *, 20, 8, *, *, *") (set_attr "isa" ", , , *, *, *, *, *, *, *, p9v, *, - , *, *, *, *, p10, - p10") + , *, *, *, *, p10") (set_attr "prefixed" "*, *, *, *, *, *, *, *, *, *, *, *, - *, *, *, *, *, yes, - yes")]) + *, *, *, *, *, yes")]) ;; VSX store VSX load VSX move GPR load GPR store GPR move ;; XXSPLTIB VSPLTISW VSX 0/-1 VMX const GPR const XXSPLTI* -;; LVX (VMX) STVX (VMX) XXSPLTI32DX +;; LVX (VMX) STVX (VMX) (define_insn "*vsx_mov_32bit" [(set (match_operand:VSX_M 0 "nonimmediate_operand" "=ZwO, wa, wa, ??r, ??Y, , wa, v, ?wa, v, , wa, - wZ, v, wa") + wZ, v") (match_operand:VSX_M 1 "input_operand" "wa, ZwO, wa, Y, r, r, wE, jwM, ?jwM, W, , eWeF, - v, wZ, eD"))] + v, wZ"))] "!TARGET_POWERPC64 && VECTOR_MEM_VSX_P (mode) && (register_operand (operands[0], mode) @@ -1248,27 +1238,19 @@ [(set_attr "type" "vecstore, vecload, vecsimple, load, store, *, vecsimple, vecsimple, vecsimple, *, *, vecperm, - vecstore, vecload, vecperm") + vecstore, vecload") (set_attr "length" "*, *, *, 16, 16, 16, *, *, *, 20, 16, *, - *, *, *") + *, *") (set_attr "isa" ", , , *, *, *, p9v, *, , *, *, p10, - *, *, p10") + *, *") (set_attr "prefixed" "*, *, *, *, *, *, *, *, *, *, *, yes, - *, *, yes") - (set_attr "max_prefixed_insns" - "*, *, *, *, *, *, - *, *, *, *, *, *, - *, *, 2") - (set_attr "num_insns" - "*, *, *, *, *, *, - *, *, *, *, *, *, - *, *, *")]) + *, *")]) ;; Explicit load/store expanders for the builtin functions (define_expand "vsx_load_" @@ -6348,79 +6330,6 @@ DONE; }) -;; XXSPLTI32DX used to create 64-bit constants -(define_mode_iterator XXSPLTI32DX [SF DF V2DF V2DI]) - -(define_insn_and_split "*xxsplti32dx_" - [(set (match_operand:XXSPLTI32DX 0 "vsx_register_operand" "=wa") - (match_operand:XXSPLTI32DX 1 "xxsplti32dx_operand"))] - "TARGET_XXSPLTI32DX" - "#" - "&& 1" - [(set (match_dup 0) - (unspec:XXSPLTI32DX [(match_dup 2) - (match_dup 3)] UNSPEC_XXSPLTI32DX_CONST)) - (set (match_dup 0) - (unspec:XXSPLTI32DX [(match_dup 0) - (match_dup 4) - (match_dup 5)] UNSPEC_XXSPLTI32DX_CONST))] -{ - HOST_WIDE_INT value = 0; - - if (!xxsplti32dx_constant_p (operands[1], mode, &value)) - gcc_unreachable (); - - HOST_WIDE_INT high = value >> 32; - HOST_WIDE_INT low = value & 0xffffffff; - - /* If the low bits are 0/-1, initialize that word first. This way we can - use a smaller XXSPLTIB instruction instead the first XXSPLTI32DX. */ - if (low == 0 || low == -1) - { - operands[2] = const1_rtx; - operands[3] = GEN_INT (low); - operands[4] = const0_rtx; - operands[5] = GEN_INT (high); - } - else - { - operands[2] = const0_rtx; - operands[3] = GEN_INT (high); - operands[4] = const1_rtx; - operands[5] = GEN_INT (low); - } -} - [(set_attr "type" "vecperm") - (set_attr "prefixed" "yes") - (set_attr "num_insns" "2") - (set_attr "max_prefixed_insns" "2")]) - -;; First word of XXSPLTI32DX -(define_insn "*xxsplti32dx__first" - [(set (match_operand:XXSPLTI32DX 0 "vsx_register_operand" "=wa,wa,wa") - (unspec:XXSPLTI32DX [(match_operand 1 "u1bit_cint_operand" "n,n,n") - (match_operand 2 "const_int_operand" "O,wM,n")] - UNSPEC_XXSPLTI32DX_CONST))] - "TARGET_XXSPLTI32DX" - "@ - xxspltib %x0,0 - xxspltib %x0,255 - xxsplti32dx %x0,%1,%2" - [(set_attr "type" "vecperm") - (set_attr "prefixed" "*,*,yes")]) - -;; Second word of XXSPLTI32DX -(define_insn "*xxsplti32dx__second" - [(set (match_operand:XXSPLTI32DX 0 "vsx_register_operand" "=wa") - (unspec:XXSPLTI32DX [(match_dup 0) - (match_operand 1 "u1bit_cint_operand" "n") - (match_operand 2 "const_int_operand" "n")] - UNSPEC_XXSPLTI32DX_CONST))] - "TARGET_XXSPLTI32DX" - "xxsplti32dx %x0,%1,%2" - [(set_attr "type" "vecperm") - (set_attr "prefixed" "yes")]) - ;; XXSPLTI32DX built-in support. (define_expand "xxsplti32dx_v4si" [(set (match_operand:V4SI 0 "register_operand" "=wa") diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c b/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c index f0eb982eadf..06a8289d09b 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c @@ -162,4 +162,4 @@ main (int argc, char *argv []) /* { dg-final { scan-assembler-times {\mxxspltiw\M} 1 } } */ /* { dg-final { scan-assembler-times {\mxxspltidp\M} 2 } } */ -/* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 4 } } */ +/* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 3 } } */