From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id D41A13848011; Wed, 14 Apr 2021 22:33:54 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org D41A13848011 Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work048)] Revert patch. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work048 X-Git-Oldrev: 951843f745756143dac6c1d02e7fc846db7b465e X-Git-Newrev: 4c3d14b2323d5c55718af3b4b9b0f7457fbcb679 Message-Id: <20210414223354.D41A13848011@sourceware.org> Date: Wed, 14 Apr 2021 22:33:54 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 14 Apr 2021 22:33:55 -0000 https://gcc.gnu.org/g:4c3d14b2323d5c55718af3b4b9b0f7457fbcb679 commit 4c3d14b2323d5c55718af3b4b9b0f7457fbcb679 Author: Michael Meissner Date: Wed Apr 14 18:33:14 2021 -0400 Revert patch. gcc/ 2021-04-14 Michael Meissner Revert patch. * config/rs6000/rs6000.c (have_compare_and_set_mask): Add IEEE 128-bit floating point types. * config/rs6000/rs6000.md (FPMASK): New iterator. (FPMASK2): New iterator. (Fv mode attribute): Add KFmode and TFmode. (movcc_fpmask): Replace movcc_p9. Add IEEE 128-bit fp support. (movcc_invert_fpmask): Replace movcc_invert_p9. Add IEEE 128-bit fp support. (fpmask): Add IEEE 128-bit fp support. Enable generator to build te RTL. (xxsel): Add IEEE 128-bit fp support. Enable generator to build te RTL. gcc/testsuite/ 2021-04-14 Michael Meissner Revert patch. * gcc.target/powerpc/float128-cmove.c: New test. * gcc.target/powerpc/float128-minmax-3.c: New test. Diff: --- gcc/config/rs6000/rs6000.c | 8 +- gcc/config/rs6000/rs6000.md | 190 +++++++-------------- gcc/testsuite/gcc.target/powerpc/float128-cmove.c | 93 ---------- .../gcc.target/powerpc/float128-minmax-3.c | 15 -- 4 files changed, 66 insertions(+), 240 deletions(-) diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index fecdcf6e01e..8d00f99e9fd 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -15706,8 +15706,8 @@ rs6000_emit_vector_cond_expr (rtx dest, rtx op_true, rtx op_false, return 1; } -/* Possibly emit the xsmaxc{dp,qp} and xsminc{dp,qp} instructions to emit a - maximum or minimum with "C" semantics. +/* Possibly emit the xsmaxcdp and xsmincdp instructions to emit a maximum or + minimum with "C" semantics. Unless you use -ffast-math, you can't use these instructions to replace conditions that implicitly reverse the condition because the comparison @@ -15843,10 +15843,6 @@ have_compare_and_set_mask (machine_mode mode) case E_DFmode: return TARGET_P9_MINMAX; - case E_KFmode: - case E_TFmode: - return (TARGET_POWER10 && TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)); - default: break; } diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 33f3e7c2159..17b2fdc1cdd 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -575,23 +575,6 @@ ; And again, for when we need two FP modes in a pattern. (define_mode_iterator SFDF2 [SF DF]) -; Floating scalars that supports the set compare mask instruction. -(define_mode_iterator FPMASK [SF - DF - (KF "(TARGET_POWER10 && TARGET_FLOAT128_HW - && FLOAT128_IEEE_P (KFmode))") - (TF "(TARGET_POWER10 && TARGET_FLOAT128_HW - && FLOAT128_IEEE_P (TFmode))")]) - -; And again, for patterns that need two (potentially) different floating point -; scalars that support the set compare mask instruction. -(define_mode_iterator FPMASK2 [SF - DF - (KF "(TARGET_POWER10 && TARGET_FLOAT128_HW - && FLOAT128_IEEE_P (KFmode))") - (TF "(TARGET_POWER10 && TARGET_FLOAT128_HW - && FLOAT128_IEEE_P (TFmode))")]) - ; A generic s/d attribute, for sp/dp for example. (define_mode_attr sd [(SF "s") (DF "d") (V4SF "s") (V2DF "d")]) @@ -625,13 +608,8 @@ ; SF/DF constraint for arithmetic on VSX registers using instructions added in ; ISA 2.06 (power7). This includes instructions that normally target DF mode, ; but are used on SFmode, since internally SFmode values are kept in the DFmode -; format. Also include IEEE 128-bit instructions which are restricted to the -; Altivec registers. -(define_mode_attr Fv [(SF "wa") - (DF "wa") - (DI "wa") - (KF "v") - (TF "v")]) +; format. +(define_mode_attr Fv [(SF "wa") (DF "wa") (DI "wa")]) ; Which isa is needed for those float instructions? (define_mode_attr Fisa [(SF "p8v") (DF "*") (DI "*")]) @@ -5338,10 +5316,10 @@ ;; Floating point conditional move (define_expand "movcc" - [(set (match_operand:FPMASK 0 "gpc_reg_operand") - (if_then_else:FPMASK (match_operand 1 "comparison_operator") - (match_operand:FPMASK 2 "gpc_reg_operand") - (match_operand:FPMASK 3 "gpc_reg_operand")))] + [(set (match_operand:SFDF 0 "gpc_reg_operand") + (if_then_else:SFDF (match_operand 1 "comparison_operator") + (match_operand:SFDF 2 "gpc_reg_operand") + (match_operand:SFDF 3 "gpc_reg_operand")))] "TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT" { if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) @@ -5361,132 +5339,92 @@ "fsel %0,%1,%2,%3" [(set_attr "type" "fp")]) -(define_insn_and_split "*movcc_fpmask" - [(set (match_operand:FPMASK 0 "vsx_register_operand" "=") - (if_then_else:FPMASK +(define_insn_and_split "*movcc_p9" + [(set (match_operand:SFDF 0 "vsx_register_operand" "=&,") + (if_then_else:SFDF (match_operator:CCFP 1 "fpmask_comparison_operator" - [(match_operand:FPMASK2 2 "vsx_register_operand" "") - (match_operand:FPMASK2 3 "vsx_register_operand" "")]) - (match_operand:FPMASK 4 "vsx_register_operand" "") - (match_operand:FPMASK 5 "vsx_register_operand" ""))) - (clobber (match_scratch:V2DI 6 "=&"))] + [(match_operand:SFDF2 2 "vsx_register_operand" ",") + (match_operand:SFDF2 3 "vsx_register_operand" ",")]) + (match_operand:SFDF 4 "vsx_register_operand" ",") + (match_operand:SFDF 5 "vsx_register_operand" ","))) + (clobber (match_scratch:V2DI 6 "=0,&wa"))] "TARGET_P9_MINMAX" "#" "&& 1" - [(pc)] + [(set (match_dup 6) + (if_then_else:V2DI (match_dup 1) + (match_dup 7) + (match_dup 8))) + (set (match_dup 0) + (if_then_else:SFDF (ne (match_dup 6) + (match_dup 8)) + (match_dup 4) + (match_dup 5)))] { - rtx dest = operands[0]; - rtx cmp = operands[1]; - rtx cmp_op1 = operands[2]; - rtx cmp_op2 = operands[3]; - rtx move_t = operands[4]; - rtx move_f = operands[5]; - rtx mask_reg = operands[6]; - rtx mask_m1 = CONSTM1_RTX (V2DImode); - rtx mask_0 = CONST0_RTX (V2DImode); - machine_mode move_mode = mode; - machine_mode compare_mode = mode; - - if (GET_CODE (mask_reg) == SCRATCH) - mask_reg = gen_reg_rtx (V2DImode); + if (GET_CODE (operands[6]) == SCRATCH) + operands[6] = gen_reg_rtx (V2DImode); - /* Emit the compare and set mask instruction. */ - emit_insn (gen_fpmask (mask_reg, cmp, cmp_op1, cmp_op2, - mask_m1, mask_0)); - - /* If we have a 64-bit comparison, but an 128-bit move, we need to extend the - mask. Because we are using the splat builtin to extend the V2DImode, we - need to use element 1 on little endian systems. */ - if (!FLOAT128_IEEE_P (compare_mode) && FLOAT128_IEEE_P (move_mode)) - { - rtx element = WORDS_BIG_ENDIAN ? const0_rtx : const1_rtx; - emit_insn (gen_vsx_xxspltd_v2di (mask_reg, mask_reg, element)); - } - - /* Now emit the XXSEL insn. */ - emit_insn (gen_xxsel (dest, mask_reg, mask_0, move_t, move_f)); - DONE; + operands[7] = CONSTM1_RTX (V2DImode); + operands[8] = CONST0_RTX (V2DImode); } - ;; length is 12 in case we need to add XXPERMDI - [(set_attr "length" "12") + [(set_attr "length" "8") (set_attr "type" "vecperm")]) ;; Handle inverting the fpmask comparisons. -(define_insn_and_split "*movcc_invert_fpmask" - [(set (match_operand:FPMASK 0 "vsx_register_operand" "=") - (if_then_else:FPMASK +(define_insn_and_split "*movcc_invert_p9" + [(set (match_operand:SFDF 0 "vsx_register_operand" "=&,") + (if_then_else:SFDF (match_operator:CCFP 1 "invert_fpmask_comparison_operator" - [(match_operand:FPMASK2 2 "vsx_register_operand" "") - (match_operand:FPMASK2 3 "vsx_register_operand" "")]) - (match_operand:FPMASK 4 "vsx_register_operand" "") - (match_operand:FPMASK 5 "vsx_register_operand" ""))) - (clobber (match_scratch:V2DI 6 "=&"))] + [(match_operand:SFDF2 2 "vsx_register_operand" ",") + (match_operand:SFDF2 3 "vsx_register_operand" ",")]) + (match_operand:SFDF 4 "vsx_register_operand" ",") + (match_operand:SFDF 5 "vsx_register_operand" ","))) + (clobber (match_scratch:V2DI 6 "=0,&wa"))] "TARGET_P9_MINMAX" "#" "&& 1" - [(pc)] + [(set (match_dup 6) + (if_then_else:V2DI (match_dup 9) + (match_dup 7) + (match_dup 8))) + (set (match_dup 0) + (if_then_else:SFDF (ne (match_dup 6) + (match_dup 8)) + (match_dup 5) + (match_dup 4)))] { - rtx dest = operands[0]; - rtx old_cmp = operands[1]; - rtx cmp_op1 = operands[2]; - rtx cmp_op2 = operands[3]; - enum rtx_code cond = reverse_condition_maybe_unordered (GET_CODE (old_cmp)); - rtx cmp_rev = gen_rtx_fmt_ee (cond, CCFPmode, cmp_op1, cmp_op2); - rtx move_f = operands[4]; - rtx move_t = operands[5]; - rtx mask_reg = operands[6]; - rtx mask_m1 = CONSTM1_RTX (V2DImode); - rtx mask_0 = CONST0_RTX (V2DImode); - machine_mode move_mode = mode; - machine_mode compare_mode = mode; + rtx op1 = operands[1]; + enum rtx_code cond = reverse_condition_maybe_unordered (GET_CODE (op1)); - if (GET_CODE (mask_reg) == SCRATCH) - mask_reg = gen_reg_rtx (V2DImode); + if (GET_CODE (operands[6]) == SCRATCH) + operands[6] = gen_reg_rtx (V2DImode); - /* Emit the compare and set mask instruction. */ - emit_insn (gen_fpmask (mask_reg, cmp_rev, cmp_op1, cmp_op2, - mask_m1, mask_0)); + operands[7] = CONSTM1_RTX (V2DImode); + operands[8] = CONST0_RTX (V2DImode); - /* If we have a 64-bit comparison, but an 128-bit move, we need to extend the - mask. Because we are using the splat builtin to extend the V2DImode, we - need to use element 1 on little endian systems. */ - if (!FLOAT128_IEEE_P (compare_mode) && FLOAT128_IEEE_P (move_mode)) - { - rtx element = WORDS_BIG_ENDIAN ? const0_rtx : const1_rtx; - emit_insn (gen_vsx_xxspltd_v2di (mask_reg, mask_reg, element)); - } - - /* Now emit the XXSEL insn. */ - emit_insn (gen_xxsel (dest, mask_reg, mask_0, move_t, move_f)); - DONE; + operands[9] = gen_rtx_fmt_ee (cond, CCFPmode, operands[2], operands[3]); } - ;; length is 12 in case we need to add XXPERMDI - [(set_attr "length" "12") + [(set_attr "length" "8") (set_attr "type" "vecperm")]) -(define_insn "fpmask" - [(set (match_operand:V2DI 0 "vsx_register_operand" "=") +(define_insn "*fpmask" + [(set (match_operand:V2DI 0 "vsx_register_operand" "=wa") (if_then_else:V2DI (match_operator:CCFP 1 "fpmask_comparison_operator" - [(match_operand:FPMASK 2 "vsx_register_operand" "") - (match_operand:FPMASK 3 "vsx_register_operand" "")]) + [(match_operand:SFDF 2 "vsx_register_operand" "") + (match_operand:SFDF 3 "vsx_register_operand" "")]) (match_operand:V2DI 4 "all_ones_constant" "") (match_operand:V2DI 5 "zero_constant" "")))] "TARGET_P9_MINMAX" -{ - return (FLOAT128_IEEE_P (mode) - ? "xscmp%V1qp %0,%2,%3" - : "xscmp%V1dp %x0,%x2,%x3"); -} + "xscmp%V1dp %x0,%x2,%x3" [(set_attr "type" "fpcompare")]) -(define_insn "xxsel" - [(set (match_operand:FPMASK 0 "vsx_register_operand" "=wa") - (if_then_else:FPMASK - (ne (match_operand:V2DI 1 "vsx_register_operand" "wa") - (match_operand:V2DI 2 "zero_constant" "")) - (match_operand:FPMASK 3 "vsx_register_operand" "wa") - (match_operand:FPMASK 4 "vsx_register_operand" "wa")))] +(define_insn "*xxsel" + [(set (match_operand:SFDF 0 "vsx_register_operand" "=") + (if_then_else:SFDF (ne (match_operand:V2DI 1 "vsx_register_operand" "wa") + (match_operand:V2DI 2 "zero_constant" "")) + (match_operand:SFDF 3 "vsx_register_operand" "") + (match_operand:SFDF 4 "vsx_register_operand" "")))] "TARGET_P9_MINMAX" "xxsel %x0,%x4,%x3,%x1" [(set_attr "type" "vecmove")]) diff --git a/gcc/testsuite/gcc.target/powerpc/float128-cmove.c b/gcc/testsuite/gcc.target/powerpc/float128-cmove.c deleted file mode 100644 index 639d5a77087..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/float128-cmove.c +++ /dev/null @@ -1,93 +0,0 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target ppc_float128_hw } */ -/* { dg-require-effective-target power10_ok } */ -/* { dg-options "-mdejagnu-cpu=power10 -O2" } */ -/* { dg-final { scan-assembler {\mxscmpeq[dq]p\M} } } */ -/* { dg-final { scan-assembler {\mxxpermdi\M} } } */ -/* { dg-final { scan-assembler {\mxxsel\M} } } */ -/* { dg-final { scan-assembler-not {\mxscmpu[dq]p\M} } } */ -/* { dg-final { scan-assembler-not {\mfcmp[uo]\M} } } */ -/* { dg-final { scan-assembler-not {\mfsel\M} } } */ - -/* This series of tests tests whether you can do a conditional move where the - test is one floating point type, and the result is another floating point - type. - - If the comparison type is SF/DFmode, and the move type is IEEE 128-bit - floating point, we have to duplicate the mask in the lower 64-bits with - XXPERMDI because XSCMPEQDP clears the bottom 64-bits of the mask register. - - Going the other way (IEEE 128-bit comparsion, 64-bit move) is fine as the - mask word will be 128-bits. */ - -float -eq_f_d (float a, float b, double x, double y) -{ - return (x == y) ? a : b; -} - -double -eq_d_f (double a, double b, float x, float y) -{ - return (x == y) ? a : b; -} - -float -eq_f_f128 (float a, float b, __float128 x, __float128 y) -{ - return (x == y) ? a : b; -} - -double -eq_d_f128 (double a, double b, __float128 x, __float128 y) -{ - return (x == y) ? a : b; -} - -__float128 -eq_f128_f (__float128 a, __float128 b, float x, float y) -{ - return (x == y) ? a : b; -} - -__float128 -eq_f128_d (__float128 a, __float128 b, double x, double y) -{ - return (x != y) ? a : b; -} - -float -ne_f_d (float a, float b, double x, double y) -{ - return (x != y) ? a : b; -} - -double -ne_d_f (double a, double b, float x, float y) -{ - return (x != y) ? a : b; -} - -float -ne_f_f128 (float a, float b, __float128 x, __float128 y) -{ - return (x != y) ? a : b; -} - -double -ne_d_f128 (double a, double b, __float128 x, __float128 y) -{ - return (x != y) ? a : b; -} - -__float128 -ne_f128_f (__float128 a, __float128 b, float x, float y) -{ - return (x != y) ? a : b; -} - -__float128 -ne_f128_d (__float128 a, __float128 b, double x, double y) -{ - return (x != y) ? a : b; -} diff --git a/gcc/testsuite/gcc.target/powerpc/float128-minmax-3.c b/gcc/testsuite/gcc.target/powerpc/float128-minmax-3.c deleted file mode 100644 index 6f7627c0f2a..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/float128-minmax-3.c +++ /dev/null @@ -1,15 +0,0 @@ -/* { dg-require-effective-target ppc_float128_hw } */ -/* { dg-require-effective-target power10_ok } */ -/* { dg-options "-mdejagnu-cpu=power10 -O2" } */ - -#ifndef TYPE -#define TYPE _Float128 -#endif - -/* Test that the fminf128/fmaxf128 functions generate if/then/else and not a - call. */ -TYPE f128_min (TYPE a, TYPE b) { return (a < b) ? a : b; } -TYPE f128_max (TYPE a, TYPE b) { return (b > a) ? b : a; } - -/* { dg-final { scan-assembler {\mxsmaxcqp\M} } } */ -/* { dg-final { scan-assembler {\mxsmincqp\M} } } */