From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 1177A38515FA; Thu, 15 Apr 2021 17:58:13 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 1177A38515FA Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work048)] Move XXPERMX from altivec.md to vsx.md. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work048 X-Git-Oldrev: e0dfd4a9c73fefb98aaf5102d025d8d7d3cde709 X-Git-Newrev: 36d0ef8ed04853ca65c74fed6556a691ef44d699 Message-Id: <20210415175813.1177A38515FA@sourceware.org> Date: Thu, 15 Apr 2021 17:58:13 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 15 Apr 2021 17:58:13 -0000 https://gcc.gnu.org/g:36d0ef8ed04853ca65c74fed6556a691ef44d699 commit 36d0ef8ed04853ca65c74fed6556a691ef44d699 Author: Michael Meissner Date: Thu Apr 15 13:57:57 2021 -0400 Move XXPERMX from altivec.md to vsx.md. This patch moves the XXPERMX support from altivec.md to vsx.md. Given the instruction support all VSX registers, vsx.md is a more proper place for this instruction. In doing the move, I discovered that the xxpermx_insn used the "v" constraint (i.e. Altivec registers), while the instruction actually supports any VSX register, so I changed the constraint to "wa". I also changed the register_operand to the more specific vsx_register_operand. I was chatting with Pat Haugen, he said that the insn type should be "vecperm" and not "vecsimple", so I changed this as well. gcc/ 2021-04-15 Michael Meissner * config/rs6000/altivec.md (UNSPEC_XXPERMX): Move to vsx.md. (xxpermx): Move to vsx.md. (xxpermx_inst): Move to vsx.md. * config/rs6000/vsx.md (UNSPEC_XXPERMX): Move from altivec.md. (xxpermx): Move from altivec.md. Use vsx_register_operand instead of register_operand. Remove setting the insn attribute "type" on the expander. (xxpermx_inst): Move from altivec.md. Use vsx_register_operand instead of register_operand. Change the constraint from "v" to "wa" to match the instruction. Change insn type to vecperm. Diff: --- gcc/config/rs6000/altivec.md | 46 -------------------------------------------- gcc/config/rs6000/vsx.md | 46 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 46 insertions(+), 46 deletions(-) diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index 9af71e036ab..aa11bda1865 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -177,7 +177,6 @@ UNSPEC_SLDB UNSPEC_SRDB UNSPEC_XXBLEND - UNSPEC_XXPERMX ]) (define_c_enum "unspecv" @@ -828,51 +827,6 @@ [(set_attr "type" "vecsimple") (set_attr "prefixed" "yes")]) -(define_expand "xxpermx" - [(set (match_operand:V2DI 0 "register_operand" "+wa") - (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "wa") - (match_operand:V2DI 2 "register_operand" "wa") - (match_operand:V16QI 3 "register_operand" "wa") - (match_operand:QI 4 "u8bit_cint_operand" "n")] - UNSPEC_XXPERMX))] - "TARGET_POWER10" -{ - if (BYTES_BIG_ENDIAN) - emit_insn (gen_xxpermx_inst (operands[0], operands[1], - operands[2], operands[3], - operands[4])); - else - { - /* Reverse value of byte element indexes by XORing with 0xFF. - Reverse the 32-byte section identifier match by subracting bits [0:2] - of elemet from 7. */ - int value = INTVAL (operands[4]); - rtx vreg = gen_reg_rtx (V16QImode); - - emit_insn (gen_xxspltib_v16qi (vreg, GEN_INT (-1))); - emit_insn (gen_xorv16qi3 (operands[3], operands[3], vreg)); - value = 7 - value; - emit_insn (gen_xxpermx_inst (operands[0], operands[2], - operands[1], operands[3], - GEN_INT (value))); - } - - DONE; -} - [(set_attr "type" "vecsimple")]) - -(define_insn "xxpermx_inst" - [(set (match_operand:V2DI 0 "register_operand" "+v") - (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "v") - (match_operand:V2DI 2 "register_operand" "v") - (match_operand:V16QI 3 "register_operand" "v") - (match_operand:QI 4 "u3bit_cint_operand" "n")] - UNSPEC_XXPERMX))] - "TARGET_POWER10" - "xxpermx %x0,%x1,%x2,%x3,%4" - [(set_attr "type" "vecsimple") - (set_attr "prefixed" "yes")]) - (define_expand "vstrir_" [(set (match_operand:VIshort 0 "altivec_register_operand") (unspec:VIshort [(match_operand:VIshort 1 "altivec_register_operand")] diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 16d0555a684..a862e231758 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -372,6 +372,7 @@ UNSPEC_XXSPLTIDP UNSPEC_XXSPLTI32DX UNSPEC_XXSPLTI32DX_CONST + UNSPEC_XXPERMX ]) (define_int_iterator XVCVBF16 [UNSPEC_VSX_XVCVSPBF16 @@ -6462,3 +6463,48 @@ "xxsplti32dx %x0,%2,%3" [(set_attr "type" "vecsimple") (set_attr "prefixed" "yes")]) + +;; XXPERMX built-in function support. +(define_expand "xxpermx" + [(set (match_operand:V2DI 0 "vsx_register_operand" "+wa") + (unspec:V2DI [(match_operand:V2DI 1 "vsx_register_operand" "wa") + (match_operand:V2DI 2 "vsx_register_operand" "wa") + (match_operand:V16QI 3 "vsx_register_operand" "wa") + (match_operand:QI 4 "u8bit_cint_operand" "n")] + UNSPEC_XXPERMX))] + "TARGET_POWER10" +{ + if (BYTES_BIG_ENDIAN) + emit_insn (gen_xxpermx_inst (operands[0], operands[1], + operands[2], operands[3], + operands[4])); + else + { + /* Reverse value of byte element indexes by XORing with 0xFF. + Reverse the 32-byte section identifier match by subracting bits [0:2] + of elemet from 7. */ + int value = INTVAL (operands[4]); + rtx vreg = gen_reg_rtx (V16QImode); + + emit_insn (gen_xxspltib_v16qi (vreg, GEN_INT (-1))); + emit_insn (gen_xorv16qi3 (operands[3], operands[3], vreg)); + value = 7 - value; + emit_insn (gen_xxpermx_inst (operands[0], operands[2], + operands[1], operands[3], + GEN_INT (value))); + } + + DONE; +}) + +(define_insn "xxpermx_inst" + [(set (match_operand:V2DI 0 "vsx_register_operand" "+wa") + (unspec:V2DI [(match_operand:V2DI 1 "vsx_register_operand" "wa") + (match_operand:V2DI 2 "vsx_register_operand" "wa") + (match_operand:V16QI 3 "vsx_register_operand" "wa") + (match_operand:QI 4 "u3bit_cint_operand" "n")] + UNSPEC_XXPERMX))] + "TARGET_POWER10" + "xxpermx %x0,%x1,%x2,%x3,%4" + [(set_attr "type" "vecperm") + (set_attr "prefixed" "yes")])