[gcc(refs/users/meissner/heads/work048)] Move XXEVAL from altivec.md to vsx.md.

[Michael Meissner <meissner@gcc.gnu.org>]

https://gcc.gnu.org/g:8c1e657d27fb51e3fa592b3e9ad1f2529092ef1e

commit 8c1e657d27fb51e3fa592b3e9ad1f2529092ef1e
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Thu Apr 15 13:58:49 2021 -0400

    Move XXEVAL from altivec.md to vsx.md.
    
    This patch moves the XXEVAL support from altivec.md to vsx.md.  Given
    the instruction support all VSX registers, vsx.md is a more proper place
    for this instruction.
    
    The xxeval insn used "altivec_register_operand".  I replaced this with
    "vsx_register_operand" since the instruction takes any VSX register.
    
    I was chatting with Pat Haugen, he said that the insn type should be
    "vecperm" and not "vecsimple", so I changed this as well.
    
    gcc/
    2021-04-15  Michael Meissner  <meissner@linux.ibm.com>
    
            * config/rs6000/altivec.md (UNSPEC_XXEVAL): Move to vsx.md.
            (xxeval): Move to vsx.md.
            * config/rs6000/vsx.md (UNSPEC_XXEVAL): Move from altivec.md.
            (xxeval): Move from altivec.md.  Change altivec_register_operand
            to vsx_register_operand.  Change insn type to vecperm.

Diff:
---
 gcc/config/rs6000/altivec.md | 13 -------------
 gcc/config/rs6000/vsx.md     | 14 ++++++++++++++
 2 files changed, 14 insertions(+), 13 deletions(-)

diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index aa11bda1865..a1ba10b0275 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -171,7 +171,6 @@
    UNSPEC_VPEXTD
    UNSPEC_VCLRLB
    UNSPEC_VCLRRB
-   UNSPEC_XXEVAL
    UNSPEC_VSTRIR
    UNSPEC_VSTRIL
    UNSPEC_SLDB
@@ -3464,18 +3463,6 @@
   [(set_attr "type" "vecperm")
    (set_attr "isa" "p9v,*")])
 
-(define_insn "xxeval"
-  [(set (match_operand:V2DI 0 "register_operand" "=wa")
-	(unspec:V2DI [(match_operand:V2DI 1 "altivec_register_operand" "wa")
-		      (match_operand:V2DI 2 "altivec_register_operand" "wa")
-		      (match_operand:V2DI 3 "altivec_register_operand" "wa")
-		      (match_operand:QI 4 "u8bit_cint_operand" "n")]
-		     UNSPEC_XXEVAL))]
-   "TARGET_POWER10"
-   "xxeval %0,%1,%2,%3,%4"
-   [(set_attr "type" "vecsimple")
-    (set_attr "prefixed" "yes")])
-
 (define_expand "vec_unpacku_hi_v16qi"
   [(set (match_operand:V8HI 0 "register_operand" "=v")
         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index a862e231758..0e5fb21d234 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -373,6 +373,7 @@
    UNSPEC_XXSPLTI32DX
    UNSPEC_XXSPLTI32DX_CONST
    UNSPEC_XXPERMX
+   UNSPEC_XXEVAL
   ])
 
 (define_int_iterator XVCVBF16	[UNSPEC_VSX_XVCVSPBF16
@@ -6508,3 +6509,16 @@
   "xxpermx %x0,%x1,%x2,%x3,%4"
   [(set_attr "type" "vecperm")
    (set_attr "prefixed" "yes")])
+
+;; XXEVAL built-in function support.
+(define_insn "xxeval"
+  [(set (match_operand:V2DI 0 "vsx_register_operand" "=wa")
+	(unspec:V2DI [(match_operand:V2DI 1 "vsx_register_operand" "wa")
+		      (match_operand:V2DI 2 "vsx_register_operand" "wa")
+		      (match_operand:V2DI 3 "vsx_register_operand" "wa")
+		      (match_operand:QI 4 "u8bit_cint_operand" "n")]
+		     UNSPEC_XXEVAL))]
+   "TARGET_POWER10"
+   "xxeval %0,%1,%2,%3,%4"
+   [(set_attr "type" "vecperm")
+    (set_attr "prefixed" "yes")])