From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1984) id 71A503893668; Fri, 16 Apr 2021 16:08:18 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 71A503893668 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Tamar Christina To: gcc-cvs@gcc.gnu.org Subject: [gcc r10-9708] SVE: Fix wrong sve predicate split (PR100048) X-Act-Checkin: gcc X-Git-Author: Tamar Christina X-Git-Refname: refs/heads/releases/gcc-10 X-Git-Oldrev: 088c0b5ccf8b670efc25bcbea722c86c8d1faadc X-Git-Newrev: d15a2a00a384672c5f8228d49eba2b0c09048a43 Message-Id: <20210416160818.71A503893668@sourceware.org> Date: Fri, 16 Apr 2021 16:08:18 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 16 Apr 2021 16:08:18 -0000 https://gcc.gnu.org/g:d15a2a00a384672c5f8228d49eba2b0c09048a43 commit r10-9708-gd15a2a00a384672c5f8228d49eba2b0c09048a43 Author: Tamar Christina Date: Fri Apr 16 16:58:50 2021 +0100 SVE: Fix wrong sve predicate split (PR100048) The attached testcase generates the following paradoxical subregs when creating the predicates. (insn 22 21 23 2 (set (reg:VNx8BI 100) (subreg:VNx8BI (reg:VNx2BI 103) 0)) (expr_list:REG_EQUAL (const_vector:VNx8BI [ (const_int 1 [0x1]) (const_int 0 [0]) (const_int 1 [0x1]) (const_int 0 [0]) repeated x5 ]) (nil))) and (insn 15 14 16 2 (set (reg:VNx8BI 96) (subreg:VNx8BI (reg:VNx2BI 99) 0)) (expr_list:REG_EQUAL (const_vector:VNx8BI [ (const_int 1 [0x1]) (const_int 0 [0]) repeated x7 ]) (nil))) This causes CSE to incorrectly think that the two predicates are equal because some of the significant bits get ignored due to the subreg. The attached patch instead makes it so it always looks at all 16-bits of the predicate, but in turn means we need to generate a TRN that matches the expected result mode. In effect in RTL we keep the mode as VNx16BI but during codegen re-interpret them as the mode the predicate instruction wanted: (insn 10 9 11 2 (set (reg:VNx8BI 96) (subreg:VNx8BI (reg:VNx16BI 99) 0)) (expr_list:REG_EQUAL (const_vector:VNx8BI [ (const_int 1 [0x1]) (const_int 0 [0]) repeated x7 ]) (nil))) Which needed correction to the TRN pattern. A new TRN1_CONV unspec is introduced which allows one to keep the arguments as VNx16BI but encode the instruction as a type of the last operand. (insn 9 8 10 2 (set (reg:VNx16BI 99) (unspec:VNx16BI [ (reg:VNx16BI 97) (reg:VNx16BI 98) (reg:VNx2BI 100) ] UNSPEC_TRN1_CONV)) (nil)) This allows us remove all the paradoxical subregs and end up with (insn 16 15 17 2 (set (reg:VNx8BI 101) (subreg:VNx8BI (reg:VNx16BI 104) 0)) (expr_list:REG_EQUAL (const_vector:VNx8BI [ (const_int 1 [0x1]) (const_int 0 [0]) (const_int 1 [0x1]) (const_int 0 [0]) repeated x5 ]) (nil))) gcc/ChangeLog: PR target/100048 * config/aarch64/aarch64-sve.md (@aarch64_sve_trn1_conv): New. * config/aarch64/aarch64.c (aarch64_expand_sve_const_pred_trn): Use new TRN optab. * config/aarch64/iterators.md (UNSPEC_TRN1_CONV): New. gcc/testsuite/ChangeLog: PR target/100048 * gcc.target/aarch64/sve/pr100048.c: New test. (cherry picked from commit 8535755af70f819d820553b2e73e72a16a984599) Diff: --- gcc/config/aarch64/aarch64-sve.md | 14 ++++++++++++++ gcc/config/aarch64/aarch64.c | 10 +++++----- gcc/config/aarch64/iterators.md | 1 + gcc/testsuite/gcc.target/aarch64/sve/pr100048.c | 25 +++++++++++++++++++++++++ 4 files changed, 45 insertions(+), 5 deletions(-) diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md index d17a7770690..bd51323e57d 100644 --- a/gcc/config/aarch64/aarch64-sve.md +++ b/gcc/config/aarch64/aarch64-sve.md @@ -8455,6 +8455,20 @@ "\t%0., %1., %2." ) +;; Special purpose permute used by the predicate generation instructions. +;; Unlike the normal permute patterns, these instructions operate on VNx16BI +;; regardless of the element size, so that all input and output bits are +;; well-defined. Operand 3 then indicates the size of the permute. +(define_insn "@aarch64_sve_trn1_conv" + [(set (match_operand:VNx16BI 0 "register_operand" "=Upa") + (unspec:VNx16BI [(match_operand:VNx16BI 1 "register_operand" "Upa") + (match_operand:VNx16BI 2 "register_operand" "Upa") + (match_operand:PRED_ALL 3 "aarch64_simd_imm_zero")] + UNSPEC_TRN1_CONV))] + "TARGET_SVE" + "trn1\t%0., %1., %2." +) + ;; ========================================================================= ;; == Conversions ;; ========================================================================= diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 9b400c49ac6..688f6986741 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -5067,12 +5067,12 @@ aarch64_expand_sve_const_pred_trn (rtx target, rtx_vector_builder &builder, } } - /* Emit the TRN1 itself. */ + /* Emit the TRN1 itself. We emit a TRN that operates on VNx16BI + operands but permutes them as though they had mode MODE. */ machine_mode mode = aarch64_sve_pred_mode (permute_size).require (); - target = aarch64_target_reg (target, mode); - emit_insn (gen_aarch64_sve (UNSPEC_TRN1, mode, target, - gen_lowpart (mode, a), - gen_lowpart (mode, b))); + target = aarch64_target_reg (target, GET_MODE (a)); + rtx type_reg = CONST0_RTX (mode); + emit_insn (gen_aarch64_sve_trn1_conv (mode, target, a, b, type_reg)); return target; } diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 0a7145281fa..ff5b23d71b1 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -633,6 +633,7 @@ UNSPEC_UZP2Q ; Used in aarch64-sve.md. UNSPEC_ZIP1Q ; Used in aarch64-sve.md. UNSPEC_ZIP2Q ; Used in aarch64-sve.md. + UNSPEC_TRN1_CONV ; Used in aarch64-sve.md. UNSPEC_COND_CMPEQ_WIDE ; Used in aarch64-sve.md. UNSPEC_COND_CMPGE_WIDE ; Used in aarch64-sve.md. UNSPEC_COND_CMPGT_WIDE ; Used in aarch64-sve.md. diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr100048.c b/gcc/testsuite/gcc.target/aarch64/sve/pr100048.c new file mode 100644 index 00000000000..525933863f7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/pr100048.c @@ -0,0 +1,25 @@ +/* { dg-additional-options "-O2 -fno-schedule-insns" } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "arm_sve.h" + +/* +** foo: +** ptrue (p[0-7])\.d, all +** pfalse (p[0-7])\.b +** ptrue (p[0-7])\.s, all +** trn1 (p[0-7])\.d, \2\.d, \3\.d +** trn1 \2\.d, \1\.d, \3\.d +** faddv (h[0-31]), \4\, (z[0-31]).h +** faddv (h[0-31]), \2\, \6\.h +** str \5, [x0] +** str \7, [x0, 2] +** ret +*/ +void foo(svfloat16_t in, float16_t *dst) { + const svbool_t pg_q0 = svdupq_n_b16(1, 0, 1, 0, 0, 0, 0, 0); + const svbool_t pg_f0 = svdupq_n_b16(1, 0, 0, 0, 0, 0, 0, 0); + dst[0] = svaddv_f16(pg_f0, in); + dst[1] = svaddv_f16(pg_q0, in); +} +