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From: Michael Meissner <meissner@gcc.gnu.org>
To: gcc-cvs@gcc.gnu.org
Subject: [gcc(refs/users/meissner/heads/work048)] Revert patch.
Date: Mon, 19 Apr 2021 15:31:32 +0000 (GMT) [thread overview]
Message-ID: <20210419153132.CD0A7385E013@sourceware.org> (raw)
https://gcc.gnu.org/g:dea3e1ae50dbb42a1f340edf38448ba1441c3b1d
commit dea3e1ae50dbb42a1f340edf38448ba1441c3b1d
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Mon Apr 19 11:31:01 2021 -0400
Revert patch.
gcc/
2021-04-15 Michael Meissner <meissner@linux.ibm.com>
Revert patch.
* config/rs6000/altivec.md (UNSPEC_XXBLEND): Move to vsx.md.
(VM3): Move to vsx.md and rename to VBLEND.
(VM3_char): Move to vsx.md and rename to VBLEND_char.
(xxblend_<mode>): Move to vsx.md.
* config/rs6000/vsx.md (UNSPEC_XXEVAL): Move from altivec.md.
(VBLEND): Move from altivec.md and rename VM3 to VBLEND.
(VBLEND_char): Move from altivec.md and rename VM3_char to
VBLEND_char.
(xxblend_<mode>): Move from altivec.md. Use vsx_register_operand
instead of register operand. Change the insn type from vecsimple
to vecperm.
Diff:
---
gcc/config/rs6000/altivec.md | 27 +++++++++++++++++++++++++++
gcc/config/rs6000/vsx.md | 26 --------------------------
2 files changed, 27 insertions(+), 26 deletions(-)
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index ed79a6b85cd..a1ba10b0275 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -175,6 +175,7 @@
UNSPEC_VSTRIL
UNSPEC_SLDB
UNSPEC_SRDB
+ UNSPEC_XXBLEND
])
(define_c_enum "unspecv"
@@ -215,6 +216,21 @@
(KF "FLOAT128_VECTOR_P (KFmode)")
(TF "FLOAT128_VECTOR_P (TFmode)")])
+;; Like VM2, just do char, short, int, long, float and double
+(define_mode_iterator VM3 [V4SI
+ V8HI
+ V16QI
+ V4SF
+ V2DF
+ V2DI])
+
+(define_mode_attr VM3_char [(V2DI "d")
+ (V4SI "w")
+ (V8HI "h")
+ (V16QI "b")
+ (V2DF "d")
+ (V4SF "w")])
+
;; Map the Vector convert single precision to double precision for integer
;; versus floating point
(define_mode_attr VS_sxwsp [(V4SI "sxw") (V4SF "sp")])
@@ -799,6 +815,17 @@
"vs<SLDB_lr>dbi %0,%1,%2,%3"
[(set_attr "type" "vecsimple")])
+(define_insn "xxblend_<mode>"
+ [(set (match_operand:VM3 0 "register_operand" "=wa")
+ (unspec:VM3 [(match_operand:VM3 1 "register_operand" "wa")
+ (match_operand:VM3 2 "register_operand" "wa")
+ (match_operand:VM3 3 "register_operand" "wa")]
+ UNSPEC_XXBLEND))]
+ "TARGET_POWER10"
+ "xxblendv<VM3_char> %x0,%x1,%x2,%x3"
+ [(set_attr "type" "vecsimple")
+ (set_attr "prefixed" "yes")])
+
(define_expand "vstrir_<mode>"
[(set (match_operand:VIshort 0 "altivec_register_operand")
(unspec:VIshort [(match_operand:VIshort 1 "altivec_register_operand")]
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index c1e453dd9ff..0e5fb21d234 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -271,19 +271,6 @@
;; and Vector Integer Multiply/Divide/Modulo Instructions
(define_mode_iterator VIlong [V2DI V4SI])
-;; Modes for XXBLEND
-(define_mode_iterator VBLEND [V16QI V8HI V4SI V4SF V2DF V2DI])
-
-;; XXBLEND type
-(define_mode_attr VBLEND_char [(V16QI "b")
- (V8HI "h")
- (V4SI "w")
- (V4SF "w")
- (V2DF "d")
- (V2DI "d")])
-
-
-
;; Constants for creating unspecs
(define_c_enum "unspec"
[UNSPEC_VSX_CONCAT
@@ -387,7 +374,6 @@
UNSPEC_XXSPLTI32DX_CONST
UNSPEC_XXPERMX
UNSPEC_XXEVAL
- UNSPEC_XXBLEND
])
(define_int_iterator XVCVBF16 [UNSPEC_VSX_XVCVSPBF16
@@ -6536,15 +6522,3 @@
"xxeval %0,%1,%2,%3,%4"
[(set_attr "type" "vecperm")
(set_attr "prefixed" "yes")])
-
-;; XXBLEND built-in function support.
-(define_insn "xxblend_<mode>"
- [(set (match_operand:VBLEND 0 "vsx_register_operand" "=wa")
- (unspec:VBLEND [(match_operand:VBLEND 1 "vsx_register_operand" "wa")
- (match_operand:VBLEND 2 "vsx_register_operand" "wa")
- (match_operand:VBLEND 3 "vsx_register_operand" "wa")]
- UNSPEC_XXBLEND))]
- "TARGET_POWER10"
- "xxblendv<Blenc_char> %x0,%x1,%x2,%x3"
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "yes")])
next reply other threads:[~2021-04-19 15:31 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-19 15:31 Michael Meissner [this message]
-- strict thread matches above, loose matches on Subject: below --
2021-04-14 22:33 Michael Meissner
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