From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 70360385E013; Mon, 19 Apr 2021 15:46:47 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 70360385E013 Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work048)] Move XXBLEND from altivec.md to vsx.md. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work048 X-Git-Oldrev: dea3e1ae50dbb42a1f340edf38448ba1441c3b1d X-Git-Newrev: 1fe5886137714af363ad627356f3a144b2415a78 Message-Id: <20210419154647.70360385E013@sourceware.org> Date: Mon, 19 Apr 2021 15:46:47 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 19 Apr 2021 15:46:47 -0000 https://gcc.gnu.org/g:1fe5886137714af363ad627356f3a144b2415a78 commit 1fe5886137714af363ad627356f3a144b2415a78 Author: Michael Meissner Date: Mon Apr 19 11:46:30 2021 -0400 Move XXBLEND from altivec.md to vsx.md. This patch moves the XXBLEND support from altivec.md to vsx.md. Given the instruction support all VSX registers, vsx.md is a more proper place for this instruction. In doing the move, I made changes to make it fit into the vsx.md conventions. I changed the mode iterator from VM3 to VBLEND. I changed the mode attribute from VM3_char to VBLEND_char. I also changed the register_operand to the more specific vsx_register_operand. I was chatting with Pat Haugen, he said that the insn type should be "vecperm" and not "vecsimple", so I changed this as well. gcc/ 2021-04-19 Michael Meissner * config/rs6000/altivec.md (UNSPEC_XXBLEND): Move to vsx.md. (VM3): Move to vsx.md. (VM3_char): Move to vsx.md. (xxblend_): Move to vsx.md. * config/rs6000/vsx.md (UNSPEC_XXEVAL): Move from altivec.md. (VM3): Move from altivec.md. (VM3_char): Move from altivec.md. (xxblend_): Move from altivec.md. Use vsx_register_operand instead of register operand. Change the insn type from vecsimple to vecperm. Diff: --- gcc/config/rs6000/altivec.md | 27 --------------------------- gcc/config/rs6000/vsx.md | 28 ++++++++++++++++++++++++++++ 2 files changed, 28 insertions(+), 27 deletions(-) diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index a1ba10b0275..ed79a6b85cd 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -175,7 +175,6 @@ UNSPEC_VSTRIL UNSPEC_SLDB UNSPEC_SRDB - UNSPEC_XXBLEND ]) (define_c_enum "unspecv" @@ -216,21 +215,6 @@ (KF "FLOAT128_VECTOR_P (KFmode)") (TF "FLOAT128_VECTOR_P (TFmode)")]) -;; Like VM2, just do char, short, int, long, float and double -(define_mode_iterator VM3 [V4SI - V8HI - V16QI - V4SF - V2DF - V2DI]) - -(define_mode_attr VM3_char [(V2DI "d") - (V4SI "w") - (V8HI "h") - (V16QI "b") - (V2DF "d") - (V4SF "w")]) - ;; Map the Vector convert single precision to double precision for integer ;; versus floating point (define_mode_attr VS_sxwsp [(V4SI "sxw") (V4SF "sp")]) @@ -815,17 +799,6 @@ "vsdbi %0,%1,%2,%3" [(set_attr "type" "vecsimple")]) -(define_insn "xxblend_" - [(set (match_operand:VM3 0 "register_operand" "=wa") - (unspec:VM3 [(match_operand:VM3 1 "register_operand" "wa") - (match_operand:VM3 2 "register_operand" "wa") - (match_operand:VM3 3 "register_operand" "wa")] - UNSPEC_XXBLEND))] - "TARGET_POWER10" - "xxblendv %x0,%x1,%x2,%x3" - [(set_attr "type" "vecsimple") - (set_attr "prefixed" "yes")]) - (define_expand "vstrir_" [(set (match_operand:VIshort 0 "altivec_register_operand") (unspec:VIshort [(match_operand:VIshort 1 "altivec_register_operand")] diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 0e5fb21d234..cea155a5d28 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -271,6 +271,21 @@ ;; and Vector Integer Multiply/Divide/Modulo Instructions (define_mode_iterator VIlong [V2DI V4SI]) +;; Like VM2 in altivec.md, just do char, short, int, long, float and double +(define_mode_iterator VM3 [V4SI + V8HI + V16QI + V4SF + V2DF + V2DI]) + +(define_mode_attr VM3_char [(V2DI "d") + (V4SI "w") + (V8HI "h") + (V16QI "b") + (V2DF "d") + (V4SF "w")]) + ;; Constants for creating unspecs (define_c_enum "unspec" [UNSPEC_VSX_CONCAT @@ -374,6 +389,7 @@ UNSPEC_XXSPLTI32DX_CONST UNSPEC_XXPERMX UNSPEC_XXEVAL + UNSPEC_XXBLEND ]) (define_int_iterator XVCVBF16 [UNSPEC_VSX_XVCVSPBF16 @@ -6522,3 +6538,15 @@ "xxeval %0,%1,%2,%3,%4" [(set_attr "type" "vecperm") (set_attr "prefixed" "yes")]) + +;; XXBLEND support. +(define_insn "xxblend_" + [(set (match_operand:VM3 0 "vsx_register_operand" "=wa") + (unspec:VM3 [(match_operand:VM3 1 "vsx_register_operand" "wa") + (match_operand:VM3 2 "vsx_register_operand" "wa") + (match_operand:VM3 3 "vsx_register_operand" "wa")] + UNSPEC_XXBLEND))] + "TARGET_POWER10" + "xxblendv %x0,%x1,%x2,%x3" + [(set_attr "type" "vecperm") + (set_attr "prefixed" "yes")])