[gcc(refs/users/meissner/heads/work049)] Update ChangeLog.meissner.

[Michael Meissner <meissner@gcc.gnu.org>]

https://gcc.gnu.org/g:46e48c8fb5f7e2f84eeab4ea4ba03789afe3db41

commit 46e48c8fb5f7e2f84eeab4ea4ba03789afe3db41
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Tue Apr 20 19:19:39 2021 -0400

    Update ChangeLog.meissner.
    
    gcc/
    2021-04-20  Michael Meissner  <meissner@linux.ibm.com>
    
            * ChangeLog.meissner: Update.
    
    gcc/testsuite/
    2021-04-20  Michael Meissner  <meissner@linux.ibm.com>
    
            * ChangeLog.meissner: Update.
    
    libgcc/
    2021-04-20  Michael Meissner  <meissner@linux.ibm.com>
    
            * ChangeLog.meissner: Update.
    
    gcc/fortran/
    2021-04-20  Michael Meissner  <meissner@linux.ibm.com>
    
            * ChangeLog.meissner: Update.

Diff:
---
 gcc/ChangeLog.meissner           | 214 +++++++++++++++++++++++++++++++++++++++
 gcc/fortran/ChangeLog.meissner   |   9 ++
 gcc/testsuite/ChangeLog.meissner |  64 ++++++++++++
 libgcc/ChangeLog.meissner        |  13 +++
 4 files changed, 300 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 7cf58b4abe3..2f3d5c458b6 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,217 @@
+work049.patch019:
+2021-04-20  Michael Meissner  <meissner@linux.ibm.com>
+
+	* config/rs6000/altivec.md (UNSPEC_XXBLEND): Move to vsx.md.
+	(VM3): Move to vsx.md.
+	(VM3_char): Move to vsx.md.
+	(xxblend_<mode>): Move to vsx.md.
+	* config/rs6000/vsx.md (UNSPEC_XXEVAL): Move from altivec.md.
+	(VM3): Move from altivec.md.
+	(VM3_char): Move from altivec.md.
+	(xxblend_<mode>): Move from altivec.md.  Use vsx_register_operand
+	instead of register operand.  Change the insn type from vecsimple
+	to vecperm.
+
+work049.patch018:
+2021-04-20  Michael Meissner  <meissner@linux.ibm.com>
+
+	* config/rs6000/altivec.md (UNSPEC_XXEVAL): Move to vsx.md.
+	(xxeval): Move to vsx.md.
+	* config/rs6000/vsx.md (UNSPEC_XXEVAL): Move from altivec.md.
+	(xxeval): Move from altivec.md.  Change altivec_register_operand
+	to vsx_register_operand.  Change insn type to vecperm.
+
+work049.patch017:
+2021-04-20  Michael Meissner  <meissner@linux.ibm.com>
+
+	* config/rs6000/altivec.md (UNSPEC_XXPERMX): Move to vsx.md.
+	(xxpermx): Move to vsx.md.
+	(xxpermx_inst): Move to vsx.md.
+	* config/rs6000/vsx.md (UNSPEC_XXPERMX): Move from altivec.md.
+	(xxpermx): Move from altivec.md.  Use vsx_register_operand
+	instead of register_operand.  Remove setting the insn attribute
+	"type" on the expander.
+	(xxpermx_inst): Move from altivec.md.  Use vsx_register_operand
+	instead of register_operand.  Change the constraint from "v" to
+	"wa" to match the instruction.  Change insn type to vecperm.
+
+work049.patch016:
+2021-04-20  Michael Meissner  <meissner@linux.ibm.com>
+
+	* config/rs6000/altivec.me (UNSPEC_XXSPLTI32DX): Move to vsx.md.
+	(xxsplti32dx_v4si): Move to vsx.md.
+	(xxsplti32dx_v4si_inst): Move to vsx.md.
+	(xxsplti32dx_v4sf): Move to vsx.md.
+	(xxsplti32dx_v4sf_inst): Move to vsx.md.
+	* config/rs6000/contraints.md (eD): New constraint.
+	* config/rs6000/predicates.md (easy_fp_constant): If we can load
+	the constant with a pair of XXSPLTI32DX instructions, it is easy.
+	(xxsplti32dx_operand): New predicate.
+	(easy_vector_constant): If we can load the constant with a pair of
+	XXSPLTI32DX instructions, it is easy.
+	* config/rs6000/rs6000-cpus.def (OTHER_POWER10_MASKS): Add
+	-mxxsplti32dx.
+	(POWERPC_MASKS): Add -mxxsplti32dx.
+	* config/rs6000/rs6000-protos.h (xxsplti32dx_constant_p): New
+	declaration.
+	* config/rs6000/rs6000.c (rs6000_option_override_internal): Add
+	-mxxsplti32dx support.
+	(xxsplti32dx_constant_p): New helper function.
+	(output_vec_const_move): Split constants that need XXSPLTI32DX.
+	(rs6000_opt_masks): Add -mxxsplti32dx.
+	* config/rs6000/rs6000.md (movsf_hardfloat): Add support for
+	loading constants with XXSPLTI32DX.
+	(mov<mode>_hardfloat32, FMOVE64 iterator): Add support for loading
+	constants with XXSPLTI32DX.
+	(mov<mode>_hardfloat64, FMOVE64 iterator): Add support for loading
+	constants with XXSPLTI32DX.
+	* config/rs6000/rs6000.opt (-mxxsplti32dx): New switch.
+	* config/rs6000/vsx.md (UNSPEC_XXSPLTI32DX): Move unspec here from
+	altivec.md.
+	(UNSPEC_XXSPLTI32DX_CONST): New unspec.
+	(vsx_mov<mode>_64bit): Bump up size of 'W' vector constants to
+	accomidate a pair of XXSPLTI32DX instructions.
+	(vsx_mov<mode>_32bit): Bump up size of 'W' vector constants to
+	accomidate a pair of XXSPLTI32DX instructions.
+	(XXSPLTI32DX): New mode iterator.
+	(xxsplti32dx_<mode>): New insn and splits.
+	(xxsplti32dx_<mode>_first): New insns.
+	(xxsplti32dx_<mode>_second): New insns.
+	(xxsplti32dx_v4si): Move here from altivec.md.
+	(xxsplti32dx_v4si_inst): Move here from altivec.md.
+	(xxsplti32dx_v4sf): Move here from altivec.md.
+	(xxsplti32dx_v4sf_inst): Move here from altivec.md.
+
+work049.patch014:
+2021-04-20  Michael Meissner  <meissner@linux.ibm.com>
+
+	* config/rs6000/altivec.md (UNSPEC_XXSPLTID): Move to vsx.md and
+	rename to UNSPEC_XXSPLTID.
+	(xxspltidp_v2df): Move to vsx.md and re-implement.
+	(xxspltidp_v2df_inst): Move to vsx.md and re-implement.
+	* config/rs6000/constraints.md (eF): New constraint.
+	* config/rs6000/predicates.md (easy_fp_constant): If we can load
+	the scalar constant with XXSPLTIDP, return true.
+	(xxspltidp_operand): New predicate.
+	(easy_vector_constant): If we can generate XXSPLTIDP, mark the
+	vector constant as easy.
+	* config/rs6000/rs6000-cpus.def (OTHER_POWER10_MASKS): Add
+	-mxxspltidp support.
+	(POWERPC_MASKS): Add -mxxspltidp support.
+	* config/rs6000/rs6000-protos.h (xxspltidp_constant_p): New
+	declaration.
+	* config/rs6000/rs6000.c (rs6000_option_override_internal): Add
+	-mxxspltidp support.
+	(xxspltidp_constant_p): New function.
+	(output_vec_const_move): Add support for XXSPLTIDP.
+	(rs6000_opt_masks): Add -mxxspltidp support.
+	(rs6000_emit_xxspltidp_v2df): Change function to implement the
+	XXSPLTIDP instruction.
+	* config/rs6000/rs6000.md (movsf_hardfloat): Add XXSPLTIDP
+	support.
+	(mov<mode>_hardfloat32, FMOVE64 iterator): Add XXSPLTIDP support.
+	(mov<mode>_hardfloat64, FMOVE64 iterator): Add XXSPLTIDP support.
+	* config/rs6000/rs6000.opt (-mxxspltidp): New switch.
+	* config/rs6000/vsx.md (UNSPEC_XXSPLTIDP): Move here from
+	altivec.md.  Rename it to UNSPEC_XXSPLTIDP to match the
+	instruction.
+	(XXSPLTIDP): New mode iterator.
+	(xxspltidp_<mode>_internal1): New define_insn_and_split.
+	(xxspltidp_<mode>_internal2): New define_insn.
+	(xxspltidp_v2df): Move to vsx.md from altivec.md.  Re-implement to
+	use the new constant format.
+
+work049.patch012:
+2021-04-20  Michael Meissner  <meissner@linux.ibm.com>
+
+	* config/rs6000/altivec.md (UNSPEC_XXSPLTIW): Delete.
+	(xxspltiw_v4si): Move to vsx.md and rewrite.
+	(xxspltiw_v4sf): Move to vsx.md and rewrite.
+	(xxspltiw_v4sf_inst): Delete.
+	* config/rs6000/predicates.md (xxspltiw_operand): New predicate.
+	(easy_vector_constant): If we can use XXSPLTIW, the vector
+	constant is easy.
+	* config/rs6000/rs6000-cpus.def (ISA_3_1_MASKS_SERVER): Add
+	-mxxspltiw support.
+	(POWERPC_MASKS): Add -mxxspltiw support.
+	* config/rs6000/rs6000.c (rs6000_option_override_internal): Add
+	-mxxspltiw support.
+	(xxspltib_constant_p): If we can generate XXSPLTIW, don't generate
+	a XXSPLTIB and an extend instruction.
+	(output_vec_const_move): Add support for XXSPLTIW vector
+	constants.
+	(rs6000_opt_masks): Add -mxxspltiw.
+	* config/rs6000/rs6000.opt (-mxxspltiw): New debug switch.
+	* config/rs6000/vsx.md (xxspltiw_v8hi): New insn.
+	(xxspltiw_v4si): Move from altivec.md and reimplement to use
+	VEC_DUPLICATE.
+	(xxspltiw_v4sf): Move from altivec.md and reimplement to use
+	VEC_DUPLICATE.
+	(XXSPLTIW): New mode iterator.
+	(XXSPLTIW splitter): New insn splitter for XXSPLTIW.
+
+work049.patch011:
+2021-04-20  Michael Meissner  <meissner@linux.ibm.com>
+
+	* config.gcc (powerpc*-*-*, rs6000-*-*): Do not set
+	LINK_OS_EXTRA_SPEC664 for the Advance Toolchain.  Continue to set
+	LINK_OS_EXTRA_SPEC32.
+
+work049.patch009:
+2021-04-20  Michael Meissner  <meissner@linux.ibm.com>
+
+	* config/rs6000/rs6000-protos.h (rs6000_const_f32_to_i32): Change
+	return type to long.
+	* config/rs6000/rs6000.c (rs6000_const_f32_to_i32): Change return
+	type to long.
+
+work049.patch007:
+2021-04-20  Michael Meissner  <meissner@linux.ibm.com>
+
+	* config/rs6000/rs6000-builtin.def (BU_IBM128_2): Rename
+	RS6000_BTM_IBM128 from RS6000_BTM_FLOAT128.
+	* config/rs6000/rs6000-call.c (rs6000_invalid_builtin): Update
+	error message for __ibm128 built-in functions.
+	(rs6000_init_builtins): Create the __ibm128 keyword on older
+	systems where long double uses the IBM extended double format,
+	even if they don't support IEEE 128-bit floating point.
+	* config/rs6000/rs6000.c (rs6000_builtin_mask_calculate): Rename
+	RS6000_BTM_IBM128 from RS6000_BTM_FLOAT128.
+	(rs6000_builtin_mask_names): Rename RS6000_BTM_IBM128 from
+	RS6000_BTM_FLOAT128.
+	* config/rs6000/rs6000.h (TARGET_IBM128): New macro.
+	(RS6000_BTM_IBM128): Rename from RS6000_BTM_FLOAT128.
+	(RS6000_BTM_COMMON): Rename RS6000_BTM_IBM128 from
+	RS6000_BTM_FLOAT128.
+
+work049.patch006:
+2021-04-20  Michael Meissner  <meissner@linux.ibm.com>
+
+	* config/rs6000/rs6000-c.c (rs6000_cpu_cpp_builtins): If long
+	double is IEEE-128 map the nanq built-in functions to the long
+	double function, not the f128 function.
+
+work049.patch002:
+2021-04-20 Michael Meissner  <meissner@linux.ibm.com>
+
+        * config/rs6000/rs6000.c (rs6000_maybe_emit_fp_cmove): Add IEEE
+	128-bit floating point conditional move support.
+	(have_compare_and_set_mask): Add IEEE 128-bit floating point
+	types.
+	* config/rs6000/rs6000.md (mov<mode>cc, IEEE128 iterator): New insn.
+	(mov<mode>cc_p10, IEEE128 iterator): New insn.
+	(mov<mode>cc_invert_p10, IEEE128 iterator): New insn.
+	(fpmask<mode>, IEEE128 iterator): New insn.
+	(xxsel<mode>, IEEE128 iterator): New insn.
+
+work049.patch001:
+2021-04-20  Michael Meissner  <meissner@linux.ibm.com>
+
+	* config/rs6000/rs6000.c (rs6000_emit_minmax): Add support for ISA
+	3.1 IEEE 128-bit floating point xsmaxcqp and xsmincqp instructions.
+	* config/rs6000/rs6000.md (s<minmax><mode>3, IEEE128 iterator):
+	New insns.
+
 2021-04-20   Michael Meissner  <meissner@linux.ibm.com>
 
 	Clone branch
diff --git a/gcc/fortran/ChangeLog.meissner b/gcc/fortran/ChangeLog.meissner
index 7cf58b4abe3..52a03e37654 100644
--- a/gcc/fortran/ChangeLog.meissner
+++ b/gcc/fortran/ChangeLog.meissner
@@ -1,3 +1,12 @@
+work049.patch020:
+2021-04-20  Michael Meissner  <meissner@linux.ibm.com>
+
+	PR gfortran/96983
+	* trans-intrinsic.c (build_round_expr): If int type is larger than
+	long long, do the round and convert to the integer type.  Do not
+	try to find a floating point type the exact size of the integer
+	type.
+
 2021-04-20   Michael Meissner  <meissner@linux.ibm.com>
 
 	Clone branch
diff --git a/gcc/testsuite/ChangeLog.meissner b/gcc/testsuite/ChangeLog.meissner
index 7cf58b4abe3..d16967a8fc0 100644
--- a/gcc/testsuite/ChangeLog.meissner
+++ b/gcc/testsuite/ChangeLog.meissner
@@ -1,3 +1,67 @@
+work049.patch016:
+2021-04-20  Michael Meissner  <meissner@linux.ibm.com>
+
+	* gcc.target/powerpc/vec-splati-runnable.c: Update insn count.
+	* gcc.target/powerpc/vec-splat-constant-sf.c: Update insn count.
+	* gcc.target/powerpc/vec-splat-constant-df.c: Update insn count.
+	* gcc.target/powerpc/vec-splat-constant-v2df.c: Update insn
+	count.
+
+work049.patch015:
+2021-04-20  Michael Meissner  <meissner@linux.ibm.com>
+
+	* gcc.target/powerpc/vec-splat-constant-sf.c: New test.
+	* gcc.target/powerpc/vec-splat-constant-df.c: New test.
+	* gcc.target/powerpc/vec-splat-constant-v2df.c: New test.
+
+work049.patch013:
+2021-04-20  Michael Meissner  <meissner@linux.ibm.com>
+
+	* gcc.target/powerpc/vec-splati-runnable.c: Set optimization level
+	to -O2.  Add missing abort call.  Update insn counts.
+	* gcc.target/powerpc/vec-splat-constant-v4sf.c: New test.
+	* gcc.target/powerpc/vec-splat-constant-v4si.c: New test.
+	* gcc.target/powerpc/vec-splat-constant-v8hi.c: New test.
+
+work049.patch005:
+2021-04-20  Michael Meissner  <meissner@linux.ibm.com>
+
+	* c-c++-common/dfp/convert-bfp-11.c: Force using IBM 128-bit long
+	double.  Remove check for 64-bit long double.
+
+work049.patch004:
+2021-04-20  Michael Meissner  <meissner@linux.ibm.com>
+
+	PR target/70117
+	* gcc.target/powerpc/pr70117.c: Force the long double type to use
+	the IBM 128-bit format.
+
+work049.patch003:
+2021-04-20  Michael Meissner  <meissner@linux.ibm.com>
+
+	* lib/target-supports.exp
+	(add_options_for_ppc_long_double_override_ibm128): New function.
+	(check_effective_target_ppc_long_double_override_ibm128): New
+	function.
+	(add_options_for_ppc_long_double_override_ieee128): New function.
+	(check_effective_target_ppc_long_double_override_ieee128): New
+	function.
+	(add_options_for_ppc_long_double_override_64bit): New function.
+	(check_effective_target_ppc_long_double_override_64bit): New
+	function.
+
+work049.patch002:
+2021-04-20  Michael Meissner  <meissner@linux.ibm.com>
+
+        * gcc.target/powerpc/float128-cmove.c: New test.
+        * gcc.target/powerpc/float128-minmax-3.c: New test.
+
+work049.patch001:
+2021-04-20  Michael Meissner  <meissner@linux.ibm.com>
+
+	* gcc.target/powerpc/float128-minmax-2.c: New test.
+
+
 2021-04-20   Michael Meissner  <meissner@linux.ibm.com>
 
 	Clone branch
diff --git a/libgcc/ChangeLog.meissner b/libgcc/ChangeLog.meissner
index 7cf58b4abe3..debfe30ac9e 100644
--- a/libgcc/ChangeLog.meissner
+++ b/libgcc/ChangeLog.meissner
@@ -1,3 +1,16 @@
+work049.patch010:
+2021-04-20  Michael Meissner  <meissner@linux.ibm.com>
+
+	PR target/98952
+	* config/rs6000/tramp.S (__trampoline_setup): Fix trampoline size
+	comparison in 32-bit.
+
+work049.patch008:
+2021-04-20  Michael Meissner  <meissner@linux.ibm.com>
+
+	* config/rs6000/ibm-ldouble.c (pack_ldouble): Use
+	__builtin_pack_ibm128 instead of __builtin_pack_longdouble.
+
 2021-04-20   Michael Meissner  <meissner@linux.ibm.com>
 
 	Clone branch