From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1652) id 29281396B414; Wed, 21 Apr 2021 13:44:15 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 29281396B414 Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Christophe Lyon To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/clyon/heads/mve-autovec)] arm: Auto-vectorization for MVE: vld2/vst2 X-Act-Checkin: gcc X-Git-Author: Christophe Lyon X-Git-Refname: refs/users/clyon/heads/mve-autovec X-Git-Oldrev: d8a3a747bc45d6942473f48c3d835089d050726c X-Git-Newrev: c3dc4028124960d6766ae47af3240ce75139ea1a Message-Id: <20210421134415.29281396B414@sourceware.org> Date: Wed, 21 Apr 2021 13:44:15 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 21 Apr 2021 13:44:15 -0000 https://gcc.gnu.org/g:c3dc4028124960d6766ae47af3240ce75139ea1a commit c3dc4028124960d6766ae47af3240ce75139ea1a Author: Christophe Lyon Date: Mon Mar 8 12:23:49 2021 +0000 arm: Auto-vectorization for MVE: vld2/vst2 This patch enables MVE vld2/vst2 instructions for auto-vectorization. We move the existing expanders from neon.md and enable them for MVE, calling the respective emitter. 2021-03-12 Christophe Lyon gcc/ * config/arm/neon.md (vec_load_lanesoi) (vec_store_lanesoi): Move ... * config/arm/vec-common.md: here. gcc/testsuite/ * gcc.target/arm/simd/mve-vld2.c: New test, derived from slp-perm-2.c Diff: --- gcc/config/arm/neon.md | 14 --------- gcc/config/arm/vec-common.md | 27 +++++++++++++++++ gcc/testsuite/gcc.target/arm/simd/mve-vld2.c | 44 ++++++++++++++++++++++++++++ 3 files changed, 71 insertions(+), 14 deletions(-) diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index 6660846bd57..bc8775c1968 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -5063,13 +5063,6 @@ if (BYTES_BIG_ENDIAN) (const_string "neon_load2_2reg")))] ) -(define_expand "vec_load_lanesoi" - [(set (match_operand:OI 0 "s_register_operand") - (unspec:OI [(match_operand:OI 1 "neon_struct_operand") - (unspec:VQ2 [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] - UNSPEC_VLD2))] - "TARGET_NEON") - (define_insn "neon_vld2" [(set (match_operand:OI 0 "s_register_operand" "=w") (unspec:OI [(match_operand:OI 1 "neon_struct_operand" "Um") @@ -5197,13 +5190,6 @@ if (BYTES_BIG_ENDIAN) (const_string "neon_store2_one_lane")))] ) -(define_expand "vec_store_lanesoi" - [(set (match_operand:OI 0 "neon_struct_operand") - (unspec:OI [(match_operand:OI 1 "s_register_operand") - (unspec:VQ2 [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] - UNSPEC_VST2))] - "TARGET_NEON") - (define_insn "neon_vst2" [(set (match_operand:OI 0 "neon_struct_operand" "=Um") (unspec:OI [(match_operand:OI 1 "s_register_operand" "w") diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md index 6805568532c..c6212d690b8 100644 --- a/gcc/config/arm/vec-common.md +++ b/gcc/config/arm/vec-common.md @@ -457,6 +457,33 @@ } else gcc_unreachable (); + DONE; +}) +(define_expand "vec_load_lanesoi" + [(set (match_operand:OI 0 "s_register_operand") + (unspec:OI [(match_operand:OI 1 "neon_struct_operand") + (unspec:VQ2 [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_VLD2))] + "TARGET_NEON || TARGET_HAVE_MVE" +{ + if (TARGET_NEON) + emit_insn (gen_neon_vld2 (operands[0], operands[1])); + else + emit_insn (gen_mve_vld2q (operands[0], operands[1])); + DONE; +}) + +(define_expand "vec_store_lanesoi" + [(set (match_operand:OI 0 "neon_struct_operand") + (unspec:OI [(match_operand:OI 1 "s_register_operand") + (unspec:VQ2 [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_VST2))] + "TARGET_NEON || TARGET_HAVE_MVE" +{ + if (TARGET_NEON) + emit_insn (gen_neon_vst2 (operands[0], operands[1])); + else + emit_insn (gen_mve_vst2q (operands[0], operands[1])); DONE; }) diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-vld2.c b/gcc/testsuite/gcc.target/arm/simd/mve-vld2.c new file mode 100644 index 00000000000..9778588f9e9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/mve-vld2.c @@ -0,0 +1,44 @@ +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O3" } */ + +#include + +#define M00 100 +#define M10 216 +#define M01 1322 +#define M11 13 + +#define N 128 + +#define FUNC(SIGN, TYPE, BITS) \ + void foo_##SIGN##BITS##x (TYPE##BITS##_t *__restrict__ pInput, \ + TYPE##BITS##_t *__restrict__ pOutput) \ + { \ + unsigned int i; \ + TYPE##BITS##_t a, b; \ + \ + for (i = 0; i < N / BITS; i++) \ + { \ + a = *pInput++; \ + b = *pInput++; \ + \ + *pOutput++ = M00 * a + M01 * b; \ + *pOutput++ = M10 * a + M11 * b; \ + } \ + } + +FUNC(s, int, 8) +FUNC(u, uint, 8) +FUNC(s, int, 16) +FUNC(u, uint, 16) +FUNC(s, int, 32) +FUNC(u, uint, 32) + +/* { dg-final { scan-assembler-times {vld2[01].8\t.q[0-9]+, q[0-9]+., } 4 } } */ +/* { dg-final { scan-assembler-times {vld2[01].16\t.q[0-9]+, q[0-9]+., } 4 } } */ +/* { dg-final { scan-assembler-times {vld2[01].32\t.q[0-9]+, q[0-9]+., } 4 } } */ +/* { dg-final { scan-assembler-times {vst2[01].8\t.q[0-9]+, q[0-9]+., } 4 } } */ +/* { dg-final { scan-assembler-times {vst2[01].16\t.q[0-9]+, q[0-9]+., } 4 } } */ +/* { dg-final { scan-assembler-times {vst2[01].32\t.q[0-9]+, q[0-9]+., } 4 } } */