From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1652) id 5C7FE3987C3D; Wed, 21 Apr 2021 13:47:27 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 5C7FE3987C3D Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Christophe Lyon To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/clyon/heads/mve-autovec)] arm: Auto-vectorization for MVE: vld4/vst4 X-Act-Checkin: gcc X-Git-Author: Christophe Lyon X-Git-Refname: refs/users/clyon/heads/mve-autovec X-Git-Oldrev: 917fff7d806754e8c0030a35b493b157611856bb X-Git-Newrev: 98571c29b784c703014eee6d5052d389be56f974 Message-Id: <20210421134727.5C7FE3987C3D@sourceware.org> Date: Wed, 21 Apr 2021 13:47:27 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 21 Apr 2021 13:47:27 -0000 https://gcc.gnu.org/g:98571c29b784c703014eee6d5052d389be56f974 commit 98571c29b784c703014eee6d5052d389be56f974 Author: Christophe Lyon Date: Thu Mar 11 11:08:49 2021 +0000 arm: Auto-vectorization for MVE: vld4/vst4 This patch enables MVE vld4/vst4 instructions for auto-vectorization. We move the existing expanders from neon.md and enable them for MVE, calling the respective emitter. 2021-03-12 Christophe Lyon gcc/ * config/arm/neon.md (vec_load_lanesxi) (vec_store_lanexoi): Move ... * config/arm/vec-common.md: here. gcc/testsuite/ * gcc.target/arm/simd/mve-vld4.c: New test, derived from slp-perm-3.c Diff: --- gcc/config/arm/neon.md | 20 --------- gcc/config/arm/vec-common.md | 26 ++++++++++++ gcc/testsuite/gcc.target/arm/simd/mve-vld4.c | 61 ++++++++++++++++++++++++++++ 3 files changed, 87 insertions(+), 20 deletions(-) diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index bc8775c1968..fb58baf9e94 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -5617,16 +5617,6 @@ if (BYTES_BIG_ENDIAN) (const_string "neon_load4_4reg")))] ) -(define_expand "vec_load_lanesxi" - [(match_operand:XI 0 "s_register_operand") - (match_operand:XI 1 "neon_struct_operand") - (unspec:VQ2 [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] - "TARGET_NEON" -{ - emit_insn (gen_neon_vld4 (operands[0], operands[1])); - DONE; -}) - (define_expand "neon_vld4" [(match_operand:XI 0 "s_register_operand") (match_operand:XI 1 "neon_struct_operand") @@ -5818,16 +5808,6 @@ if (BYTES_BIG_ENDIAN) (const_string "neon_store4_4reg")))] ) -(define_expand "vec_store_lanesxi" - [(match_operand:XI 0 "neon_struct_operand") - (match_operand:XI 1 "s_register_operand") - (unspec:VQ2 [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] - "TARGET_NEON" -{ - emit_insn (gen_neon_vst4 (operands[0], operands[1])); - DONE; -}) - (define_expand "neon_vst4" [(match_operand:XI 0 "neon_struct_operand") (match_operand:XI 1 "s_register_operand") diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md index 9abc7ed4426..a103ab3a950 100644 --- a/gcc/config/arm/vec-common.md +++ b/gcc/config/arm/vec-common.md @@ -496,3 +496,29 @@ emit_insn (gen_mve_vst2q (operands[0], operands[1])); DONE; }) + +(define_expand "vec_load_lanesxi" + [(match_operand:XI 0 "s_register_operand") + (match_operand:XI 1 "neon_struct_operand") + (unspec:VQ2 [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + "TARGET_NEON || TARGET_HAVE_MVE" +{ + if (TARGET_NEON) + emit_insn (gen_neon_vld4 (operands[0], operands[1])); + else + emit_insn (gen_mve_vld4q (operands[0], operands[1])); + DONE; +}) + +(define_expand "vec_store_lanesxi" + [(match_operand:XI 0 "neon_struct_operand") + (match_operand:XI 1 "s_register_operand") + (unspec:VQ2 [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + "TARGET_NEON || TARGET_HAVE_MVE" +{ + if (TARGET_NEON) + emit_insn (gen_neon_vst4 (operands[0], operands[1])); + else + emit_insn (gen_mve_vst4q (operands[0], operands[1])); + DONE; +}) diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-vld4.c b/gcc/testsuite/gcc.target/arm/simd/mve-vld4.c new file mode 100644 index 00000000000..e86c3aeb1a3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/mve-vld4.c @@ -0,0 +1,61 @@ +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O3" } */ + +#include + +#define M00 100 +#define M10 216 +#define M20 23 +#define M30 237 +#define M01 1322 +#define M11 13 +#define M21 27271 +#define M31 2280 +#define M02 74 +#define M12 191 +#define M22 500 +#define M32 111 +#define M03 134 +#define M13 117 +#define M23 11 +#define M33 771 + +#define N 128 + +#define FUNC(SIGN, TYPE, BITS) \ + void foo_##SIGN##BITS##x (TYPE##BITS##_t *__restrict__ pInput, \ + TYPE##BITS##_t *__restrict__ pOutput) \ + { \ + unsigned int i; \ + TYPE##BITS##_t a, b, c, d; \ + \ + for (i = 0; i < N / BITS; i++) \ + { \ + a = *pInput++; \ + b = *pInput++; \ + c = *pInput++; \ + d = *pInput++; \ + \ + *pOutput++ = M00 * a + M01 * b + M02 * c + M03 * d; \ + *pOutput++ = M10 * a + M11 * b + M12 * c + M13 * d; \ + *pOutput++ = M20 * a + M21 * b + M22 * c + M23 * d; \ + *pOutput++ = M30 * a + M31 * b + M32 * c + M33 * d; \ + } \ + } + +FUNC(s, int, 8) +FUNC(u, uint, 8) +FUNC(s, int, 16) +FUNC(u, uint, 16) +FUNC(s, int, 32) +FUNC(u, uint, 32) + +/* { dg-final { scan-assembler-times {vld4[0123].8\t.q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+., } 8 } } */ +/* { dg-final { scan-assembler-times {vld4[0123].16\t.q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+., } 8 } } */ +/* { dg-final { scan-assembler-times {vld4[0123].32\t.q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+., } 8 } } */ +/* { dg-final { scan-assembler-times {vst4[0123].8\t.q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+., } 8 } } */ +/* { dg-final { scan-assembler-times {vst4[0123].16\t.q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+., } 8 } } */ +/* { dg-final { scan-assembler-times {vst4[0123].32\t.q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+., } 8 } } */ +