From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2153) id 980B53A71C3D; Fri, 23 Apr 2021 10:16:58 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 980B53A71C3D Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Jakub Jelinek To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/vendors/redhat/heads/gcc-8-branch)] AArch64: Add Neoverse N2 tuning model X-Act-Checkin: gcc X-Git-Author: Kyrylo Tkachov X-Git-Refname: refs/vendors/redhat/heads/gcc-8-branch X-Git-Oldrev: f7e00ce5f5b0e63a820cc69fca549857df551ea2 X-Git-Newrev: c25d669bc1486d66c63c3213fb37475f16c25150 Message-Id: <20210423101658.980B53A71C3D@sourceware.org> Date: Fri, 23 Apr 2021 10:16:58 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 23 Apr 2021 10:16:58 -0000 https://gcc.gnu.org/g:c25d669bc1486d66c63c3213fb37475f16c25150 commit c25d669bc1486d66c63c3213fb37475f16c25150 Author: Kyrylo Tkachov Date: Thu Oct 8 15:20:23 2020 +0100 AArch64: Add Neoverse N2 tuning model This is the GCC 8 patch for the Neoverse N2 tuning struct. It sets the AARCH64_EXTRA_TUNE_PREFER_ADVSIMD_AUTOVEC tune flag as well. Bootstrapped and tested on the branch. gcc/ * config/aarch64/aarch64.c (neoversen2_tunings): Define. * config/aarch64/aarch64-cores.def (neoverse-n2): Use it. Diff: --- gcc/config/aarch64/aarch64-cores.def | 2 +- gcc/config/aarch64/aarch64.c | 26 ++++++++++++++++++++++++++ 2 files changed, 27 insertions(+), 1 deletion(-) diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def index 29727fabc2a..dfb839c01cc 100644 --- a/gcc/config/aarch64/aarch64-cores.def +++ b/gcc/config/aarch64/aarch64-cores.def @@ -101,7 +101,7 @@ AARCH64_CORE("zeus", zeus, cortexa57, 8_4A, AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL AARCH64_CORE("neoverse-v1", neoversev1, cortexa57, 8_4A, AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_SVE | AARCH64_FL_RNG, neoversev1, 0x41, 0xd40, -1) /* Armv8.5-A Architecture Processors. */ -AARCH64_CORE("neoverse-n2", neoversen2, cortexa57, 8_4A, AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_F16 | AARCH64_FL_SVE | AARCH64_FL_RNG, cortexa72, 0x41, 0xd49, -1) +AARCH64_CORE("neoverse-n2", neoversen2, cortexa57, 8_4A, AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_F16 | AARCH64_FL_SVE | AARCH64_FL_RNG, neoversen2, 0x41, 0xd49, -1) /* ARMv8-A big.LITTLE implementations. */ diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 3d218b6b951..72c11e35659 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -786,6 +786,32 @@ static const struct tune_params neoversev1_tunings = &generic_prefetch_tune }; +static const struct tune_params neoversen2_tunings = +{ + &cortexa57_extra_costs, + &generic_addrcost_table, + &cortexa57_regmove_cost, + &cortexa57_vector_cost, + &generic_branch_cost, + &generic_approx_modes, + 4, /* memmov_cost */ + 3, /* issue_rate */ + (AARCH64_FUSE_AES_AESMC | AARCH64_FUSE_MOV_MOVK | AARCH64_FUSE_ADRP_ADD + | AARCH64_FUSE_MOVK_MOVK), /* fusible_ops */ + 16, /* function_align. */ + 4, /* jump_align. */ + 8, /* loop_align. */ + 2, /* int_reassoc_width. */ + 4, /* fp_reassoc_width. */ + 1, /* vec_reassoc_width. */ + 2, /* min_div_recip_mul_sf. */ + 2, /* min_div_recip_mul_df. */ + 0, /* max_case_values. */ + tune_params::AUTOPREFETCHER_WEAK, /* autoprefetcher_model. */ + (AARCH64_EXTRA_TUNE_PREFER_ADVSIMD_AUTOVEC), /* tune_flags. */ + &generic_prefetch_tune +}; + static const struct tune_params cortexa73_tunings = { &cortexa57_extra_costs,