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* [gcc(refs/users/meissner/heads/work050)] Update ChangeLog.meissner.
@ 2021-04-29 2:40 Michael Meissner
0 siblings, 0 replies; 6+ messages in thread
From: Michael Meissner @ 2021-04-29 2:40 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:1bf80ace079f831e80f777a972cfd30066264708
commit 1bf80ace079f831e80f777a972cfd30066264708
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Apr 28 22:39:48 2021 -0400
Update ChangeLog.meissner.
gcc/
2021-04-28 Michael Meissner <meissner@linux.ibm.com>
* ChangeLog.meissner: Update.
Diff:
---
gcc/ChangeLog.meissner | 48 ++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 48 insertions(+)
diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index a4423c64bef..9f04a2f5bfe 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,51 @@
+work050.patch12;
+2021-04-28 Michael Meissner <meissner@linux.ibm.com>
+
+ * config/rs6000/vsx.md (xxeval): Use register_predicate instead of
+ altivec_register_predicate.
+
+work050.patch11:
+2021-04-28 Michael Meissner <meissner@linux.ibm.com>
+
+ * config/rs6000/altivec.md (UNSPEC_XXEVAL): Move to vsx.md.
+ (UNSPEC_XXSPLTIW): Move to vsx.md.
+ (UNSPEC_XXSPLTID): Move to vsx.md.
+ (UNSPEC_XXSPLTI32DX): Move to vsx.md.
+ (UNSPEC_XXBLEND): Move to vsx.md.
+ (UNSPEC_XXPERMX): Move to vsx.md.
+ (VM3): Move to vsx.md.
+ (VM3_char): Move to vsx.md.
+ (xxspltiw_v4si): Move to vsx.md.
+ (xxspltiw_v4sf): Move to vsx.md.
+ (xxspltiw_v4sf_inst): Move to vsx.md.
+ (xxspltidp_v2df): Move to vsx.md.
+ (xxspltidp_v2df_inst): Move to vsx.md.
+ (xxsplti32dx_v4si_inst): Move to vsx.md.
+ (xxsplti32dx_v4sf): Move to vsx.md.
+ (xxsplti32dx_v4sf_inst): Move to vsx.md.
+ (xxblend_<mode>): Move to vsx.md.
+ (xxpermx): Move to vsx.md.
+ (xxpermx_inst): Move to vsx.md.
+ * config/rs6000/vsx.md (UNSPEC_XXEVAL): Move from altivec.md.
+ (UNSPEC_XXSPLTIW): Move from altivec.md.
+ (UNSPEC_XXSPLTID): Move from altivec.md.
+ (UNSPEC_XXSPLTI32DX): Move from altivec.md.
+ (UNSPEC_XXBLEND): Move from altivec.md.
+ (UNSPEC_XXPERMX): Move from altivec.md.
+ (VM3): Move from altivec.md.
+ (VM3_char): Move from altivec.md.
+ (xxspltiw_v4si): Move from altivec.md.
+ (xxspltiw_v4sf): Move from altivec.md.
+ (xxspltiw_v4sf_inst): Move from altivec.md.
+ (xxspltidp_v2df): Move from altivec.md.
+ (xxspltidp_v2df_inst): Move from altivec.md.
+ (xxsplti32dx_v4si_inst): Move from altivec.md.
+ (xxsplti32dx_v4sf): Move from altivec.md.
+ (xxsplti32dx_v4sf_inst): Move from altivec.md.
+ (xxblend_<mode>): Move from altivec.md.
+ (xxpermx): Move from altivec.md.
+ (xxpermx_inst): Move from altivec.md.
+
work050.patch10:
2021-04-20 Michael Meissner <meissner@linux.ibm.com>
^ permalink raw reply [flat|nested] 6+ messages in thread
* [gcc(refs/users/meissner/heads/work050)] Update ChangeLog.meissner.
@ 2021-04-29 14:37 Michael Meissner
0 siblings, 0 replies; 6+ messages in thread
From: Michael Meissner @ 2021-04-29 14:37 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:58e04cc6482ce06b502bf349c5bc347dd681784c
commit 58e04cc6482ce06b502bf349c5bc347dd681784c
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Thu Apr 29 10:36:39 2021 -0400
Update ChangeLog.meissner.
gcc/
2021-04-29 Michael Meissner <meissner@linux.ibm.com>
* ChangeLog.meissner: Update.
Diff:
---
gcc/ChangeLog.meissner | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 3f8f51471a3..e5b7342bbfb 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,11 @@
+work050.patch20:
+2021-04-29 Michael Meissner <meissner@linux.ibm.com>
+
+ PR bootstrap/100327
+ * config/rs6000/rs6000.c
+ (TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P): Define.
+ (rs6000_iibgcc_floating_mode_supported_p): New target hook.
+
work050.patch18:
2021-04-28 Michael Meissner <meissner@linux.ibm.com>
^ permalink raw reply [flat|nested] 6+ messages in thread
* [gcc(refs/users/meissner/heads/work050)] Update ChangeLog.meissner.
@ 2021-04-29 4:53 Michael Meissner
0 siblings, 0 replies; 6+ messages in thread
From: Michael Meissner @ 2021-04-29 4:53 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:a99074ac58359080c1fa722f17f4495b08d3efd1
commit a99074ac58359080c1fa722f17f4495b08d3efd1
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Thu Apr 29 00:52:58 2021 -0400
Update ChangeLog.meissner.
gcc/
2021-04-28 Michael Meissner <meissner@linux.ibm.com>
* ChangeLog.meissner: Update.
gcc/testsuite/
2021-04-28 Michael Meissner <meissner@linux.ibm.com>
* ChangeLog.meissner: Update.
Diff:
---
gcc/ChangeLog.meissner | 68 ++++++++++++++++++++++++++++++++++++++++
gcc/testsuite/ChangeLog.meissner | 16 ++++++++++
2 files changed, 84 insertions(+)
diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index d1d832247d8..3f8f51471a3 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,71 @@
+work050.patch18:
+2021-04-28 Michael Meissner <meissner@linux.ibm.com>
+
+ * config/rs6000/constraint.md (eD): New constraint.
+ * config/rs6000/predicates.md (easy_fp_constant): If the constant
+ can be loaded with XXSPLTI32DX, it is easy.
+ (xxsplti32dx_operand): New predicate.
+ (easy_vector_constant): If the constant can be loaded with
+ XXSPLTI32DX, it is easy.
+ * config/rs6000/rs6000-protos.h (xxsplti32dx_constant_p): New
+ declaration.
+ * config/rs6000/rs6000.c (rs6000_option_override_internal): Add
+ support for -mxxsplti32dx.
+ (xxsplti32dx_constant_float_p): New helper function.
+ (xxsplti32dx_constant_p): New function.
+ (output_vec_const_move): If the operand can be loaded with
+ XXSPLTI32DX, split it.
+ (rs6000_opt_masks): Add -mxxsplti32dx.
+ * config/rs6000/rs6000.md (movsf_hardfloat): Add support for
+ constants loaded with XXSPLTI32DX.
+ (mov<mode>_hardfloat32, FMOVE64 iterator): Add support for
+ constants loaded with XXSPLTI32DX.
+ (mov<mode>_hardfloat64, FMOVE64 iterator): Add support for
+ constants loaded with XXSPLTI32DX.
+ * config/rs6000/rs6000.opt (-mxxsplti32dx): New option.
+ * config/rs6000/vsx.md (UNSPEC_XXSPLTI32DX_CONST): New unspec.
+ (XXSPLTI32DX): New mode iterator.
+ (xxsplti32dx_<mode>): New insn and splitter for XXSPLTI32DX.
+ (xxsplti32dx_<mode>_first): New insn.
+ (xxsplti32dx_<mode>_second): New insn.
+
+work050.patch16:
+2021-04-28 Michael Meissner <meissner@linux.ibm.com>
+
+ * config/rs6000/constraints.md (eF): New constraint.
+ * config/rs6000/predicates.md (easy_fp_constant): If we can load
+ the scalar constant with XXSPLTIDP, the floating point constant is
+ easy.
+ (xxspltidp_operand): New predicate.
+ (easy_vector_constant): If we can generate XXSPLTIDP, mark the
+ vector constant as easy.
+ * config/rs6000/rs6000-cpus.def (OTHER_POWER10_MASKS): Add
+ -mxxspltidp support.
+ (POWERPC_MASKS): Add -mxxspltidp support.
+ * config/rs6000/rs6000-protos.h (xxspltidp_constant_p): New
+ declaration.
+ * config/rs6000/rs6000.c (rs6000_option_override_internal): Add
+ -mxxspltidp support.
+ (const_vector_element_all_same): New function.
+ (xxspltidp_constant_p): New function.
+ (output_vec_const_move): Add support for XXSPLTIDP.
+ (rs6000_opt_masks): Add -mxxspltidp support.
+ (rs6000_emit_xxspltidp_v2df): Change function to implement the
+ XXSPLTIDP instruction.
+ * config/rs6000/rs6000.md (movsf_hardfloat): Add XXSPLTIDP
+ support.
+ (mov<mode>_hardfloat32, FMOVE64 iterator): Add XXSPLTIDP support.
+ (mov<mode>_hardfloat64, FMOVE64 iterator): Add XXSPLTIDP support.
+ * config/rs6000/rs6000.opt (-mxxspltidp): New switch.
+ * config/rs6000/vsx.md (UNSPEC_XXSPLTIDP): Rename UNSPEC_XXSPLTID
+ to UNSPEC_XXSPLTIDP to match the instruction.
+ (xxspltidp_v2df): Use 'use' for the expand arguments, instead of
+ writing out an insn.
+ (xxspltidp_v2df_inst): Delete.
+ (XXSPLTIDP): New mode iterator.
+ (xxspltidp_<mode>_internal1): New define_insn_and_split.
+ (xxspltidp_<mode>_internal2): New define_insn.
+
work050.patch14:
2021-04-28 Michael Meissner <meissner@linux.ibm.com>
diff --git a/gcc/testsuite/ChangeLog.meissner b/gcc/testsuite/ChangeLog.meissner
index 4ed38685eca..05696d23512 100644
--- a/gcc/testsuite/ChangeLog.meissner
+++ b/gcc/testsuite/ChangeLog.meissner
@@ -1,3 +1,19 @@
+work050.patch19:
+2021-04-28 Michael Meissner <meissner@linux.ibm.com>
+
+ * gcc.target/powerpc/vec-splati-runnable.c: Update insn count.
+ * gcc.target/powerpc/vec-splat-constant-sf.c: Update insn count.
+ * gcc.target/powerpc/vec-splat-constant-df.c: Update insn count.
+ * gcc.target/powerpc/vec-splat-constant-v2df.c: Update insn
+ count.
+
+work050.patch17:
+2021-04-28 Michael Meissner <meissner@linux.ibm.com>
+
+ * gcc.target/powerpc/vec-splat-constant-sf.c: New test.
+ * gcc.target/powerpc/vec-splat-constant-df.c: New test.
+ * gcc.target/powerpc/vec-splat-constant-v2df.c: New test.
+
work050.patch15:
2021-04-28 Michael Meissner <meissner@linux.ibm.com>
^ permalink raw reply [flat|nested] 6+ messages in thread
* [gcc(refs/users/meissner/heads/work050)] Update ChangeLog.meissner.
@ 2021-04-29 3:33 Michael Meissner
0 siblings, 0 replies; 6+ messages in thread
From: Michael Meissner @ 2021-04-29 3:33 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:84db946e479d735ef7b92a865d9a69dae2981836
commit 84db946e479d735ef7b92a865d9a69dae2981836
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Apr 28 23:33:39 2021 -0400
Update ChangeLog.meissner.
gcc/
2021-04-28 Michael Meissner <meissner@linux.ibm.com>
* ChangeLog.meissner: Update.
gcc/testsuite/
2021-04-28 Michael Meissner <meissner@linux.ibm.com>
* ChangeLog.meissner: Update.
Diff:
---
gcc/ChangeLog.meissner | 24 ++++++++++++++++++++++++
gcc/testsuite/ChangeLog.meissner | 8 ++++++++
2 files changed, 32 insertions(+)
diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 9f04a2f5bfe..d1d832247d8 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,27 @@
+work050.patch14:
+2021-04-28 Michael Meissner <meissner@linux.ibm.com>
+
+ * config/rs6000/predicates.md (xxspltiw_operand): New predicate.
+ (easy_vector_constant): If we can use XXSPLTIW, the vector
+ constant is easy.
+ * config/rs6000/rs6000-cpus.def (ISA_3_1_MASKS_SERVER): Add
+ -mxxspltiw support.
+ (POWERPC_MASKS): Add -mxxspltiw support.
+ * config/rs6000/rs6000.c (rs6000_option_override_internal): Add
+ -mxxspltiw support.
+ (xxspltib_constant_p): If we can generate XXSPLTIW, don't generate
+ a XXSPLTIB and an extend instruction.
+ (output_vec_const_move): Add support for loading up vector
+ constants with XXSPLTIW.
+ (rs6000_opt_masks): Add -mxxspltiw.
+ * config/rs6000/rs6000.opt (-mxxspltiw): New debug switch.
+ * config/rs6000/vsx.md (xxspltiw_v8hi): New insn.
+ (xxspltiw_v4si): Rewrite to use VEC_DUPLICATE.
+ (xxspltiw_v4sf): Rewrite to use VEC_DUPLICATE.
+ (xxspltiw_v4sf_inst): Delete.
+ (XXSPLTIW): New mode iterator.
+ (XXSPLTIW splitter): New insn splitter for XXSPLTIW.
+
work050.patch12;
2021-04-28 Michael Meissner <meissner@linux.ibm.com>
diff --git a/gcc/testsuite/ChangeLog.meissner b/gcc/testsuite/ChangeLog.meissner
index c46ebbc4437..4ed38685eca 100644
--- a/gcc/testsuite/ChangeLog.meissner
+++ b/gcc/testsuite/ChangeLog.meissner
@@ -1,3 +1,11 @@
+work050.patch15:
+2021-04-28 Michael Meissner <meissner@linux.ibm.com>
+
+ * gcc.target/powerpc/vec-splati-runnable.c: Update insn counts.
+ * gcc.target/powerpc/vec-splat-constant-v4sf.c: New test.
+ * gcc.target/powerpc/vec-splat-constant-v4si.c: New test.
+ * gcc.target/powerpc/vec-splat-constant-v8hi.c: New test.
+
work050.patch13:
2021-04-28 Michael Meissner <meissner@linux.ibm.com>
^ permalink raw reply [flat|nested] 6+ messages in thread
* [gcc(refs/users/meissner/heads/work050)] Update ChangeLog.meissner.
@ 2021-04-29 2:50 Michael Meissner
0 siblings, 0 replies; 6+ messages in thread
From: Michael Meissner @ 2021-04-29 2:50 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:7cf5f4a398713dc14c76926d8da212de6e60f87f
commit 7cf5f4a398713dc14c76926d8da212de6e60f87f
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Apr 28 22:50:12 2021 -0400
Update ChangeLog.meissner.
gcc/testsuite/
2021-04-28 Michael Meissner <meissner@linux.ibm.com>
* ChangeLog.meissner: Update.
Diff:
---
gcc/testsuite/ChangeLog.meissner | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/gcc/testsuite/ChangeLog.meissner b/gcc/testsuite/ChangeLog.meissner
index 953df73cba3..c46ebbc4437 100644
--- a/gcc/testsuite/ChangeLog.meissner
+++ b/gcc/testsuite/ChangeLog.meissner
@@ -1,3 +1,9 @@
+work050.patch13:
+2021-04-28 Michael Meissner <meissner@linux.ibm.com>
+
+ * gcc.target/powerpc/vec-splati-runnable.c: Run test with -O2
+ optimization. Add missing abort call in the test.
+
work050.patch05:
2021-04-28 Michael Meissner <meissner@linux.ibm.com>
^ permalink raw reply [flat|nested] 6+ messages in thread
* [gcc(refs/users/meissner/heads/work050)] Update ChangeLog.meissner.
@ 2021-04-29 0:48 Michael Meissner
0 siblings, 0 replies; 6+ messages in thread
From: Michael Meissner @ 2021-04-29 0:48 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:8350fb38b02711775369a8ddaf76b07b5d6daa83
commit 8350fb38b02711775369a8ddaf76b07b5d6daa83
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Apr 28 20:47:51 2021 -0400
Update ChangeLog.meissner.
gcc/
2021-04-28 Michael Meissner <meissner@linux.ibm.com>
* ChangeLog.meissner: Update.
gcc/testsuite/
2021-04-28 Michael Meissner <meissner@linux.ibm.com>
* ChangeLog.meissner: Update.
libgcc/
2021-04-28 Michael Meissner <meissner@linux.ibm.com>
* ChangeLog.meissner: Update.
Diff:
---
gcc/ChangeLog.meissner | 62 ++++++++++++++++++++++++++++++++++++++++
gcc/testsuite/ChangeLog.meissner | 38 ++++++++++++++++++++++++
libgcc/ChangeLog.meissner | 6 ++++
3 files changed, 106 insertions(+)
diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 44fb962dabe..a4423c64bef 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,65 @@
+work050.patch10:
+2021-04-20 Michael Meissner <meissner@linux.ibm.com>
+
+ * config.gcc (powerpc*-*-*, rs6000-*-*): Do not set
+ LINK_OS_EXTRA_SPEC664 for the Advance Toolchain. Continue to set
+ LINK_OS_EXTRA_SPEC32.
+
+work050.patch09:
+2021-04-28 Michael Meissner <meissner@linux.ibm.com>
+
+ * config/rs6000/rs6000-protos.h (rs6000_const_f32_to_i32): Change
+ return type to long.
+ * config/rs6000/rs6000.c (rs6000_const_f32_to_i32): Change return
+ type to long.
+
+work050.patch07:
+2021-04-28 Michael Meissner <meissner@linux.ibm.com>
+
+ * config/rs6000/rs6000-builtin.def (BU_IBM128_2): Rename
+ RS6000_BTM_IBM128 from RS6000_BTM_FLOAT128.
+ * config/rs6000/rs6000-call.c (rs6000_invalid_builtin): Update
+ error message for __ibm128 built-in functions.
+ (rs6000_init_builtins): Create the __ibm128 keyword on older
+ systems where long double uses the IBM extended double format,
+ even if they don't support IEEE 128-bit floating point.
+ * config/rs6000/rs6000.c (rs6000_builtin_mask_calculate): Rename
+ RS6000_BTM_IBM128 from RS6000_BTM_FLOAT128.
+ (rs6000_builtin_mask_names): Rename RS6000_BTM_IBM128 from
+ RS6000_BTM_FLOAT128.
+ * config/rs6000/rs6000.h (TARGET_IBM128): New macro.
+ (RS6000_BTM_IBM128): Rename from RS6000_BTM_FLOAT128.
+ (RS6000_BTM_COMMON): Rename RS6000_BTM_IBM128 from
+ RS6000_BTM_FLOAT128.
+
+work050.patch06:
+2021-04-28 Michael Meissner <meissner@linux.ibm.com>
+
+ * config/rs6000/rs6000-c.c (rs6000_cpu_cpp_builtins): If long
+ double is IEEE-128 map the nanq built-in functions to the long
+ double function, not the f128 function.
+
+work050.patch02:
+2021-04-28 Michael Meissner <meissner@linux.ibm.com>
+
+ * config/rs6000/rs6000.c (rs6000_maybe_emit_fp_cmove): Add IEEE
+ 128-bit floating point conditional move support.
+ (have_compare_and_set_mask): Add IEEE 128-bit floating point
+ types.
+ * config/rs6000/rs6000.md (mov<mode>cc, IEEE128 iterator): New insn.
+ (mov<mode>cc_p10, IEEE128 iterator): New insn.
+ (mov<mode>cc_invert_p10, IEEE128 iterator): New insn.
+ (fpmask<mode>, IEEE128 iterator): New insn.
+ (xxsel<mode>, IEEE128 iterator): New insn.
+
+work050.patch01:
+2021-04-28 Michael Meissner <meissner@linux.ibm.com>
+
+ * config/rs6000/rs6000.c (rs6000_emit_minmax): Add support for ISA
+ 3.1 IEEE 128-bit floating point xsmaxcqp and xsmincqp instructions.
+ * config/rs6000/rs6000.md (s<minmax><mode>3, IEEE128 iterator):
+ New insns.
+
2021-04-28 Michael Meissner <meissner@linux.ibm.com>
Clone branch
diff --git a/gcc/testsuite/ChangeLog.meissner b/gcc/testsuite/ChangeLog.meissner
index 44fb962dabe..953df73cba3 100644
--- a/gcc/testsuite/ChangeLog.meissner
+++ b/gcc/testsuite/ChangeLog.meissner
@@ -1,3 +1,41 @@
+work050.patch05:
+2021-04-28 Michael Meissner <meissner@linux.ibm.com>
+
+ * c-c++-common/dfp/convert-bfp-11.c: Force using IBM 128-bit long
+ double. Remove check for 64-bit long double.
+
+work050.patch04:
+2021-04-28 Michael Meissner <meissner@linux.ibm.com>
+
+ PR target/70117
+ * gcc.target/powerpc/pr70117.c: Force the long double type to use
+ the IBM 128-bit format.
+
+work050.patch03:
+2021-04-28 Michael Meissner <meissner@linux.ibm.com>
+
+ * lib/target-supports.exp
+ (add_options_for_ppc_long_double_override_ibm128): New function.
+ (check_effective_target_ppc_long_double_override_ibm128): New
+ function.
+ (add_options_for_ppc_long_double_override_ieee128): New function.
+ (check_effective_target_ppc_long_double_override_ieee128): New
+ function.
+ (add_options_for_ppc_long_double_override_64bit): New function.
+ (check_effective_target_ppc_long_double_override_64bit): New
+ function.
+
+work050.patch02:
+2021-04-28 Michael Meissner <meissner@linux.ibm.com>
+
+ * gcc.target/powerpc/float128-cmove.c: New test.
+ * gcc.target/powerpc/float128-minmax-3.c: New test.
+
+work050.patch01:
+2021-04-28 Michael Meissner <meissner@linux.ibm.com>
+
+ * gcc.target/powerpc/float128-minmax-2.c: New test.
+
2021-04-28 Michael Meissner <meissner@linux.ibm.com>
Clone branch
diff --git a/libgcc/ChangeLog.meissner b/libgcc/ChangeLog.meissner
index 44fb962dabe..530dc59f41b 100644
--- a/libgcc/ChangeLog.meissner
+++ b/libgcc/ChangeLog.meissner
@@ -1,3 +1,9 @@
+work050.patch08:
+2021-04-28 Michael Meissner <meissner@linux.ibm.com>
+
+ * config/rs6000/ibm-ldouble.c (pack_ldouble): Use
+ __builtin_pack_ibm128 instead of __builtin_pack_longdouble.
+
2021-04-28 Michael Meissner <meissner@linux.ibm.com>
Clone branch
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This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).