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* [gcc(refs/users/meissner/heads/work052)] Update ChangeLog.meissner.
@ 2021-05-05 20:56 Michael Meissner
0 siblings, 0 replies; 2+ messages in thread
From: Michael Meissner @ 2021-05-05 20:56 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:f92859df9ebf6033608dc31211e0a920e87e4822
commit f92859df9ebf6033608dc31211e0a920e87e4822
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed May 5 16:56:05 2021 -0400
Update ChangeLog.meissner.
gcc/testsuite/
2021-05-05 Michael Meissner <meissner@linux.ibm.com>
* ChangeLog.meissner: Update.
Diff:
---
gcc/testsuite/ChangeLog.meissner | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/gcc/testsuite/ChangeLog.meissner b/gcc/testsuite/ChangeLog.meissner
index 55e3d0f2932..932b19db7d1 100644
--- a/gcc/testsuite/ChangeLog.meissner
+++ b/gcc/testsuite/ChangeLog.meissner
@@ -1,3 +1,12 @@
+work052.patch023:
+2021-05-05 Michael Meissner <meissner@linux.ibm.com>
+
+ PR testsuite/100170
+ * gcc.target/powerpc/ppc-eq0-1.c: Adjust insn count if power10
+ code is selected.
+ * gcc.target/powerpc/ppc-ne0-1.c: Turn off power10 code
+ generation.
+
work052.patch022:
2021-05-04 Michael Meissner <meissner@linux.ibm.com>
^ permalink raw reply [flat|nested] 2+ messages in thread
* [gcc(refs/users/meissner/heads/work052)] Update ChangeLog.meissner.
@ 2021-05-04 21:09 Michael Meissner
0 siblings, 0 replies; 2+ messages in thread
From: Michael Meissner @ 2021-05-04 21:09 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:564fbc775aea915f94bd378347ac6497f9469dee
commit 564fbc775aea915f94bd378347ac6497f9469dee
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Tue May 4 17:09:00 2021 -0400
Update ChangeLog.meissner.
gcc/
2021-05-04 Michael Meissner <meissner@linux.ibm.com>
* ChangeLog.meissner: Update.
gcc/testsuite/
2021-05-04 Michael Meissner <meissner@linux.ibm.com>
* ChangeLog.meissner: Update.
libgcc/
2021-05-04 Michael Meissner <meissner@linux.ibm.com>
* ChangeLog.meissner: Update.
Diff:
---
gcc/ChangeLog.meissner | 200 +++++++++++++++++++++++++++++++++++++++
gcc/testsuite/ChangeLog.meissner | 136 ++++++++++++++++++++++++++
libgcc/ChangeLog.meissner | 6 ++
3 files changed, 342 insertions(+)
diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 039fb645663..8376f8ea788 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,203 @@
+work052.patch017:
+2021-05-03 Michael Meissner <meissner@linux.ibm.com>
+
+ * config/rs6000/constraint.md (eD): New constraint.
+ * config/rs6000/predicates.md (easy_fp_constant): If the constant
+ can be loaded with XXSPLTI32DX, it is easy.
+ (xxsplti32dx_operand): New predicate.
+ (easy_vector_constant): If the constant can be loaded with
+ XXSPLTI32DX, it is easy.
+ * config/rs6000/rs6000-protos.h (xxsplti32dx_constant_p): New
+ declaration.
+ * config/rs6000/rs6000.c (rs6000_option_override_internal): Add
+ support for -mxxsplti32dx.
+ (xxsplti32dx_constant_float_p): New helper function.
+ (xxsplti32dx_constant_p): New function.
+ (output_vec_const_move): If the operand can be loaded with
+ XXSPLTI32DX, split it.
+ (rs6000_opt_masks): Add -mxxsplti32dx.
+ * config/rs6000/rs6000.md (movsf_hardfloat): Add support for
+ constants loaded with XXSPLTI32DX.
+ (mov<mode>_hardfloat32, FMOVE64 iterator): Add support for
+ constants loaded with XXSPLTI32DX.
+ (mov<mode>_hardfloat64, FMOVE64 iterator): Add support for
+ constants loaded with XXSPLTI32DX.
+ * config/rs6000/rs6000.opt (-mxxsplti32dx): New option.
+ * config/rs6000/vsx.md (UNSPEC_XXSPLTI32DX_CONST): New unspec.
+ (XXSPLTI32DX): New mode iterator.
+ (xxsplti32dx_<mode>): New insn and splitter for XXSPLTI32DX.
+ (xxsplti32dx_<mode>_first): New insn.
+ (xxsplti32dx_<mode>_second): New insn.
+
+work052.patch015:
+2021-05-03 Michael Meissner <meissner@linux.ibm.com>
+
+ * config/rs6000/constraints.md (eF): New constraint.
+ * config/rs6000/predicates.md (easy_fp_constant): If we can load
+ the scalar constant with XXSPLTIDP, the floating point constant is
+ easy.
+ (xxspltidp_operand): New predicate.
+ (easy_vector_constant): If we can generate XXSPLTIDP, mark the
+ vector constant as easy.
+ * config/rs6000/rs6000-cpus.def (OTHER_POWER10_MASKS): Add
+ -mxxspltidp support.
+ (POWERPC_MASKS): Add -mxxspltidp support.
+ * config/rs6000/rs6000-protos.h (xxspltidp_constant_p): New
+ declaration.
+ * config/rs6000/rs6000.c (rs6000_option_override_internal): Add
+ -mxxspltidp support.
+ (const_vector_element_all_same): New function.
+ (xxspltidp_constant_p): New function.
+ (output_vec_const_move): Add support for XXSPLTIDP.
+ (rs6000_opt_masks): Add -mxxspltidp support.
+ (rs6000_emit_xxspltidp_v2df): Change function to implement the
+ XXSPLTIDP instruction.
+ * config/rs6000/rs6000.md (movsf_hardfloat): Add XXSPLTIDP
+ support.
+ (mov<mode>_hardfloat32, FMOVE64 iterator): Add XXSPLTIDP support.
+ (mov<mode>_hardfloat64, FMOVE64 iterator): Add XXSPLTIDP support.
+ * config/rs6000/rs6000.opt (-mxxspltidp): New switch.
+ * config/rs6000/vsx.md (UNSPEC_XXSPLTIDP): Rename UNSPEC_XXSPLTID
+ to UNSPEC_XXSPLTIDP to match the instruction.
+ (xxspltidp_v2df): Use 'use' for the expand arguments, instead of
+ writing out an insn.
+ (xxspltidp_v2df_inst): Delete.
+ (XXSPLTIDP): New mode iterator.
+ (xxspltidp_<mode>_internal1): New define_insn_and_split.
+ (xxspltidp_<mode>_internal2): New define_insn.
+
+work052.patch013:
+2021-05-03 Michael Meissner <meissner@linux.ibm.com>
+
+ * config/rs6000/predicates.md (xxspltiw_operand): New predicate.
+ (easy_vector_constant): If we can use XXSPLTIW, the vector
+ constant is easy.
+ * config/rs6000/rs6000-cpus.def (ISA_3_1_MASKS_SERVER): Add
+ -mxxspltiw support.
+ (POWERPC_MASKS): Add -mxxspltiw support.
+ * config/rs6000/rs6000.c (rs6000_option_override_internal): Add
+ -mxxspltiw support.
+ (xxspltib_constant_p): If we can generate XXSPLTIW, don't generate
+ a XXSPLTIB and an extend instruction.
+ (output_vec_const_move): Add support for loading up vector
+ constants with XXSPLTIW.
+ (rs6000_opt_masks): Add -mxxspltiw.
+ * config/rs6000/rs6000.opt (-mxxspltiw): New debug switch.
+ * config/rs6000/vsx.md (UNSPEC_XXSPLTIW): Delete.
+ (xxspltiw_v8hi): New insn.
+ (xxspltiw_v4si): Rewrite to generate a vector constant.
+ (xxspltiw_v4sf): Rewrite to generate a vector constant.
+ (xxspltiw_v4si_inst): Delete.
+ (xxspltiw_v4sf_inst): Delete.
+ (xxspltiw_v8hi_dup): New insn.
+ (xxspltiw_v4si_dup): New insn.
+ (xxspltiw_v4sf_dup): New insn.
+ (XXSPLTIW): New mode iterator.
+ (XXSPLTIW splitter): New insn splitter for XXSPLTIW.
+
+work052.patch011:
+2021-05-02 Michael Meissner <meissner@linux.ibm.com>
+
+ * config/rs6000/vsx.md (xxeval): Use register_predicate instead of
+ altivec_register_predicate.
+
+work052.patch010:
+2021-05-02 Michael Meissner <meissner@linux.ibm.com>
+
+ * config/rs6000/altivec.md (UNSPEC_XXEVAL): Move to vsx.md.
+ (UNSPEC_XXSPLTIW): Move to vsx.md.
+ (UNSPEC_XXSPLTID): Move to vsx.md.
+ (UNSPEC_XXSPLTI32DX): Move to vsx.md.
+ (UNSPEC_XXBLEND): Move to vsx.md.
+ (UNSPEC_XXPERMX): Move to vsx.md.
+ (VM3): Move to vsx.md.
+ (VM3_char): Move to vsx.md.
+ (xxspltiw_v4si): Move to vsx.md.
+ (xxspltiw_v4sf): Move to vsx.md.
+ (xxspltiw_v4sf_inst): Move to vsx.md.
+ (xxspltidp_v2df): Move to vsx.md.
+ (xxspltidp_v2df_inst): Move to vsx.md.
+ (xxsplti32dx_v4si_inst): Move to vsx.md.
+ (xxsplti32dx_v4sf): Move to vsx.md.
+ (xxsplti32dx_v4sf_inst): Move to vsx.md.
+ (xxblend_<mode>): Move to vsx.md.
+ (xxpermx): Move to vsx.md.
+ (xxpermx_inst): Move to vsx.md.
+ * config/rs6000/vsx.md (UNSPEC_XXEVAL): Move from altivec.md.
+ (UNSPEC_XXSPLTIW): Move from altivec.md.
+ (UNSPEC_XXSPLTID): Move from altivec.md.
+ (UNSPEC_XXSPLTI32DX): Move from altivec.md.
+ (UNSPEC_XXBLEND): Move from altivec.md.
+ (UNSPEC_XXPERMX): Move from altivec.md.
+ (VM3): Move from altivec.md.
+ (VM3_char): Move from altivec.md.
+ (xxspltiw_v4si): Move from altivec.md.
+ (xxspltiw_v4sf): Move from altivec.md.
+ (xxspltiw_v4sf_inst): Move from altivec.md.
+ (xxspltidp_v2df): Move from altivec.md.
+ (xxspltidp_v2df_inst): Move from altivec.md.
+ (xxsplti32dx_v4si_inst): Move from altivec.md.
+ (xxsplti32dx_v4sf): Move from altivec.md.
+ (xxsplti32dx_v4sf_inst): Move from altivec.md.
+ (xxblend_<mode>): Move from altivec.md.
+ (xxpermx): Move from altivec.md.
+ (xxpermx_inst): Move from altivec.md.
+
+work052.patch009:
+2021-05-02 Michael Meissner <meissner@linux.ibm.com>
+
+ * config.gcc (powerpc*-*-*, rs6000-*-*): Do not set
+ LINK_OS_EXTRA_SPEC664 for the Advance Toolchain. Continue to set
+ LINK_OS_EXTRA_SPEC32.
+
+work052.patch008:
+2021-05-02 Michael Meissner <meissner@linux.ibm.com>
+
+ * config/rs6000/rs6000-protos.h (rs6000_const_f32_to_i32): Change
+ return type to long.
+ * config/rs6000/rs6000.c (rs6000_const_f32_to_i32): Change return
+ type to long.
+
+work052.patch006:
+2021-05-02 Michael Meissner <meissner@linux.ibm.com>
+
+ * config/rs6000/rs6000-builtin.def (BU_IBM128_2): Rename
+ RS6000_BTM_IBM128 from RS6000_BTM_FLOAT128.
+ * config/rs6000/rs6000-call.c (rs6000_invalid_builtin): Update
+ error message for __ibm128 built-in functions.
+ (rs6000_init_builtins): Create the __ibm128 keyword on older
+ systems where long double uses the IBM extended double format,
+ even if they don't support IEEE 128-bit floating point.
+ * config/rs6000/rs6000.c (rs6000_builtin_mask_calculate): Rename
+ RS6000_BTM_IBM128 from RS6000_BTM_FLOAT128.
+ (rs6000_builtin_mask_names): Rename RS6000_BTM_IBM128 from
+ RS6000_BTM_FLOAT128.
+ * config/rs6000/rs6000.h (TARGET_IBM128): New macro.
+ (RS6000_BTM_IBM128): Rename from RS6000_BTM_FLOAT128.
+ (RS6000_BTM_COMMON): Rename RS6000_BTM_IBM128 from
+ RS6000_BTM_FLOAT128.
+
+work052.patch002:
+2021-05-02 Michael Meissner <meissner@linux.ibm.com>
+
+ * config/rs6000/rs6000.c (rs6000_maybe_emit_fp_cmove): Add IEEE
+ 128-bit floating point conditional move support.
+ (have_compare_and_set_mask): Add IEEE 128-bit floating point
+ types.
+ * config/rs6000/rs6000.md (mov<mode>cc, IEEE128 iterator): New insn.
+ (mov<mode>cc_p10, IEEE128 iterator): New insn.
+ (mov<mode>cc_invert_p10, IEEE128 iterator): New insn.
+ (fpmask<mode>, IEEE128 iterator): New insn.
+ (xxsel<mode>, IEEE128 iterator): New insn.
+
+work052.patch001:
+2021-05-02 Michael Meissner <meissner@linux.ibm.com>
+
+ * config/rs6000/rs6000.c (rs6000_emit_minmax): Add support for ISA
+ 3.1 IEEE 128-bit floating point xsmaxcqp and xsmincqp instructions.
+ * config/rs6000/rs6000.md (s<minmax><mode>3, IEEE128 iterator):
+ New insns.
+
2021-05-02 Michael Meissner <meissner@linux.ibm.com>
Clone branch
diff --git a/gcc/testsuite/ChangeLog.meissner b/gcc/testsuite/ChangeLog.meissner
index 039fb645663..55e3d0f2932 100644
--- a/gcc/testsuite/ChangeLog.meissner
+++ b/gcc/testsuite/ChangeLog.meissner
@@ -1,3 +1,139 @@
+work052.patch022:
+2021-05-04 Michael Meissner <meissner@linux.ibm.com>
+
+ * gcc.target/powerpc/fold-vec-div-longlong.c:
+ * gcc.target/powerpc/fold-vec-mult-longlong.c: Turn off power10
+ code generation.
+
+work052.patch021:
+2021-05-04 Michael Meissner <meissner@linux.ibm.com>
+
+ PR target/100166
+ * gcc.target/powerpc/fold-vec-splat-floatdouble.c:
+ * gcc.target/powerpc/fold-vec-splat-longlong.c:
+ * gcc.target/powerpc/lvsl-lvsr.c: Update insn counts if power10
+ code generation is used.
+
+work052.patch020:
+2021-05-04 Michael Meissner <meissner@linux.ibm.com>
+
+ PR target/100166
+ * gcc.target/powerpc/fold-vec-load-builtin_vec_xl-char.c:
+ * gcc.target/powerpc/fold-vec-load-builtin_vec_xl-double.c:
+ * gcc.target/powerpc/fold-vec-load-builtin_vec_xl-float.c:
+ * gcc.target/powerpc/fold-vec-load-builtin_vec_xl-int.c:
+ * gcc.target/powerpc/fold-vec-load-builtin_vec_xl-longlong.c:
+ * gcc.target/powerpc/fold-vec-load-builtin_vec_xl-short.c:
+ * gcc.target/powerpc/fold-vec-load-vec_vsx_ld-char.c:
+ * gcc.target/powerpc/fold-vec-load-vec_vsx_ld-double.c:
+ * gcc.target/powerpc/fold-vec-load-vec_vsx_ld-float.c:
+ * gcc.target/powerpc/fold-vec-load-vec_vsx_ld-int.c:
+ * gcc.target/powerpc/fold-vec-load-vec_vsx_ld-longlong.c:
+ * gcc.target/powerpc/fold-vec-load-vec_vsx_ld-short.c:
+ * gcc.target/powerpc/fold-vec-load-vec_xl-char.c:
+ * gcc.target/powerpc/fold-vec-load-vec_xl-double.c:
+ * gcc.target/powerpc/fold-vec-load-vec_xl-float.c:
+ * gcc.target/powerpc/fold-vec-load-vec_xl-int.c:
+ * gcc.target/powerpc/fold-vec-load-vec_xl-longlong.c:
+ * gcc.target/powerpc/fold-vec-load-vec_xl-short.c:
+ * gcc.target/powerpc/fold-vec-store-builtin_vec_xst-char.c:
+ * gcc.target/powerpc/fold-vec-store-builtin_vec_xst-double.c:
+ * gcc.target/powerpc/fold-vec-store-builtin_vec_xst-float.c:
+ * gcc.target/powerpc/fold-vec-store-builtin_vec_xst-int.c:
+ * gcc.target/powerpc/fold-vec-store-builtin_vec_xst-longlong.c:
+ * gcc.target/powerpc/fold-vec-store-builtin_vec_xst-short.c:
+ * gcc.target/powerpc/fold-vec-store-vec_vsx_st-char.c:
+ * gcc.target/powerpc/fold-vec-store-vec_vsx_st-double.c:
+ * gcc.target/powerpc/fold-vec-store-vec_vsx_st-float.c:
+ * gcc.target/powerpc/fold-vec-store-vec_vsx_st-int.c:
+ * gcc.target/powerpc/fold-vec-store-vec_vsx_st-longlong.c:
+ * gcc.target/powerpc/fold-vec-store-vec_vsx_st-short.c:
+ * gcc.target/powerpc/fold-vec-store-vec_xst-char.c:
+ * gcc.target/powerpc/fold-vec-store-vec_xst-double.c:
+ * gcc.target/powerpc/fold-vec-store-vec_xst-float.c:
+ * gcc.target/powerpc/fold-vec-store-vec_xst-int.c:
+ * gcc.target/powerpc/fold-vec-store-vec_xst-longlong.c:
+ * gcc.target/powerpc/fold-vec-store-vec_xst-short.c: Update
+ insn counts if power10 code generation is used.
+
+
+work052.patch019:
+2021-05-03 Michael Meissner <meissner@linux.ibm.com>
+
+ * gcc.target/powerpc/float128-minmax.c: Turn off power10 code
+ generation.
+ * gcc.target/powerpc/pr86731-fwrapv.c: Turn off power10 code
+ generation.
+
+work052.patch018:
+2021-05-03 Michael Meissner <meissner@linux.ibm.com>
+
+ * gcc.target/powerpc/vec-splat-constant-sf.c: Update insn count.
+ * gcc.target/powerpc/vec-splat-constant-df.c: Update insn count.
+ * gcc.target/powerpc/vec-splat-constant-v2df.c: Update insn
+ count.
+
+work052.patch016:
+2021-05-03 Michael Meissner <meissner@linux.ibm.com>
+
+ * gcc.target/powerpc/vec-splat-constant-sf.c: New test.
+ * gcc.target/powerpc/vec-splat-constant-df.c: New test.
+ * gcc.target/powerpc/vec-splat-constant-v2df.c: New test.
+
+work052.patch014:
+2021-05-03 Michael Meissner <meissner@linux.ibm.com>
+
+ * gcc.target/powerpc/vec-splati-runnable.c: Update insn counts.
+ * gcc.target/powerpc/vec-splat-constant-v4sf.c: New test.
+ * gcc.target/powerpc/vec-splat-constant-v4si.c: New test.
+ * gcc.target/powerpc/vec-splat-constant-v8hi.c: New test.
+
+work052.patch012:
+2021-05-02 Michael Meissner <meissner@linux.ibm.com>
+
+ * gcc.target/powerpc/vec-splati-runnable.c: Run test with -O2
+ optimization. Do not check what XXSPLTIDP generates if the value
+ is undefined.
+
+work052.patch005:
+gcc/testsuite/
+2021-05-02 Michael Meissner <meissner@linux.ibm.com>
+
+ * c-c++-common/dfp/convert-bfp-11.c: Force using IBM 128-bit long
+ double. Remove check for 64-bit long double.
+
+work052.patch004:
+2021-05-02x Michael Meissner <meissner@linux.ibm.com>
+
+ PR target/70117
+ * gcc.target/powerpc/pr70117.c: Force the long double type to use
+ the IBM 128-bit format.
+
+work052.patch003:
+2021-05-02 Michael Meissner <meissner@linux.ibm.com>
+
+ * lib/target-supports.exp
+ (add_options_for_ppc_long_double_override_ibm128): New function.
+ (check_effective_target_ppc_long_double_override_ibm128): New
+ function.
+ (add_options_for_ppc_long_double_override_ieee128): New function.
+ (check_effective_target_ppc_long_double_override_ieee128): New
+ function.
+ (add_options_for_ppc_long_double_override_64bit): New function.
+ (check_effective_target_ppc_long_double_override_64bit): New
+ function.
+
+work052.patch002:
+2021-05-02 Michael Meissner <meissner@linux.ibm.com>
+
+ * gcc.target/powerpc/float128-cmove.c: New test.
+ * gcc.target/powerpc/float128-minmax-3.c: New test.
+
+work052.patch001:
+2021-05-02 Michael Meissner <meissner@linux.ibm.com>
+
+ * gcc.target/powerpc/float128-minmax-2.c: New test.
+
2021-05-02 Michael Meissner <meissner@linux.ibm.com>
Clone branch
diff --git a/libgcc/ChangeLog.meissner b/libgcc/ChangeLog.meissner
index 039fb645663..e30b9794f48 100644
--- a/libgcc/ChangeLog.meissner
+++ b/libgcc/ChangeLog.meissner
@@ -1,3 +1,9 @@
+work052.patch007:
+2021-05-02 Michael Meissner <meissner@linux.ibm.com>
+
+ * config/rs6000/ibm-ldouble.c (pack_ldouble): Use
+ __builtin_pack_ibm128 instead of __builtin_pack_longdouble.
+
2021-05-02 Michael Meissner <meissner@linux.ibm.com>
Clone branch
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