From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1816) id DF2B2393C842; Fri, 14 May 2021 08:56:59 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org DF2B2393C842 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Kyrylo Tkachov To: gcc-cvs@gcc.gnu.org Subject: [gcc r12-790] aarch64: Merge sqdmlal2 and sqdmlsl2 expanders X-Act-Checkin: gcc X-Git-Author: Kyrylo Tkachov X-Git-Refname: refs/heads/master X-Git-Oldrev: 3489257a33d69d9d3778b585558adb7dc33eec6d X-Git-Newrev: 543c0cbca0ca4e9dbe703a9ea4b8eb79744157b6 Message-Id: <20210514085659.DF2B2393C842@sourceware.org> Date: Fri, 14 May 2021 08:56:59 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 14 May 2021 08:57:00 -0000 https://gcc.gnu.org/g:543c0cbca0ca4e9dbe703a9ea4b8eb79744157b6 commit r12-790-g543c0cbca0ca4e9dbe703a9ea4b8eb79744157b6 Author: Kyrylo Tkachov Date: Wed May 12 10:52:51 2021 +0100 aarch64: Merge sqdmlal2 and sqdmlsl2 expanders The various sqdmlal2 and sqdmlsl2 expanders perform almost identical functions and can be merged using code iterators and attributes to reduce the code in the MD file. No behavioural change is expected. gcc/ChangeLog: * config/aarch64/aarch64-simd.md (aarch64_sqdmlal2): Merge into... (aarch64_sqdmll2): ... This. (aarch64_sqdmlsl2): Delete. (aarch64_sqdmlal2_lane): Merge this... (aarch64_sqdmlsl2_lane): ... And this... (aarch64_sqdmll2_lane): ... Into this. (aarch64_sqdmlal2_laneq): Merge this... (aarch64_sqdmlsl2_laneq): ... And this... (aarch64_sqdmll2_laneq): ... Into this. (aarch64_sqdmlal2_n): Merge this... (aarch64_sqdmlsl2_n): ... And this... (aarch64_sqdmll2_n): ... Into this. Diff: --- gcc/config/aarch64/aarch64-simd.md | 104 ++++++++++--------------------------- 1 file changed, 28 insertions(+), 76 deletions(-) diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 99620895e78..802cca3a68a 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -5356,29 +5356,19 @@ [(set_attr "type" "neon_sat_mla__scalar_long")] ) -(define_expand "aarch64_sqdmlal2" +(define_expand "aarch64_sqdmll2" [(match_operand: 0 "register_operand") - (match_operand: 1 "register_operand") + (SBINQOPS: + (match_operand: 1 "register_operand") + (match_dup 1)) (match_operand:VQ_HSI 2 "register_operand") (match_operand:VQ_HSI 3 "register_operand")] "TARGET_SIMD" { rtx p = aarch64_simd_vect_par_cnst_half (mode, , true); - emit_insn (gen_aarch64_sqdmlal2_internal (operands[0], operands[1], - operands[2], operands[3], p)); - DONE; -}) - -(define_expand "aarch64_sqdmlsl2" - [(match_operand: 0 "register_operand") - (match_operand: 1 "register_operand") - (match_operand:VQ_HSI 2 "register_operand") - (match_operand:VQ_HSI 3 "register_operand")] - "TARGET_SIMD" -{ - rtx p = aarch64_simd_vect_par_cnst_half (mode, , true); - emit_insn (gen_aarch64_sqdmlsl2_internal (operands[0], operands[1], - operands[2], operands[3], p)); + emit_insn (gen_aarch64_sqdmll2_internal (operands[0], + operands[1], operands[2], + operands[3], p)); DONE; }) @@ -5436,63 +5426,37 @@ [(set_attr "type" "neon_sat_mla__scalar_long")] ) -(define_expand "aarch64_sqdmlal2_lane" - [(match_operand: 0 "register_operand") - (match_operand: 1 "register_operand") - (match_operand:VQ_HSI 2 "register_operand") - (match_operand: 3 "register_operand") - (match_operand:SI 4 "immediate_operand")] - "TARGET_SIMD" -{ - rtx p = aarch64_simd_vect_par_cnst_half (mode, , true); - emit_insn (gen_aarch64_sqdmlal2_lane_internal (operands[0], operands[1], - operands[2], operands[3], - operands[4], p)); - DONE; -}) - -(define_expand "aarch64_sqdmlal2_laneq" - [(match_operand: 0 "register_operand") - (match_operand: 1 "register_operand") - (match_operand:VQ_HSI 2 "register_operand") - (match_operand: 3 "register_operand") - (match_operand:SI 4 "immediate_operand")] - "TARGET_SIMD" -{ - rtx p = aarch64_simd_vect_par_cnst_half (mode, , true); - emit_insn (gen_aarch64_sqdmlal2_laneq_internal (operands[0], operands[1], - operands[2], operands[3], - operands[4], p)); - DONE; -}) - -(define_expand "aarch64_sqdmlsl2_lane" +(define_expand "aarch64_sqdmll2_lane" [(match_operand: 0 "register_operand") - (match_operand: 1 "register_operand") + (SBINQOPS: + (match_operand: 1 "register_operand") + (match_dup 1)) (match_operand:VQ_HSI 2 "register_operand") (match_operand: 3 "register_operand") (match_operand:SI 4 "immediate_operand")] "TARGET_SIMD" { rtx p = aarch64_simd_vect_par_cnst_half (mode, , true); - emit_insn (gen_aarch64_sqdmlsl2_lane_internal (operands[0], operands[1], - operands[2], operands[3], - operands[4], p)); + emit_insn (gen_aarch64_sqdmll2_lane_internal (operands[0], + operands[1], operands[2], + operands[3], operands[4], p)); DONE; }) -(define_expand "aarch64_sqdmlsl2_laneq" +(define_expand "aarch64_sqdmll2_laneq" [(match_operand: 0 "register_operand") - (match_operand: 1 "register_operand") + (SBINQOPS: + (match_operand: 1 "register_operand") + (match_dup 1)) (match_operand:VQ_HSI 2 "register_operand") (match_operand: 3 "register_operand") (match_operand:SI 4 "immediate_operand")] "TARGET_SIMD" { rtx p = aarch64_simd_vect_par_cnst_half (mode, , true); - emit_insn (gen_aarch64_sqdmlsl2_laneq_internal (operands[0], operands[1], - operands[2], operands[3], - operands[4], p)); + emit_insn (gen_aarch64_sqdmll2_laneq_internal (operands[0], + operands[1], operands[2], + operands[3], operands[4], p)); DONE; }) @@ -5515,31 +5479,19 @@ [(set_attr "type" "neon_sat_mla__scalar_long")] ) -(define_expand "aarch64_sqdmlal2_n" - [(match_operand: 0 "register_operand") - (match_operand: 1 "register_operand") - (match_operand:VQ_HSI 2 "register_operand") - (match_operand: 3 "register_operand")] - "TARGET_SIMD" -{ - rtx p = aarch64_simd_vect_par_cnst_half (mode, , true); - emit_insn (gen_aarch64_sqdmlal2_n_internal (operands[0], operands[1], - operands[2], operands[3], - p)); - DONE; -}) - -(define_expand "aarch64_sqdmlsl2_n" +(define_expand "aarch64_sqdmll2_n" [(match_operand: 0 "register_operand") - (match_operand: 1 "register_operand") + (SBINQOPS: + (match_operand: 1 "register_operand") + (match_dup 1)) (match_operand:VQ_HSI 2 "register_operand") (match_operand: 3 "register_operand")] "TARGET_SIMD" { rtx p = aarch64_simd_vect_par_cnst_half (mode, , true); - emit_insn (gen_aarch64_sqdmlsl2_n_internal (operands[0], operands[1], - operands[2], operands[3], - p)); + emit_insn (gen_aarch64_sqdmll2_n_internal (operands[0], + operands[1], operands[2], + operands[3], p)); DONE; })