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From: Jonathan Wright <jonwri01@gcc.gnu.org>
To: gcc-cvs@gcc.gnu.org
Subject: [gcc r12-920] aarch64: Use correct type attributes for RTL generating XTN(2)
Date: Wed, 19 May 2021 13:47:12 +0000 (GMT) [thread overview]
Message-ID: <20210519134712.96BF8386FC08@sourceware.org> (raw)
https://gcc.gnu.org/g:45364338209929542b14b805796f40b71a0fa960
commit r12-920-g45364338209929542b14b805796f40b71a0fa960
Author: Jonathan Wright <jonathan.wright@arm.com>
Date: Tue May 18 15:56:53 2021 +0100
aarch64: Use correct type attributes for RTL generating XTN(2)
Use the correct "neon_move_narrow_q" type attribute in RTL patterns
that generate XTN/XTN2 instructions.
This makes a material difference because these instructions can be
executed on both SIMD pipes in the Cortex-A57 core model, whereas the
"neon_shift_imm_narrow_q" attribute (in use until now) would suggest
to the scheduler that they could only execute on one of the two
pipes.
gcc/ChangeLog:
2021-05-18 Jonathan Wright <jonathan.wright@arm.com>
* config/aarch64/aarch64-simd.md: Use "neon_move_narrow_q"
type attribute in patterns generating XTN(2).
Diff:
---
gcc/config/aarch64/aarch64-simd.md | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 447b5575f2f..e750faed1db 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -1697,7 +1697,7 @@
(truncate:<VNARROWQ> (match_operand:VQN 1 "register_operand" "w")))]
"TARGET_SIMD"
"xtn\\t%0.<Vntype>, %1.<Vtype>"
- [(set_attr "type" "neon_shift_imm_narrow_q")]
+ [(set_attr "type" "neon_move_narrow_q")]
)
(define_insn "aarch64_xtn2<mode>_le"
@@ -1707,7 +1707,7 @@
(truncate:<VNARROWQ> (match_operand:VQN 2 "register_operand" "w"))))]
"TARGET_SIMD && !BYTES_BIG_ENDIAN"
"xtn2\t%0.<V2ntype>, %2.<Vtype>"
- [(set_attr "type" "neon_shift_imm_narrow_q")]
+ [(set_attr "type" "neon_move_narrow_q")]
)
(define_insn "aarch64_xtn2<mode>_be"
@@ -1717,7 +1717,7 @@
(match_operand:<VNARROWQ> 1 "register_operand" "0")))]
"TARGET_SIMD && BYTES_BIG_ENDIAN"
"xtn2\t%0.<V2ntype>, %2.<Vtype>"
- [(set_attr "type" "neon_shift_imm_narrow_q")]
+ [(set_attr "type" "neon_move_narrow_q")]
)
(define_expand "aarch64_xtn2<mode>"
@@ -8618,7 +8618,7 @@
(truncate:<VNARROWQ> (match_operand:VQN 1 "register_operand" "w")))]
"TARGET_SIMD"
"xtn\t%0.<Vntype>, %1.<Vtype>"
- [(set_attr "type" "neon_shift_imm_narrow_q")]
+ [(set_attr "type" "neon_move_narrow_q")]
)
(define_insn "aarch64_bfdot<mode>"
reply other threads:[~2021-05-19 13:47 UTC|newest]
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