From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 7835) id 96BF8386FC08; Wed, 19 May 2021 13:47:12 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 96BF8386FC08 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Jonathan Wright To: gcc-cvs@gcc.gnu.org Subject: [gcc r12-920] aarch64: Use correct type attributes for RTL generating XTN(2) X-Act-Checkin: gcc X-Git-Author: Jonathan Wright X-Git-Refname: refs/heads/master X-Git-Oldrev: 577d5819e0cada818aca975752809d55ccecc6e8 X-Git-Newrev: 45364338209929542b14b805796f40b71a0fa960 Message-Id: <20210519134712.96BF8386FC08@sourceware.org> Date: Wed, 19 May 2021 13:47:12 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 19 May 2021 13:47:12 -0000 https://gcc.gnu.org/g:45364338209929542b14b805796f40b71a0fa960 commit r12-920-g45364338209929542b14b805796f40b71a0fa960 Author: Jonathan Wright Date: Tue May 18 15:56:53 2021 +0100 aarch64: Use correct type attributes for RTL generating XTN(2) Use the correct "neon_move_narrow_q" type attribute in RTL patterns that generate XTN/XTN2 instructions. This makes a material difference because these instructions can be executed on both SIMD pipes in the Cortex-A57 core model, whereas the "neon_shift_imm_narrow_q" attribute (in use until now) would suggest to the scheduler that they could only execute on one of the two pipes. gcc/ChangeLog: 2021-05-18 Jonathan Wright * config/aarch64/aarch64-simd.md: Use "neon_move_narrow_q" type attribute in patterns generating XTN(2). Diff: --- gcc/config/aarch64/aarch64-simd.md | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 447b5575f2f..e750faed1db 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -1697,7 +1697,7 @@ (truncate: (match_operand:VQN 1 "register_operand" "w")))] "TARGET_SIMD" "xtn\\t%0., %1." - [(set_attr "type" "neon_shift_imm_narrow_q")] + [(set_attr "type" "neon_move_narrow_q")] ) (define_insn "aarch64_xtn2_le" @@ -1707,7 +1707,7 @@ (truncate: (match_operand:VQN 2 "register_operand" "w"))))] "TARGET_SIMD && !BYTES_BIG_ENDIAN" "xtn2\t%0., %2." - [(set_attr "type" "neon_shift_imm_narrow_q")] + [(set_attr "type" "neon_move_narrow_q")] ) (define_insn "aarch64_xtn2_be" @@ -1717,7 +1717,7 @@ (match_operand: 1 "register_operand" "0")))] "TARGET_SIMD && BYTES_BIG_ENDIAN" "xtn2\t%0., %2." - [(set_attr "type" "neon_shift_imm_narrow_q")] + [(set_attr "type" "neon_move_narrow_q")] ) (define_expand "aarch64_xtn2" @@ -8618,7 +8618,7 @@ (truncate: (match_operand:VQN 1 "register_operand" "w")))] "TARGET_SIMD" "xtn\t%0., %1." - [(set_attr "type" "neon_shift_imm_narrow_q")] + [(set_attr "type" "neon_move_narrow_q")] ) (define_insn "aarch64_bfdot"