From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1652) id 85DCB3851C3A; Fri, 21 May 2021 16:14:32 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 85DCB3851C3A Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Christophe Lyon To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/clyon/heads/mve-autovec)] arm: Auto-vectorization for MVE: vaddv X-Act-Checkin: gcc X-Git-Author: Christophe Lyon X-Git-Refname: refs/users/clyon/heads/mve-autovec X-Git-Oldrev: a4de252dd69f56d989955935e544fa1f14b9b8a2 X-Git-Newrev: f5acca021becbf6e39ffd5249c2fd554ea030ca5 Message-Id: <20210521161432.85DCB3851C3A@sourceware.org> Date: Fri, 21 May 2021 16:14:32 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 21 May 2021 16:14:32 -0000 https://gcc.gnu.org/g:f5acca021becbf6e39ffd5249c2fd554ea030ca5 commit f5acca021becbf6e39ffd5249c2fd554ea030ca5 Author: Christophe Lyon Date: Fri May 21 16:12:58 2021 +0000 arm: Auto-vectorization for MVE: vaddv Diff: --- gcc/config/arm/mve.md | 2 +- gcc/config/arm/neon.md | 13 ------------- gcc/config/arm/vec-common.md | 26 +++++++++++++++++++++++++ gcc/testsuite/gcc.target/arm/simd/mve-vaddv-1.c | 26 +++++++++++++++++++++++++ 4 files changed, 53 insertions(+), 14 deletions(-) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 133ebe93cf3..0a6ba80c99d 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -464,7 +464,7 @@ ;; ;; [vaddvq_s, vaddvq_u]) ;; -(define_insn "mve_vaddvq_" +(define_insn "@mve_vaddvq_" [ (set (match_operand:SI 0 "s_register_operand" "=Te") (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")] diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index 977adef5490..6a6573317cf 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -1161,19 +1161,6 @@ DONE; }) -(define_expand "reduc_plus_scal_" - [(match_operand: 0 "nonimmediate_operand") - (match_operand:VQ 1 "s_register_operand")] - "ARM_HAVE_NEON__ARITH && !BYTES_BIG_ENDIAN" -{ - rtx step1 = gen_reg_rtx (mode); - - emit_insn (gen_quad_halves_plus (step1, operands[1])); - emit_insn (gen_reduc_plus_scal_ (operands[0], step1)); - - DONE; -}) - (define_expand "reduc_plus_scal_v2di" [(match_operand:DI 0 "nonimmediate_operand") (match_operand:V2DI 1 "s_register_operand")] diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md index e8b2901b006..cc136e2865f 100644 --- a/gcc/config/arm/vec-common.md +++ b/gcc/config/arm/vec-common.md @@ -539,3 +539,29 @@ emit_insn (gen_mve_vst4q (operands[0], operands[1])); DONE; }) + +(define_expand "reduc_plus_scal_" + [(match_operand: 0 "nonimmediate_operand") + (match_operand:VQ 1 "s_register_operand")] + "ARM_HAVE_NEON__ARITH || (TARGET_HAVE_MVE && mode != V4SFmode) + && !TARGET_REALLY_IWMMXT + && !BYTES_BIG_ENDIAN" +{ + if (TARGET_NEON) + { + rtx step1 = gen_reg_rtx (mode); + + emit_insn (gen_quad_halves_plus (step1, operands[1])); + emit_insn (gen_reduc_plus_scal_ (operands[0], step1)); + } + else + { + /* vaddv generates a 32 bits accumulator. */ + rtx op0 = gen_reg_rtx (SImode); + + emit_insn (gen_mve_vaddvq (VADDVQ_S, mode, op0, operands[1])); + emit_insn (gen_rtx_SET (operands[0], gen_rtx_SUBREG (mode, op0, 0))); + } + + DONE; +}) diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-vaddv-1.c b/gcc/testsuite/gcc.target/arm/simd/mve-vaddv-1.c new file mode 100644 index 00000000000..b6b0bc368f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/mve-vaddv-1.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O3" } */ + +#include + +#define FUNC(SIGN, TYPE, BITS, NB) \ + TYPE##32_t test_ ##_ ## SIGN ## BITS ## x ## NB (TYPE##BITS##_t *a) { \ + int i; \ + TYPE##BITS##_t result = 0; \ + for (i=0; i