From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 14BD5385E02C; Tue, 25 May 2021 05:14:56 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 14BD5385E02C Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work053)] Revert patches. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work053 X-Git-Oldrev: 91c31f70de9db1966042d45a2d1c3c9821f02e57 X-Git-Newrev: bf90a563930d303451ae3a4392656cf381d0f576 Message-Id: <20210525051456.14BD5385E02C@sourceware.org> Date: Tue, 25 May 2021 05:14:56 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 25 May 2021 05:14:56 -0000 https://gcc.gnu.org/g:bf90a563930d303451ae3a4392656cf381d0f576 commit bf90a563930d303451ae3a4392656cf381d0f576 Author: Michael Meissner Date: Tue May 25 01:13:58 2021 -0400 Revert patches. gcc/ 2021-05-25 Michael Meissner Revert patch. * config/rs6000/constraint.md (eQ): New constraint. * config/rs6000/predicates.md (easy_fp_constant): If the constant can be loaded with LXVKQ, it is easy. (lxvkq_operand): New predicate. * config/rs6000/rs6000-protos.h (lxvkq_constant_p): New declaration. * config/rs6000/rs6000-cpus.h (ISA_3_1_MASKS_SERVER): Add -mlxvkq. (POWERPC_MASKS): Add -mlxvkq. * config/rs6000/rs6000.c (rs6000_option_override_internal): Add support for -mlxvkq. (lxvkq_constant_p): New function. (rs6000_output_move_128bit): Add support for generating lxvkq. (rs6000_opt_masks): Add -mlxvkq. * config/rs6000/rs6000.opt (-mlxvkq): New option. * config/rs6000/vsx.md (vsx_mov_64bit): Add support to generate lxvkq. (vsx_mov_32bit): Add support to generate lxvkq. gcc/testsuite/ 2021-05-20 Michael Meissner Revert patch. * gcc.target/powerpc/float128-lxvkq.c: New test. gcc/ 2021-05-20 Michael Meissner Revert patch. * config/rs6000/constraint.md (eD): New constraint. * config/rs6000/predicates.md (easy_fp_constant): If the constant can be loaded with XXSPLTI32DX, it is easy. (xxsplti32dx_operand): New predicate. (easy_vector_constant): If the constant can be loaded with XXSPLTI32DX, it is easy. * config/rs6000/rs6000-protos.h (xxsplti32dx_constant_p): New declaration. * config/rs6000/rs6000.c (rs6000_option_override_internal): Add support for -mxxsplti32dx. (xxsplti32dx_constant_float_p): New helper function. (xxsplti32dx_constant_p): New function. (output_vec_const_move): If the operand can be loaded with XXSPLTI32DX, split it. (rs6000_opt_masks): Add -mxxsplti32dx. * config/rs6000/rs6000.md (movsf_hardfloat): Add support for constants loaded with XXSPLTI32DX. (mov_hardfloat32, FMOVE64 iterator): Add support for constants loaded with XXSPLTI32DX. (mov_hardfloat64, FMOVE64 iterator): Add support for constants loaded with XXSPLTI32DX. * config/rs6000/rs6000.opt (-mxxsplti32dx): New option. * config/rs6000/vsx.md (UNSPEC_XXSPLTI32DX_CONST): New unspec. (XXSPLTI32DX): New mode iterator. (xxsplti32dx_): New insn and splitter for XXSPLTI32DX. (xxsplti32dx__first): New insn. (xxsplti32dx__second): New insn. gcc/testsuite/ 2021-05-20 Michael Meissner Revert patch. * gcc.target/powerpc/vec-splat-constant-sf.c: Update insn count. * gcc.target/powerpc/vec-splat-constant-df.c: Update insn count. * gcc.target/powerpc/vec-splat-constant-v2df.c: Update insn count. Diff: --- gcc/config/rs6000/constraints.md | 11 -- gcc/config/rs6000/predicates.md | 32 --- gcc/config/rs6000/rs6000-cpus.def | 2 - gcc/config/rs6000/rs6000-protos.h | 3 - gcc/config/rs6000/rs6000.c | 218 +-------------------- gcc/config/rs6000/rs6000.md | 67 ++----- gcc/config/rs6000/rs6000.opt | 8 - gcc/config/rs6000/vsx.md | 100 ++-------- gcc/testsuite/gcc.target/powerpc/float128-lxvkq.c | 144 -------------- .../gcc.target/powerpc/vec-splat-constant-df.c | 9 +- .../gcc.target/powerpc/vec-splat-constant-sf.c | 5 +- .../gcc.target/powerpc/vec-splat-constant-v2df.c | 10 +- 12 files changed, 42 insertions(+), 567 deletions(-) diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md index d14ce98e9ac..e1fadd63580 100644 --- a/gcc/config/rs6000/constraints.md +++ b/gcc/config/rs6000/constraints.md @@ -208,12 +208,6 @@ (and (match_code "const_int") (match_test "((- (unsigned HOST_WIDE_INT) ival) + 0x8000) < 0x10000"))) -;; SF/DF/V2DF/DI/V2DI scalar or vector constant that can be loaded with a pair -;; of XXSPLTI32DX instructions. -(define_constraint "eD" - "A vector constant that can be loaded with XXSPLTI32DX instructions." - (match_operand 0 "xxsplti32dx_operand")) - ;; SF/DF/V2DF scalar or vector constant that can be loaded with XXSPLTIDP (define_constraint "eF" "A vector constant that can be loaded with the XXSPLTIDP instruction." @@ -224,11 +218,6 @@ "A signed 34-bit integer constant if prefixed instructions are supported." (match_operand 0 "cint34_operand")) -;; KF/TF scalar than can be loaded with XVKQ -(define_constraint "eQ" - "An IEEE 128-bit constant that can be loaded with the LXVKQ instruction." - (match_operand 0 "lxvkq_operand")) - ;; Floating-point constraints. These two are defined so that insn ;; length attributes can be calculated exactly. diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index 0c17db42962..8c461ba2b76 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -606,16 +606,6 @@ if (xxspltidp_operand (op, mode)) return 1; - /* If we have the ISA 3.1 XXSPLTI32DX instruction, see if the constant can - be loaded with a pair of those instructions. */ - if (xxsplti32dx_operand (op, mode)) - return 1; - - /* If we have the ISA 3.1 LXVKQ instruction, see if the constant can be loaded - with that instruction. */ - if (lxvkq_operand (op, mode)) - return 1; - /* Otherwise consider floating point constants hard, so that the constant gets pushed to memory during the early RTL phases. This has the advantage that double precision constants that can be @@ -694,25 +684,6 @@ return xxspltidp_constant_p (op, mode, &value); }) -;; Return 1 if operand is a SF/DF CONST_DOUBLE or V2DF CONST_VECTOR that can be -;; loaded via a pair f ISA 3.1 XXSPLTI32DX instructions. Do not return true if -;; the value can be loaded with the XXSPLTIDP instruction or XXSPLTIB to load 0. -(define_predicate "xxsplti32dx_operand" - (match_code "const_double,const_vector,vec_duplicate") -{ - HOST_WIDE_INT high = 0, low = 0; - return xxsplti32dx_constant_p (op, mode, &high, &low); -}) - -;; Return 1 if the operand is an IEEE 128-bit special constant that can be -;; loaded with the LXVKQ instruction. -(define_predicate "lxvkq_operand" - (match_code "const_double") -{ - int immediate = 0; - return lxvkq_constant_p (op, mode, &immediate); -}) - ;; Return 1 if the operand is a CONST_VECTOR and can be loaded into a ;; vector register without using memory. (define_predicate "easy_vector_constant" @@ -732,9 +703,6 @@ if (xxspltidp_operand (op, mode)) return true; - if (xxsplti32dx_operand (op, mode)) - return true; - if (TARGET_P9_VECTOR && xxspltib_constant_p (op, mode, &num_insns, &value)) return true; diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def index a9553129838..3b657e490b1 100644 --- a/gcc/config/rs6000/rs6000-cpus.def +++ b/gcc/config/rs6000/rs6000-cpus.def @@ -83,7 +83,6 @@ #define ISA_3_1_MASKS_SERVER (ISA_3_0_MASKS_SERVER \ | OPTION_MASK_POWER10 \ | OTHER_POWER10_MASKS \ - | OPTION_MASK_LXVKQ \ | OPTION_MASK_P10_FUSION \ | OPTION_MASK_P10_FUSION_LD_CMPI \ | OPTION_MASK_P10_FUSION_2LOGICAL \ @@ -140,7 +139,6 @@ | OPTION_MASK_P10_FUSION_2LOGICAL \ | OPTION_MASK_HTM \ | OPTION_MASK_ISEL \ - | OPTION_MASK_LXVKQ \ | OPTION_MASK_MFCRF \ | OPTION_MASK_MMA \ | OPTION_MASK_MODULO \ diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h index d71aef11bed..ea8ca6f8d95 100644 --- a/gcc/config/rs6000/rs6000-protos.h +++ b/gcc/config/rs6000/rs6000-protos.h @@ -33,9 +33,6 @@ extern void init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, int, int, int, extern bool easy_altivec_constant (rtx, machine_mode); extern bool xxspltib_constant_p (rtx, machine_mode, int *, int *); extern bool xxspltidp_constant_p (rtx, machine_mode, HOST_WIDE_INT *); -extern bool xxsplti32dx_constant_p (rtx, machine_mode, HOST_WIDE_INT *, - HOST_WIDE_INT *); -extern bool lxvkq_constant_p (rtx, machine_mode, int *); extern int vspltis_shifted (rtx); extern HOST_WIDE_INT const_vector_elt_as_int (rtx, unsigned int); extern bool macho_lo_sum_memory_operand (rtx, machine_mode); diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index a0586804625..bac28806a89 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -4489,23 +4489,14 @@ rs6000_option_override_internal (bool global_init_p) if (TARGET_POWER10 && TARGET_VSX) { - if ((rs6000_isa_flags_explicit & OPTION_MASK_XXSPLTI32DX) == 0) - rs6000_isa_flags |= OPTION_MASK_XXSPLTI32DX; - if ((rs6000_isa_flags_explicit & OPTION_MASK_XXSPLTIW) == 0) rs6000_isa_flags |= OPTION_MASK_XXSPLTIW; if ((rs6000_isa_flags_explicit & OPTION_MASK_XXSPLTIDP) == 0) rs6000_isa_flags |= OPTION_MASK_XXSPLTIDP; - - if ((rs6000_isa_flags_explicit & OPTION_MASK_LXVKQ) == 0) - rs6000_isa_flags |= OPTION_MASK_LXVKQ; } else - rs6000_isa_flags &= ~(OPTION_MASK_LXVKQ - | OPTION_MASK_XXSPLTIW - | OPTION_MASK_XXSPLTIDP - | OPTION_MASK_XXSPLTI32DX); + rs6000_isa_flags &= ~(OPTION_MASK_XXSPLTIW | OPTION_MASK_XXSPLTIDP); if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET) rs6000_print_isa_options (stderr, 0, "after subtarget", rs6000_isa_flags); @@ -6595,199 +6586,6 @@ xxspltidp_constant_p (rtx op, return true; } -/* Return true if OP is a floating point constant that can be loaded with the - XXSPLTI32DX instruction. If the constant can be loaded with the simpler - XXSPLTIDP (constants that can fit as SFmode constants) or XXSPLTIB (0.0) - instructions, return false. - - Return the two 32-bit constants to use in the two XXSPLTI32DX instructions - via HIGH_PTR and LOW_PTR. */ - -static bool -xxsplti32dx_constant_float_p (rtx op, - machine_mode mode, - HOST_WIDE_INT *high_ptr, - HOST_WIDE_INT *low_ptr) -{ - HOST_WIDE_INT xxspltidp_value = 0; - - if (!CONST_DOUBLE_P (op)) - return false; - - if (mode != SFmode && mode != DFmode) - return false; - - if (op == CONST0_RTX (mode)) - return false; - - if (xxspltidp_constant_p (op, mode, &xxspltidp_value)) - return false; - - long high_low[2]; - const struct real_value *rv = CONST_DOUBLE_REAL_VALUE (op); - REAL_VALUE_TO_TARGET_DOUBLE (*rv, high_low); - - /* The double precision value is laid out in memory order. We need to undo - this for XXSPLTI32DX. */ - if (!BYTES_BIG_ENDIAN) - std::swap (high_low[0], high_low[1]); - - *high_ptr = high_low[0]; - *low_ptr = high_low[1]; - return true; -} - -/* Return true if OP is of the given MODE and can be synthesized with ISA 3.1 - XXSPLTI32DX instruction. If the instruction can be synthesized with - XXSPLTIDP or is 0/-1, return false. - - We handle the following types of constants: - - 1) vector double constants where each element is the same and you can't - load the constant with XXSPLTIDP; - - 2) vector long long constants where each element is the same; - - 3) Scalar floating point constants that can't be loaded with XXSPLTIDP. - - Return the two 32-bit constants to use in the two XXSPLTI32DX instructions - via HIGH_PTR and LOW_PTR. */ - -bool -xxsplti32dx_constant_p (rtx op, - machine_mode mode, - HOST_WIDE_INT *high_ptr, - HOST_WIDE_INT *low_ptr) -{ - *high_ptr = *low_ptr = 0; - - if (!TARGET_XXSPLTI32DX) - return false; - - if (mode == VOIDmode) - mode = GET_MODE (op); - - if (op == CONST0_RTX (mode)) - return false; - - switch (mode) - { - default: - break; - - case E_V2DFmode: - { - rtx ele = const_vector_element_all_same (op); - if (!ele) - return false; - - return xxsplti32dx_constant_float_p (ele, DFmode, high_ptr, low_ptr); - } - - case E_SFmode: - case E_DFmode: - return xxsplti32dx_constant_float_p (op, mode, high_ptr, low_ptr); - - case E_V2DImode: - { - rtx ele = const_vector_element_all_same (op); - if (!ele) - return false; - - /* If we can generate XXSPLTIB and VEXTSB2D, don't return true. */ - HOST_WIDE_INT value = INTVAL (ele); - if (IN_RANGE (value, -128, 127)) - return false; - - *high_ptr = value >> 32; - *low_ptr = value & 0xffffffff; - return true; - } - } - - return false; -} - -/* Return true if OP is of the given MODE is one of the 18 special values that - can be generated with the LXVKQ instruction. - - Return the constant that will go in the LXVKQ instruction. - - The LXVKQ immediates are: - 1 - 7: 1.0 .. 7.0. - 8: Positive infinity. - 9: Default quiet NaN. - 16: -0.0. - 17 - 23: -1.0 .. 7.0. - 24: Negative infinity. */ - -bool -lxvkq_constant_p (rtx op, - machine_mode mode, - int *imm_p) -{ - *imm_p = -1; - - if (!TARGET_LXVKQ) - return false; - - if (mode == VOIDmode) - mode = GET_MODE (op); - - if (!FLOAT128_IEEE_P (mode)) - return false; - - if (!CONST_DOUBLE_P (op)) - return false; - - /* All of the values generated can be expressed as SFmode values, so if it - doesn't fit in SFmode, exit. */ - const struct real_value *rv = CONST_DOUBLE_REAL_VALUE (op); - if (!exact_real_truncate (SFmode, rv)) - return 0; - - /* +/- Inifinity is 8/24. */ - if (REAL_VALUE_ISINF (*rv)) - { - *imm_p = real_isneg (rv) ? 24 : 8; - return true; - } - - /* NaN is 9. */ - if (REAL_VALUE_ISNAN (*rv) && !REAL_VALUE_NEGATIVE (*rv)) - { - *imm_p = 9; - return true; - } - - /* -0.0 is 16. */ - if (REAL_VALUE_MINUS_ZERO (*rv)) - { - *imm_p = 16; - return true; - } - - /* The other values are all integers 1..7, and -1..-7. */ - if (!real_isinteger (rv, mode)) - return false; - - HOST_WIDE_INT value = real_to_integer (rv); - if (value >= 1 && value <= 7) - { - *imm_p = value; - return true; - } - else if (value >= -7 && value <= -1) - { - /* Subtraction is used because value is negative. */ - *imm_p = 16 - value; - return true; - } - - /* We can't load the value with LXVKQ. */ - return false; -} - const char * output_vec_const_move (rtx *operands) { @@ -6836,9 +6634,6 @@ output_vec_const_move (rtx *operands) || xxspltidp_operand (vec, mode)) return "#"; - if (xxsplti32dx_operand (vec, mode)) - return "#"; - if (TARGET_P9_VECTOR && xxspltib_constant_p (vec, mode, &num_insns, &xxspltib_value)) { @@ -13560,7 +13355,6 @@ rs6000_output_move_128bit (rtx operands[]) int src_regno; bool dest_gpr_p, dest_fp_p, dest_vmx_p, dest_vsx_p; bool src_gpr_p, src_fp_p, src_vmx_p, src_vsx_p; - int lxvkq_immediate = 0; if (REG_P (dest)) { @@ -13705,14 +13499,6 @@ rs6000_output_move_128bit (rtx operands[]) } /* Constants. */ - else if (dest_vmx_p - && CONST_DOUBLE_P (src) - && lxvkq_constant_p (src, mode, &lxvkq_immediate)) - { - operands[2] = GEN_INT (lxvkq_immediate); - return "lxvkq %x0,%2"; - } - else if (dest_regno >= 0 && (CONST_INT_P (src) || CONST_WIDE_INT_P (src) @@ -24412,7 +24198,6 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] = { "hard-dfp", OPTION_MASK_DFP, false, true }, { "htm", OPTION_MASK_HTM, false, true }, { "isel", OPTION_MASK_ISEL, false, true }, - { "lxvkq", OPTION_MASK_LXVKQ, false, true }, { "mfcrf", OPTION_MASK_MFCRF, false, true }, { "mfpgpr", 0, false, true }, { "mma", OPTION_MASK_MMA, false, true }, @@ -24440,7 +24225,6 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] = { "string", 0, false, true }, { "update", OPTION_MASK_NO_UPDATE, true , true }, { "vsx", OPTION_MASK_VSX, false, true }, - { "xxsplti32dx", OPTION_MASK_XXSPLTI32DX, false, true }, { "xxspltiw", OPTION_MASK_XXSPLTIW, false, true }, { "xxspltidp", OPTION_MASK_XXSPLTIDP, false, true }, #ifdef OPTION_MASK_64BIT diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 1200c4db6a9..57bbe281cee 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -7614,17 +7614,17 @@ ;; ;; LWZ LFS LXSSP LXSSPX STFS STXSSP ;; STXSSPX STW XXLXOR LI FMR XSCPSGNDP -;; MR MT MF NOP XXSPLTIDP XXSPLTI32DX +;; MR MT MF NOP XXSPLTIDP (define_insn "movsf_hardfloat" [(set (match_operand:SF 0 "nonimmediate_operand" "=!r, f, v, wa, m, wY, Z, m, wa, !r, f, wa, - !r, *c*l, !r, *h, wa, wa") + !r, *c*l, !r, *h, wa") (match_operand:SF 1 "input_operand" "m, m, wY, Z, f, v, wa, r, j, j, f, wa, - r, r, *h, 0, eF, eD"))] + r, r, *h, 0, eF"))] "(register_operand (operands[0], SFmode) || register_operand (operands[1], SFmode)) && TARGET_HARD_FLOAT @@ -7647,28 +7647,19 @@ mt%0 %1 mf%1 %0 nop - # #" [(set_attr "type" "load, fpload, fpload, fpload, fpstore, fpstore, fpstore, store, veclogical, integer, fpsimple, fpsimple, - *, mtjmpr, mfjmpr, *, vecperm, vecperm") + *, mtjmpr, mfjmpr, *, vecperm") (set_attr "isa" "*, *, p9v, p8v, *, p9v, p8v, *, *, *, *, *, - *, *, *, *, p10, p10") + *, *, *, *, p10") (set_attr "prefixed" "*, *, *, *, *, *, *, *, *, *, *, *, - *, *, *, *, yes, yes") - (set_attr "max_prefixed_insns" - "*, *, *, *, *, *, - *, *, *, *, *, *, - *, *, *, *, *, 2") - (set_attr "num_insns" - "*, *, *, *, *, *, - *, *, *, *, *, *, - *, *, *, *, *, 2")]) + *, *, *, *, yes")]) ;; LWZ LFIWZX STW STFIWX MTVSRWZ MFVSRWZ ;; FMR MR MT%0 MF%1 NOP @@ -7928,18 +7919,18 @@ ;; STFD LFD FMR LXSD STXSD ;; LXSD STXSD XXLOR XXLXOR GPR<-0 -;; LWZ STW MR XXSPLTIDP XXSPLTI32DX +;; LWZ STW MR XXSPLTIDP (define_insn "*mov_hardfloat32" [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m, d, d, , wY, , Z, , , !r, - Y, r, !r, wa, wa") + Y, r, !r, wa") (match_operand:FMOVE64 1 "input_operand" "d, m, d, wY, , Z, , , , , - r, Y, r, eF, eD"))] + r, Y, r, eF"))] "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && (gpc_reg_operand (operands[0], mode) || gpc_reg_operand (operands[1], mode))" @@ -7957,33 +7948,24 @@ # # # - # #" [(set_attr "type" "fpstore, fpload, fpsimple, fpload, fpstore, fpload, fpstore, veclogical, veclogical, two, - store, load, two, vecperm, vecperm") + store, load, two, vecperm") (set_attr "size" "64") (set_attr "length" "*, *, *, *, *, *, *, *, *, 8, - 8, 8, 8, *, *") + 8, 8, 8, *") (set_attr "isa" "*, *, *, p9v, p9v, p7v, p7v, *, *, *, - *, *, *, p10, p10") + *, *, *, p10") (set_attr "prefixed" "*, *, *, *, *, *, *, *, *, *, - *, *, *, yes, yes") - (set_attr "max_prefixed_insns" - "*, *, *, *, *, - *, *, *, *, *, - *, *, *, *, 2") - (set_attr "num_insns" - "*, *, *, *, *, - *, *, *, *, *, - *, *, *, *, 2")]) + *, *, *, yes")]) ;; STW LWZ MR G-const H-const F-const @@ -8010,19 +7992,19 @@ ;; STFD LFD FMR LXSD STXSD ;; LXSDX STXSDX XXLOR XXLXOR LI 0 ;; STD LD MR MT{CTR,LR} MF{CTR,LR} -;; NOP MFVSRD MTVSRD XXSPLTIDP XXSPLTI32DX +;; NOP MFVSRD MTVSRD XXSPLTIDP (define_insn "*mov_hardfloat64" [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m, d, d, , wY, , Z, , , !r, YZ, r, !r, *c*l, !r, - *h, r, , wa, wa") + *h, r, , wa") (match_operand:FMOVE64 1 "input_operand" "d, m, d, wY, , Z, , , , , r, YZ, r, r, *h, - 0, , r, eF, eD"))] + 0, , r, eF"))] "TARGET_POWERPC64 && TARGET_HARD_FLOAT && (gpc_reg_operand (operands[0], mode) || gpc_reg_operand (operands[1], mode))" @@ -8045,34 +8027,23 @@ nop mfvsrd %0,%x1 mtvsrd %x0,%1 - # #" [(set_attr "type" "fpstore, fpload, fpsimple, fpload, fpstore, fpload, fpstore, veclogical, veclogical, integer, store, load, *, mtjmpr, mfjmpr, - *, mfvsr, mtvsr, vecperm, vecperm") + *, mfvsr, mtvsr, vecperm") (set_attr "size" "64") (set_attr "isa" "*, *, *, p9v, p9v, p7v, p7v, *, *, *, *, *, *, *, *, - *, p8v, p8v, p10, p10") + *, p8v, p8v, p10") (set_attr "prefixed" "*, *, *, *, *, *, *, *, *, *, *, *, *, *, *, - *, *, *, yes, yes") - (set_attr "max_prefixed_insns" - "*, *, *, *, *, - *, *, *, *, *, - *, *, *, *, *, - *, *, *, *, 2") - (set_attr "num_insns" - "*, *, *, *, *, - *, *, *, *, *, - *, *, *, *, *, - *, *, *, *, *")]) + *, *, *, yes")]) ;; STD LD MR MT MF G-const ;; H-const F-const Special diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index 5bf96209b83..03e7ed28634 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -635,11 +635,3 @@ Generate (do not generate) XXSPLTIW instructions. mxxspltidp Target Undocumented Mask(XXSPLTIDP) Var(rs6000_isa_flags) Generate (do not generate) XXSPLTIDP instructions. - -mxxsplti32dx -Target Undocumented Mask(XXSPLTI32DX) Var(rs6000_isa_flags) -Generate (do not generate) XXSPLTI32DX instructions. - -mlxvkq -Target Undocumented Mask(LXVKQ) Var(rs6000_isa_flags) -Generate (do not generate) LXVKQ instructions. diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index bc708113865..168e4c21af8 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -388,7 +388,6 @@ UNSPEC_XXEVAL UNSPEC_XXSPLTIDP UNSPEC_XXSPLTI32DX - UNSPEC_XXSPLTI32DX_CONST UNSPEC_XXBLEND UNSPEC_XXPERMX ]) @@ -1189,17 +1188,17 @@ ;; VSX store VSX load VSX move VSX->GPR GPR->VSX LQ (GPR) ;; STQ (GPR) GPR load GPR store GPR move XXSPLTIB VSPLTISW -;; VSX 0/-1 VMX const GPR const LVX (VMX) STVX (VMX) LXVKQ +;; VSX 0/-1 VMX const GPR const LVX (VMX) STVX (VMX) (define_insn "vsx_mov_64bit" [(set (match_operand:VSX_M 0 "nonimmediate_operand" "=ZwO, wa, wa, r, we, ?wQ, ?&r, ??r, ??Y, , wa, v, - ?wa, v, , wZ, v, wa") + ?wa, v, , wZ, v") (match_operand:VSX_M 1 "input_operand" "wa, ZwO, wa, we, r, r, wQ, Y, r, r, wE, jwM, - ?jwM, W, , v, wZ, eQ"))] + ?jwM, W, , v, wZ"))] "TARGET_POWERPC64 && VECTOR_MEM_VSX_P (mode) && (register_operand (operands[0], mode) @@ -1210,37 +1209,37 @@ [(set_attr "type" "vecstore, vecload, vecsimple, mtvsr, mfvsr, load, store, load, store, *, vecsimple, vecsimple, - vecsimple, *, *, vecstore, vecload, vecsimple") + vecsimple, *, *, vecstore, vecload") (set_attr "num_insns" "*, *, *, 2, *, 2, 2, 2, 2, 2, *, *, - *, 5, 2, *, *, *") + *, 5, 2, *, *") (set_attr "max_prefixed_insns" "*, *, *, *, *, 2, 2, 2, 2, 2, *, *, - *, *, *, *, *, *") + *, *, *, *, *") (set_attr "length" "*, *, *, 8, *, 8, 8, 8, 8, 8, *, *, - *, 20, 8, *, *, *") + *, 20, 8, *, *") (set_attr "isa" ", , , *, *, *, *, *, *, *, p9v, *, - , *, *, *, *, p10")]) + , *, *, *, *")]) ;; VSX store VSX load VSX move GPR load GPR store GPR move ;; XXSPLTIB VSPLTISW VSX 0/-1 VMX const GPR const -;; LVX (VMX) STVX (VMX) LXVKQ +;; LVX (VMX) STVX (VMX) (define_insn "*vsx_mov_32bit" [(set (match_operand:VSX_M 0 "nonimmediate_operand" "=ZwO, wa, wa, ??r, ??Y, , wa, v, ?wa, v, , - wZ, v, wa") + wZ, v") (match_operand:VSX_M 1 "input_operand" "wa, ZwO, wa, Y, r, r, wE, jwM, ?jwM, W, , - v, wZ, eQ"))] + v, wZ"))] "!TARGET_POWERPC64 && VECTOR_MEM_VSX_P (mode) && (register_operand (operands[0], mode) @@ -1251,15 +1250,15 @@ [(set_attr "type" "vecstore, vecload, vecsimple, load, store, *, vecsimple, vecsimple, vecsimple, *, *, - vecstore, vecload, vecsimple") + vecstore, vecload") (set_attr "length" "*, *, *, 16, 16, 16, *, *, *, 20, 16, - *, *, *") + *, *") (set_attr "isa" ", , , *, *, *, p9v, *, , *, *, - *, *, p10")]) + *, *")]) ;; Explicit load/store expanders for the builtin functions (define_expand "vsx_load_" @@ -6531,74 +6530,3 @@ "xxspltidp %x0,%1" [(set_attr "type" "vecperm") (set_attr "prefixed" "yes")]) - -;; XXSPLTI32DX used to create 64-bit constants or vector constants where the -;; even elements match and the odd elements match. -(define_mode_iterator XXSPLTI32DX [SF DF V2DF V2DI]) - -(define_insn_and_split "*xxsplti32dx_" - [(set (match_operand:XXSPLTI32DX 0 "vsx_register_operand" "=wa") - (match_operand:XXSPLTI32DX 1 "xxsplti32dx_operand"))] - "TARGET_XXSPLTI32DX" - "#" - "&& 1" - [(set (match_dup 0) - (unspec:XXSPLTI32DX [(match_dup 2) - (match_dup 3)] UNSPEC_XXSPLTI32DX_CONST)) - (set (match_dup 0) - (unspec:XXSPLTI32DX [(match_dup 0) - (match_dup 4) - (match_dup 5)] UNSPEC_XXSPLTI32DX_CONST))] -{ - HOST_WIDE_INT high = 0, low = 0; - - if (!xxsplti32dx_constant_p (operands[1], mode, &high, &low)) - gcc_unreachable (); - - /* If the low bits are 0 or all 1s, initialize that word first. This way we - can use a smaller XXSPLTIB instruction instead the first XXSPLTI32DX. */ - if (low == 0 || low == -1) - { - operands[2] = const1_rtx; - operands[3] = GEN_INT (low); - operands[4] = const0_rtx; - operands[5] = GEN_INT (high); - } - else - { - operands[2] = const0_rtx; - operands[3] = GEN_INT (high); - operands[4] = const1_rtx; - operands[5] = GEN_INT (low); - } -} - [(set_attr "type" "vecperm") - (set_attr "prefixed" "yes") - (set_attr "num_insns" "2") - (set_attr "max_prefixed_insns" "2")]) - -;; First word of XXSPLTI32DX -(define_insn "*xxsplti32dx__first" - [(set (match_operand:XXSPLTI32DX 0 "vsx_register_operand" "=wa,wa,wa") - (unspec:XXSPLTI32DX [(match_operand 1 "u1bit_cint_operand" "n,n,n") - (match_operand 2 "const_int_operand" "O,wM,n")] - UNSPEC_XXSPLTI32DX_CONST))] - "TARGET_XXSPLTI32DX" - "@ - xxspltib %x0,0 - xxspltib %x0,255 - xxsplti32dx %x0,%1,%2" - [(set_attr "type" "vecperm") - (set_attr "prefixed" "*,*,yes")]) - -;; Second word of XXSPLTI32DX -(define_insn "*xxsplti32dx__second" - [(set (match_operand:XXSPLTI32DX 0 "vsx_register_operand" "=wa") - (unspec:XXSPLTI32DX [(match_operand:XXSPLTI32DX 1 "vsx_register_operand" "0") - (match_operand 2 "u1bit_cint_operand" "n") - (match_operand 3 "const_int_operand" "n")] - UNSPEC_XXSPLTI32DX_CONST))] - "TARGET_XXSPLTI32DX" - "xxsplti32dx %x0,%2,%3" - [(set_attr "type" "vecperm") - (set_attr "prefixed" "yes")]) diff --git a/gcc/testsuite/gcc.target/powerpc/float128-lxvkq.c b/gcc/testsuite/gcc.target/powerpc/float128-lxvkq.c deleted file mode 100644 index a5cbe0b477f..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/float128-lxvkq.c +++ /dev/null @@ -1,144 +0,0 @@ -/* { dg-require-effective-target ppc_float128_hw } */ -/* { dg-require-effective-target power10_ok } */ -/* { dg-options "-mdejagnu-cpu=power10 -O2" } */ - -/* Test whether the LXVKQ instruction is generated to load special IEEE 128-bit - constants. */ - -_Float128 -return_0 (void) -{ - return 0.0f128; /* XXSPLTIB 34,0. */ -} - -_Float128 -return_1 (void) -{ - return 1.0f128; /* LXVKQ 34,1. */ -} - -_Float128 -return_2 (void) -{ - return 2.0f128; /* LXVKQ 34,2. */ -} - -_Float128 -return_3 (void) -{ - return 3.0f128; /* LXVKQ 34,3. */ -} - -_Float128 -return_4 (void) -{ - return 4.0f128; /* LXVKQ 34,4. */ -} - -_Float128 -return_5 (void) -{ - return 5.0f128; /* LXVKQ 34,5. */ -} - -_Float128 -return_6 (void) -{ - return 6.0f128; /* LXVKQ 34,6. */ -} - -_Float128 -return_7 (void) -{ - return 7.0f128; /* LXVKQ 34,7. */ -} - -_Float128 -return_m0 (void) -{ - return -0.0f128; /* LXVKQ 34,16. */ -} - -_Float128 -return_m1 (void) -{ - return -1.0f128; /* LXVKQ 34,17. */ -} - -_Float128 -return_m2 (void) -{ - return -2.0f128; /* LXVKQ 34,18. */ -} - -_Float128 -return_m3 (void) -{ - return -3.0f128; /* LXVKQ 34,19. */ -} - -_Float128 -return_m4 (void) -{ - return -4.0f128; /* LXVKQ 34,20. */ -} - -_Float128 -return_m5 (void) -{ - return -5.0f128; /* LXVKQ 34,21. */ -} - -_Float128 -return_m6 (void) -{ - return -6.0f128; /* LXVKQ 34,22. */ -} - -_Float128 -return_m7 (void) -{ - return -7.0f128; /* LXVKQ 34,23. */ -} - -_Float128 -return_inf (void) -{ - return __builtin_inff128 (); /* LXVKQ 34,8. */ -} - -_Float128 -return_minf (void) -{ - return - __builtin_inff128 (); /* LXVKQ 34,24. */ -} - -_Float128 -return_nan (void) -{ - return __builtin_nanf128 (""); /* LXVKQ 34,9. */ -} - -/* Note, the following NaNs should not generate a LXVKQ instruction. */ -_Float128 -return_mnan (void) -{ - return - __builtin_nanf128 (""); /* PLXV 34,... */ -} - -_Float128 -return_nan2 (void) -{ - return __builtin_nanf128 ("1"); /* PLXV 34,... */ -} - -_Float128 -return_nans (void) -{ - return __builtin_nansf128 (""); /* PLXV 34,... */ -} - -/* { dg-final { scan-assembler-times {\mlxvkq\M} 18 } } */ -/* { dg-final { scan-assembler-times {\mplxv\M} 3 } } */ -/* { dg-final { scan-assembler-times {\mxxspltib\M} 1 } } */ - diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c index 1435ef4ef4f..8f6e176f9af 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c @@ -48,16 +48,13 @@ scalar_double_m_inf (void) /* XXSPLTIDP. */ double scalar_double_pi (void) { - return M_PI; /* 2x XXSPLTI32DX. */ + return M_PI; /* PLFD. */ } double scalar_double_denorm (void) { - return 0x1p-149f; /* XXSPLTIB, XXSPLTI32DX. */ + return 0x1p-149f; /* PLFD. */ } -/* { dg-final { scan-assembler-times {\mxxspltidp\M} 5 } } */ -/* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 3 } } */ -/* { dg-final { scan-assembler-not {\mplfd\M} } } */ -/* { dg-final { scan-assembler-not {\mplxsd\M} } } */ +/* { dg-final { scan-assembler-times {\mxxspltidp\M} 5 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c index e9a45d5159d..72504bdfbbd 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c @@ -57,7 +57,4 @@ scalar_float_denorm (void) return 0x1p-149f; /* PLFS. */ } -/* { dg-final { scan-assembler-times {\mxxspltidp\M} 6 } } */ -/* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 1 } } */ -/* { dg-final { scan-assembler-not {\mplfs\M} } } */ -/* { dg-final { scan-assembler-not {\mplxssp\M} } } */ +/* { dg-final { scan-assembler-times {\mxxspltidp\M} 6 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c index d81198b163d..d509459292c 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c @@ -51,16 +51,14 @@ v2df_double_m_inf (void) vector double v2df_double_pi (void) { - return (vector double) { M_PI, M_PI }; /* 2x XXSPLTI32DX. */ + return (vector double) { M_PI, M_PI }; /* PLFD. */ } vector double v2df_double_denorm (void) { - return (vector double) { (double)0x1p-149f, /* XXSPLTIB, */ - (double)0x1p-149f }; /* XXSPLTI32DX. */ + return (vector double) { (double)0x1p-149f, + (double)0x1p-149f }; /* PLFD. */ } -/* { dg-final { scan-assembler-times {\mxxspltidp\M} 5 } } */ -/* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 3 } } */ -/* { dg-final { scan-assembler-not {\mplxv\M} } } */ +/* { dg-final { scan-assembler-times {\mxxspltidp\M} 5 } } */