From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 7810) id 32A66385781D; Tue, 25 May 2021 12:38:11 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 32A66385781D MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Alex Coplan To: gcc-cvs@gcc.gnu.org Subject: [gcc r10-9867] arm: Fix wrong code with MVE V2DImode loads and stores [PR99960] X-Act-Checkin: gcc X-Git-Author: Alex Coplan X-Git-Refname: refs/heads/releases/gcc-10 X-Git-Oldrev: bc59a99c2937f511c22e6f9c4634d9a6efc53b68 X-Git-Newrev: 59eb00c08db6683f6a69e3b9fd2743f00e187951 Message-Id: <20210525123811.32A66385781D@sourceware.org> Date: Tue, 25 May 2021 12:38:11 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 25 May 2021 12:38:11 -0000 https://gcc.gnu.org/g:59eb00c08db6683f6a69e3b9fd2743f00e187951 commit r10-9867-g59eb00c08db6683f6a69e3b9fd2743f00e187951 Author: Alex Coplan Date: Mon May 10 09:46:45 2021 +0100 arm: Fix wrong code with MVE V2DImode loads and stores [PR99960] As the PR shows, we currently miscompile V2DImode loads and stores for MVE. We're currently using 64-bit loads/stores, but need to be using 128-bit vector loads and stores. Fixed thusly. Some intrinsics tests were checking that we (incorrectly) used the 64-bit loads/stores: these have been updated. gcc/ChangeLog: PR target/99960 * config/arm/mve.md (*mve_mov): Simplify output code. Use vldrw.u32 and vstrw.32 for V2D[IF]mode loads and stores. gcc/testsuite/ChangeLog: PR target/99960 * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c: Update now that we're (correctly) using full 128-bit vector loads/stores. * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_s64.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_u64.c: Likewise. * gcc.target/arm/mve/intrinsics/vuninitializedq_int.c: Likewise. * gcc.target/arm/mve/intrinsics/vuninitializedq_int1.c: Likewise. (cherry picked from commit 7596c762137f26f495b53ec93471273887832e31) Diff: --- gcc/config/arm/mve.md | 35 ++++------------------ .../arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c | 4 +-- .../arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c | 4 +-- .../mve/intrinsics/vldrdq_gather_base_wb_z_s64.c | 4 +-- .../mve/intrinsics/vldrdq_gather_base_wb_z_u64.c | 4 +-- .../arm/mve/intrinsics/vuninitializedq_int.c | 3 +- .../arm/mve/intrinsics/vuninitializedq_int1.c | 3 +- 7 files changed, 15 insertions(+), 42 deletions(-) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 7614ec37112..6d84cd47a9b 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -41,44 +41,19 @@ if (which_alternative == 4 || which_alternative == 7) { - rtx ops[2]; - int regno = (which_alternative == 7) - ? REGNO (operands[1]) : REGNO (operands[0]); - - ops[0] = operands[0]; - ops[1] = operands[1]; - if (mode == V2DFmode || mode == V2DImode) - { - if (which_alternative == 7) - { - ops[1] = gen_rtx_REG (DImode, regno); - output_asm_insn ("vstr.64\t%P1, %E0",ops); - } - else - { - ops[0] = gen_rtx_REG (DImode, regno); - output_asm_insn ("vldr.64\t%P0, %E1",ops); - } - } - else if (mode == TImode) + if (mode == V2DFmode || mode == V2DImode || mode == TImode) { if (which_alternative == 7) - output_asm_insn ("vstr.64\t%q1, %E0",ops); + output_asm_insn ("vstrw.32\t%q1, %E0", operands); else - output_asm_insn ("vldr.64\t%q0, %E1",ops); + output_asm_insn ("vldrw.u32\t%q0, %E1",operands); } else { if (which_alternative == 7) - { - ops[1] = gen_rtx_REG (TImode, regno); - output_asm_insn ("vstr.\t%q1, %E0",ops); - } + output_asm_insn ("vstr.\t%q1, %E0", operands); else - { - ops[0] = gen_rtx_REG (TImode, regno); - output_asm_insn ("vldr.\t%q0, %E1",ops); - } + output_asm_insn ("vldr.\t%q0, %E1", operands); } return ""; } diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c index 7420d0198e7..a9b1f81b62d 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c @@ -11,6 +11,6 @@ foo (uint64x2_t * addr) } /* { dg-final { scan-assembler "vldrd.64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */ -/* { dg-final { scan-assembler-times "vldr.64" 1 } } */ -/* { dg-final { scan-assembler-times "vstr.64" 1 } } */ +/* { dg-final { scan-assembler-times "vldrw.u32" 1 } } */ +/* { dg-final { scan-assembler-times "vstrw.32" 1 } } */ /* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c index ebe5b2fd70c..e32a06695ae 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c @@ -11,6 +11,6 @@ foo (uint64x2_t * addr) } /* { dg-final { scan-assembler "vldrd.64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */ -/* { dg-final { scan-assembler-times "vldr.64" 1 } } */ -/* { dg-final { scan-assembler-times "vstr.64" 1 } } */ +/* { dg-final { scan-assembler-times "vldrw.u32" 1 } } */ +/* { dg-final { scan-assembler-times "vstrw.32" 1 } } */ /* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_s64.c index 231a24a1e55..bb06cf88e32 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_s64.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_s64.c @@ -10,6 +10,6 @@ int64x2_t foo (uint64x2_t * addr, mve_pred16_t p) /* { dg-final { scan-assembler "vpst" } } */ /* { dg-final { scan-assembler "vldrdt.u64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */ -/* { dg-final { scan-assembler-times "vldr.64" 1 } } */ -/* { dg-final { scan-assembler-times "vstr.64" 1 } } */ +/* { dg-final { scan-assembler-times "vldrw.u32" 1 } } */ +/* { dg-final { scan-assembler-times "vstrw.32" 1 } } */ /* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_u64.c index b8d9b5c1391..558115d49ef 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_u64.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_u64.c @@ -10,6 +10,6 @@ uint64x2_t foo (uint64x2_t * addr, mve_pred16_t p) /* { dg-final { scan-assembler "vpst" } } */ /* { dg-final { scan-assembler "vldrdt.u64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */ -/* { dg-final { scan-assembler-times "vldr.64" 1 } } */ -/* { dg-final { scan-assembler-times "vstr.64" 1 } } */ +/* { dg-final { scan-assembler-times "vldrw.u32" 1 } } */ +/* { dg-final { scan-assembler-times "vstrw.32" 1 } } */ /* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vuninitializedq_int.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vuninitializedq_int.c index bf6692fe573..cc5e6358bee 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vuninitializedq_int.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vuninitializedq_int.c @@ -27,6 +27,5 @@ foo () /* { dg-final { scan-assembler-times "vstrb.8" 2 } } */ /* { dg-final { scan-assembler-times "vstrh.16" 2 } } */ -/* { dg-final { scan-assembler-times "vstrw.32" 2 } } */ -/* { dg-final { scan-assembler-times "vstr.64" 2 } } */ +/* { dg-final { scan-assembler-times "vstrw.32" 4 } } */ /* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vuninitializedq_int1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vuninitializedq_int1.c index 4f66a07ac29..bfeb52b4dd6 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vuninitializedq_int1.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vuninitializedq_int1.c @@ -28,6 +28,5 @@ foo () /* { dg-final { scan-assembler-times "vstrb.8" 2 } } */ /* { dg-final { scan-assembler-times "vstrh.16" 2 } } */ -/* { dg-final { scan-assembler-times "vstrw.32" 2 } } */ -/* { dg-final { scan-assembler-times "vstr.64" 2 } } */ +/* { dg-final { scan-assembler-times "vstrw.32" 4 } } */ /* { dg-final { scan-assembler-not "__ARM_undef" } } */