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From: Michael Meissner <meissner@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work053)] Generate 128-bit divide/modulus. Date: Tue, 1 Jun 2021 21:45:08 +0000 (GMT) [thread overview] Message-ID: <20210601214508.41D6C3838018@sourceware.org> (raw) https://gcc.gnu.org/g:ebe8a4f31863a06fa35c628092194d293c6f156e commit ebe8a4f31863a06fa35c628092194d293c6f156e Author: Michael Meissner <meissner@linux.ibm.com> Date: Tue Jun 1 17:44:51 2021 -0400 Generate 128-bit divide/modulus. This patch adds support for the VDIVSQ, VDIVUQ, VMODSQ, and VMODUQ instructions to do 128-bit arithmetic. gcc/ 2021-06-01 Michael Meissner <meissner@linux.ibm.com> * config/rs6000/rs6000.md (udivti3): New insn. (divti3): New insn. (umodti3): New insn. (modti3): New insn. gcc/testsuite/ 2021-06-01 Michael Meissner <meissner@linux.ibm.com> * gcc.target/powerpc/p10-vdiv-vmod.c: New test. Diff: --- gcc/config/rs6000/rs6000.md | 34 ++++++++++++++++++++++ gcc/testsuite/gcc.target/powerpc/p10-vdivq-vmodq.c | 27 +++++++++++++++++ 2 files changed, 61 insertions(+) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 1200c4db6a9..86a61706c64 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -3216,6 +3216,14 @@ [(set_attr "type" "div") (set_attr "size" "<bits>")]) +(define_insn "udivti3" + [(set (match_operand:TI 0 "altivec_register_operand" "=v") + (udiv:TI (match_operand:TI 1 "altivec_register_operand" "v") + (match_operand:TI 2 "altivec_register_operand" "v")))] + "TARGET_POWER10 && TARGET_POWERPC64" + "vdivuq %0,%1,%2" + [(set_attr "type" "vecdiv") + (set_attr "size" "128")]) ;; For powers of two we can do sra[wd]i/addze for divide and then adjust for ;; modulus. If it isn't a power of two, force operands into register and do @@ -3306,6 +3314,15 @@ (set_attr "length" "8,12") (set_attr "cell_micro" "not")]) +(define_insn "divti3" + [(set (match_operand:TI 0 "altivec_register_operand" "=v") + (div:TI (match_operand:TI 1 "altivec_register_operand" "v") + (match_operand:TI 2 "altivec_register_operand" "v")))] + "TARGET_POWER10 && TARGET_POWERPC64" + "vdivsq %0,%1,%2" + [(set_attr "type" "vecdiv") + (set_attr "size" "128")]) + (define_expand "mod<mode>3" [(set (match_operand:GPR 0 "gpc_reg_operand") (mod:GPR (match_operand:GPR 1 "gpc_reg_operand") @@ -3406,6 +3423,23 @@ (minus:GPR (match_dup 1) (match_dup 3)))]) +(define_insn "umodti3" + [(set (match_operand:TI 0 "altivec_register_operand" "=v") + (umod:TI (match_operand:TI 1 "altivec_register_operand" "v") + (match_operand:TI 2 "altivec_register_operand" "v")))] + "TARGET_POWER10 && TARGET_POWERPC64" + "vmoduq %0,%1,%2" + [(set_attr "type" "vecdiv") + (set_attr "size" "128")]) + +(define_insn "modti3" + [(set (match_operand:TI 0 "altivec_register_operand" "=v") + (mod:TI (match_operand:TI 1 "altivec_register_operand" "v") + (match_operand:TI 2 "altivec_register_operand" "v")))] + "TARGET_POWER10 && TARGET_POWERPC64" + "vmodsq %0,%1,%2" + [(set_attr "type" "vecdiv") + (set_attr "size" "128")]) \f ;; Logical instructions ;; The logical instructions are mostly combined by using match_operator, diff --git a/gcc/testsuite/gcc.target/powerpc/p10-vdivq-vmodq.c b/gcc/testsuite/gcc.target/powerpc/p10-vdivq-vmodq.c new file mode 100644 index 00000000000..cd29b0a4b6b --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/p10-vdivq-vmodq.c @@ -0,0 +1,27 @@ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target power10_ok } */ +/* { dg-options "-mdejagnu-cpu=power10 -O2" } */ + +unsigned __int128 u_div(unsigned __int128 a, unsigned __int128 b) +{ + return a/b; +} + +unsigned __int128 u_mod(unsigned __int128 a, unsigned __int128 b) +{ + return a%b; +} +__int128 s_div(__int128 a, __int128 b) +{ + return a/b; +} + +__int128 s_mod(__int128 a, __int128 b) +{ + return a%b; +} + +/* { dg-final { scan-assembler {\mvdivsq\M} } } */ +/* { dg-final { scan-assembler {\mvdivuq\M} } } */ +/* { dg-final { scan-assembler {\mvmodsq\M} } } */ +/* { dg-final { scan-assembler {\mvmoduq\M} } } */
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