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From: Aaron Sawdey <acsawdey@gcc.gnu.org>
To: gcc-cvs@gcc.gnu.org
Subject: [gcc r12-1196] Fix operand order to subf for p10 fusion.
Date: Thu, 3 Jun 2021 16:42:43 +0000 (GMT) [thread overview]
Message-ID: <20210603164243.B638E398E413@sourceware.org> (raw)
https://gcc.gnu.org/g:52e130652a76ff3d14c0f572fcd79fa53637ce2c
commit r12-1196-g52e130652a76ff3d14c0f572fcd79fa53637ce2c
Author: Aaron Sawdey <acsawdey@linux.ibm.com>
Date: Wed Jun 2 22:54:08 2021 -0500
Fix operand order to subf for p10 fusion.
This certainly causes a bootstrap miscompare, and might also be
responsible for PR/100820. The operands to subf were reversed
in the logical-add/sub fusion patterns, and I screwed up my
bootstrap test which is how it ended up getting committed.
gcc/ChangeLog
* config/rs6000/genfusion.pl (gen_logical_addsubf): Fix input
order to subf instruction.
* config/rs6000/fusion.md: Regenerate.
Diff:
---
gcc/config/rs6000/fusion.md | 64 +++++++++++++++++++++---------------------
gcc/config/rs6000/genfusion.pl | 20 +++++++------
2 files changed, 43 insertions(+), 41 deletions(-)
diff --git a/gcc/config/rs6000/fusion.md b/gcc/config/rs6000/fusion.md
index 51912106663..e642ff5f95f 100644
--- a/gcc/config/rs6000/fusion.md
+++ b/gcc/config/rs6000/fusion.md
@@ -1733,10 +1733,10 @@
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
"(TARGET_P10_FUSION && TARGET_P10_FUSION_LOGADD)"
"@
- and %3,%1,%0\;subf %3,%3,%2
- and %3,%1,%0\;subf %3,%3,%2
- and %3,%1,%0\;subf %3,%3,%2
- and %4,%1,%0\;subf %3,%4,%2"
+ and %3,%1,%0\;subf %3,%2,%3
+ and %3,%1,%0\;subf %3,%2,%3
+ and %3,%1,%0\;subf %3,%2,%3
+ and %4,%1,%0\;subf %3,%2,%4"
[(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1751,10 +1751,10 @@
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
"(TARGET_P10_FUSION && TARGET_P10_FUSION_LOGADD)"
"@
- nand %3,%1,%0\;subf %3,%3,%2
- nand %3,%1,%0\;subf %3,%3,%2
- nand %3,%1,%0\;subf %3,%3,%2
- nand %4,%1,%0\;subf %3,%4,%2"
+ nand %3,%1,%0\;subf %3,%2,%3
+ nand %3,%1,%0\;subf %3,%2,%3
+ nand %3,%1,%0\;subf %3,%2,%3
+ nand %4,%1,%0\;subf %3,%2,%4"
[(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1769,10 +1769,10 @@
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
"(TARGET_P10_FUSION && TARGET_P10_FUSION_LOGADD)"
"@
- nor %3,%1,%0\;subf %3,%3,%2
- nor %3,%1,%0\;subf %3,%3,%2
- nor %3,%1,%0\;subf %3,%3,%2
- nor %4,%1,%0\;subf %3,%4,%2"
+ nor %3,%1,%0\;subf %3,%2,%3
+ nor %3,%1,%0\;subf %3,%2,%3
+ nor %3,%1,%0\;subf %3,%2,%3
+ nor %4,%1,%0\;subf %3,%2,%4"
[(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1787,10 +1787,10 @@
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
"(TARGET_P10_FUSION && TARGET_P10_FUSION_LOGADD)"
"@
- or %3,%1,%0\;subf %3,%3,%2
- or %3,%1,%0\;subf %3,%3,%2
- or %3,%1,%0\;subf %3,%3,%2
- or %4,%1,%0\;subf %3,%4,%2"
+ or %3,%1,%0\;subf %3,%2,%3
+ or %3,%1,%0\;subf %3,%2,%3
+ or %3,%1,%0\;subf %3,%2,%3
+ or %4,%1,%0\;subf %3,%2,%4"
[(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1805,10 +1805,10 @@
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
"(TARGET_P10_FUSION && TARGET_P10_FUSION_LOGADD)"
"@
- and %3,%1,%0\;subf %3,%2,%3
- and %3,%1,%0\;subf %3,%2,%3
- and %3,%1,%0\;subf %3,%2,%3
- and %4,%1,%0\;subf %3,%2,%4"
+ and %3,%1,%0\;subf %3,%3,%2
+ and %3,%1,%0\;subf %3,%3,%2
+ and %3,%1,%0\;subf %3,%3,%2
+ and %4,%1,%0\;subf %3,%4,%2"
[(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1823,10 +1823,10 @@
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
"(TARGET_P10_FUSION && TARGET_P10_FUSION_LOGADD)"
"@
- nand %3,%1,%0\;subf %3,%2,%3
- nand %3,%1,%0\;subf %3,%2,%3
- nand %3,%1,%0\;subf %3,%2,%3
- nand %4,%1,%0\;subf %3,%2,%4"
+ nand %3,%1,%0\;subf %3,%3,%2
+ nand %3,%1,%0\;subf %3,%3,%2
+ nand %3,%1,%0\;subf %3,%3,%2
+ nand %4,%1,%0\;subf %3,%4,%2"
[(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1841,10 +1841,10 @@
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
"(TARGET_P10_FUSION && TARGET_P10_FUSION_LOGADD)"
"@
- nor %3,%1,%0\;subf %3,%2,%3
- nor %3,%1,%0\;subf %3,%2,%3
- nor %3,%1,%0\;subf %3,%2,%3
- nor %4,%1,%0\;subf %3,%2,%4"
+ nor %3,%1,%0\;subf %3,%3,%2
+ nor %3,%1,%0\;subf %3,%3,%2
+ nor %3,%1,%0\;subf %3,%3,%2
+ nor %4,%1,%0\;subf %3,%4,%2"
[(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1859,10 +1859,10 @@
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
"(TARGET_P10_FUSION && TARGET_P10_FUSION_LOGADD)"
"@
- or %3,%1,%0\;subf %3,%2,%3
- or %3,%1,%0\;subf %3,%2,%3
- or %3,%1,%0\;subf %3,%2,%3
- or %4,%1,%0\;subf %3,%2,%4"
+ or %3,%1,%0\;subf %3,%3,%2
+ or %3,%1,%0\;subf %3,%3,%2
+ or %3,%1,%0\;subf %3,%3,%2
+ or %4,%1,%0\;subf %3,%4,%2"
[(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
diff --git a/gcc/config/rs6000/genfusion.pl b/gcc/config/rs6000/genfusion.pl
index 1285dd42043..577b9553deb 100755
--- a/gcc/config/rs6000/genfusion.pl
+++ b/gcc/config/rs6000/genfusion.pl
@@ -166,7 +166,7 @@ sub gen_logical_addsubf
$outer_op, $outer_comp, $outer_inv, $outer_rtl, $inner, @inner_ops,
$inner_comp, $inner_inv, $inner_rtl, $inner_op, $both_commute, $c4,
$bc, $inner_arg0, $inner_arg1, $inner_exp, $outer_arg2, $outer_exp,
- $target_flag, $ftype, $insn, $is_rsubf, $outer_32, $outer_42,
+ $target_flag, $ftype, $insn, $is_subf, $is_rsubf, $outer_32, $outer_42,
$outer_name, $fuse_type);
KIND: foreach $kind ('scalar','vector') {
@outer_ops = @logicals;
@@ -188,11 +188,10 @@ sub gen_logical_addsubf
$c4 = "${constraint},${constraint},${constraint},${constraint}";
OUTER: foreach $outer ( @outer_ops ) {
$outer_name = "${vchr}${outer}";
- if ( $outer eq "rsubf" ) {
- $is_rsubf = 1;
+ $is_subf = ( $outer eq "subf" );
+ $is_rsubf = ( $outer eq "rsubf" );
+ if ( $is_rsubf ) {
$outer = "subf";
- } else {
- $is_rsubf = 0;
}
$outer_op = "${vchr}${outer}";
$outer_comp = $complement{$outer};
@@ -241,16 +240,19 @@ sub gen_logical_addsubf
if ( ($outer_comp & 2) == 2 ) {
$inner_exp = "(not:${mode} $inner_exp)";
}
+ if ( $is_subf ) {
+ $outer_32 = "%2,%3";
+ $outer_42 = "%2,%4";
+ } else {
+ $outer_32 = "%3,%2";
+ $outer_42 = "%4,%2";
+ }
if ( $is_rsubf == 1 ) {
$outer_exp = "(${outer_rtl}:${mode} ${outer_arg2}
${inner_exp})";
- $outer_32 = "%2,%3";
- $outer_42 = "%2,%4";
} else {
$outer_exp = "(${outer_rtl}:${mode} ${inner_exp}
${outer_arg2})";
- $outer_32 = "%3,%2";
- $outer_42 = "%4,%2";
}
if ( $outer_inv == 1 ) {
$outer_exp = "(not:${mode} $outer_exp)";
reply other threads:[~2021-06-03 16:42 UTC|newest]
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