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From: Michael Meissner <meissner@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work055)] Revert patch. Date: Tue, 8 Jun 2021 02:58:44 +0000 (GMT) [thread overview] Message-ID: <20210608025844.8A570385780D@sourceware.org> (raw) https://gcc.gnu.org/g:bc4b76e491a481c25cb8803055fc213c87831070 commit bc4b76e491a481c25cb8803055fc213c87831070 Author: Michael Meissner <meissner@linux.ibm.com> Date: Mon Jun 7 22:58:08 2021 -0400 Revert patch. gcc/ 2021-06-07 Michael Meissner <meissner@linux.ibm.com> Revert patch. * config/rs6000/rs6000.c (rs6000_emit_minmax): Add support for ISA 3.1 IEEE 128-bit floating point xsmaxcqp and xsmincqp instructions. * config/rs6000/rs6000.md (s<minmax><mode>3, IEEE128 iterator): New insns. gcc/testsuite/ 2021-06-07 Michael Meissner <meissner@linux.ibm.com> Revert patch. * gcc.target/powerpc/float128-minmax-2.c: New test. * gcc.target/powerpc/float128-minmax.c: Do not run on power10. * lib/target-supports.exp (check_effective_target_has_arch_pwr10): New target support. Diff: --- gcc/config/rs6000/rs6000.c | 3 +-- gcc/config/rs6000/rs6000.md | 11 ----------- gcc/testsuite/gcc.target/powerpc/float128-minmax-2.c | 15 --------------- gcc/testsuite/gcc.target/powerpc/float128-minmax.c | 7 ++----- gcc/testsuite/lib/target-supports.exp | 10 ---------- 5 files changed, 3 insertions(+), 43 deletions(-) diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 1651788df6a..b01bb5c8191 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -16103,8 +16103,7 @@ rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1) /* VSX/altivec have direct min/max insns. */ if ((code == SMAX || code == SMIN) && (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) - || (mode == SFmode && VECTOR_UNIT_VSX_P (DFmode)) - || (TARGET_POWER10 && TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)))) + || (mode == SFmode && VECTOR_UNIT_VSX_P (DFmode)))) { emit_insn (gen_rtx_SET (dest, gen_rtx_fmt_ee (code, mode, op0, op1))); return; diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 064c3a2d9d6..3f59b544f6a 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -5214,17 +5214,6 @@ } [(set_attr "type" "fp")]) -;; Min/max for ISA 3.1 IEEE 128-bit floating point -(define_insn "s<minmax><mode>3" - [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") - (fp_minmax:IEEE128 - (match_operand:IEEE128 1 "altivec_register_operand" "v") - (match_operand:IEEE128 2 "altivec_register_operand" "v")))] - "TARGET_POWER10" - "xs<minmax>cqp %0,%1,%2" - [(set_attr "type" "vecfloat") - (set_attr "size" "128")]) - ;; The conditional move instructions allow us to perform max and min operations ;; even when we don't have the appropriate max/min instruction using the FSEL ;; instruction. diff --git a/gcc/testsuite/gcc.target/powerpc/float128-minmax-2.c b/gcc/testsuite/gcc.target/powerpc/float128-minmax-2.c deleted file mode 100644 index c71ba08c9f8..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/float128-minmax-2.c +++ /dev/null @@ -1,15 +0,0 @@ -/* { dg-require-effective-target ppc_float128_hw } */ -/* { dg-require-effective-target power10_ok } */ -/* { dg-options "-mdejagnu-cpu=power10 -O2 -ffast-math" } */ - -#ifndef TYPE -#define TYPE _Float128 -#endif - -/* Test that the fminf128/fmaxf128 functions generate if/then/else and not a - call. */ -TYPE f128_min (TYPE a, TYPE b) { return __builtin_fminf128 (a, b); } -TYPE f128_max (TYPE a, TYPE b) { return __builtin_fmaxf128 (a, b); } - -/* { dg-final { scan-assembler {\mxsmaxcqp\M} } } */ -/* { dg-final { scan-assembler {\mxsmincqp\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/float128-minmax.c b/gcc/testsuite/gcc.target/powerpc/float128-minmax.c index 76bb88b170d..fe397518f2f 100644 --- a/gcc/testsuite/gcc.target/powerpc/float128-minmax.c +++ b/gcc/testsuite/gcc.target/powerpc/float128-minmax.c @@ -1,10 +1,7 @@ /* { dg-do compile { target lp64 } } */ -/* { dg-require-effective-target powerpc_p9vector_ok && ! has_arch_pwr10 } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ /* { dg-require-effective-target float128 } */ -/* { dg-options "-O2 -ffast-math" } */ - -/* We don't run this test on power10 because power10 has instructions to - implement min/max directly. */ +/* { dg-options "-mpower9-vector -O2 -ffast-math" } */ #ifndef TYPE #define TYPE _Float128 diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 789723fb287..7f78c5593ac 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -6127,16 +6127,6 @@ proc check_effective_target_has_arch_pwr9 { } { }] } -proc check_effective_target_has_arch_pwr10 { } { - return [check_no_compiler_messages arch_pwr10 assembly { - #ifndef _ARCH_PWR10 - #error does not have power10 support. - #else - /* "has power10 support" */ - #endif - }] -} - # Return 1 if this is a PowerPC target supporting -mcpu=power10. # Limit this to 64-bit linux systems for now until other targets support # power10.
next reply other threads:[~2021-06-08 2:58 UTC|newest] Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-06-08 2:58 Michael Meissner [this message] -- strict thread matches above, loose matches on Subject: below -- 2021-06-11 22:58 Michael Meissner 2021-06-11 22:17 Michael Meissner 2021-06-10 22:51 Michael Meissner 2021-06-10 20:35 Michael Meissner 2021-06-10 17:03 Michael Meissner 2021-06-09 17:48 Michael Meissner 2021-06-09 15:45 Michael Meissner 2021-06-09 6:04 Michael Meissner 2021-06-09 5:36 Michael Meissner 2021-06-09 5:32 Michael Meissner 2021-06-09 5:28 Michael Meissner 2021-06-08 4:10 Michael Meissner 2021-06-08 3:46 Michael Meissner 2021-06-08 1:04 Michael Meissner
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