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From: Pat Haugen <pthaugen@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc r12-1298] Update Power10 scheduling description for new fused instruction types. Date: Tue, 8 Jun 2021 16:42:53 +0000 (GMT) [thread overview] Message-ID: <20210608164253.DA08B396E846@sourceware.org> (raw) https://gcc.gnu.org/g:69bb37f9e0143fbca3124069c0e9b6937ccf1fc7 commit r12-1298-g69bb37f9e0143fbca3124069c0e9b6937ccf1fc7 Author: Pat Haugen <pthaugen@linux.ibm.com> Date: Tue Jun 8 11:41:55 2021 -0500 Update Power10 scheduling description for new fused instruction types. gcc/ChangeLog: * config/rs6000/power10.md (power10-fused-load, power10-fused-store, power10-fused_alu, power10-fused-vec, power10-fused-branch): New. Diff: --- gcc/config/rs6000/power10.md | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/gcc/config/rs6000/power10.md b/gcc/config/rs6000/power10.md index 665f0f22c62..0186ae95896 100644 --- a/gcc/config/rs6000/power10.md +++ b/gcc/config/rs6000/power10.md @@ -100,6 +100,11 @@ (eq_attr "cpu" "power10")) "DU_any_power10,LU_power10") +(define_insn_reservation "power10-fused-load" 4 + (and (eq_attr "type" "fused_load_cmpi,fused_addis_load,fused_load_load") + (eq_attr "cpu" "power10")) + "DU_even_power10,LU_power10") + (define_insn_reservation "power10-prefixed-load" 4 (and (eq_attr "type" "load") (eq_attr "update" "no") @@ -176,6 +181,11 @@ (eq_attr "cpu" "power10")) "DU_any_power10,STU_power10") +(define_insn_reservation "power10-fused-store" 0 + (and (eq_attr "type" "fused_store_store") + (eq_attr "cpu" "power10")) + "DU_even_power10,STU_power10") + (define_insn_reservation "power10-prefixed-store" 0 (and (eq_attr "type" "store,fpstore,vecstore") (eq_attr "prefixed" "yes") @@ -244,6 +254,11 @@ (define_bypass 4 "power10-alu" "power10-crlogical,power10-mfcr,power10-mfcrf") +(define_insn_reservation "power10-fused_alu" 2 + (and (eq_attr "type" "fused_arith_logical,fused_cmp_isel,fused_carry") + (eq_attr "cpu" "power10")) + "DU_even_power10,EXU_power10") + ; paddi (define_insn_reservation "power10-paddi" 2 (and (eq_attr "type" "add") @@ -403,6 +418,11 @@ (eq_attr "cpu" "power10")) "DU_any_power10,EXU_power10") +(define_insn_reservation "power10-fused-vec" 2 + (and (eq_attr "type" "fused_vector") + (eq_attr "cpu" "power10")) + "DU_even_power10,EXU_power10") + (define_insn_reservation "power10-veccmp" 3 (and (eq_attr "type" "veccmp") (eq_attr "cpu" "power10")) @@ -490,6 +510,11 @@ (eq_attr "cpu" "power10")) "DU_any_power10,STU_power10") +(define_insn_reservation "power10-fused-branch" 3 + (and (eq_attr "type" "fused_mtbc") + (eq_attr "cpu" "power10")) + "DU_even_power10,STU_power10") + ; Crypto (define_insn_reservation "power10-crypto" 4
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